arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2013-2015 Freescale Semiconductor, Inc.
   4  */
   5
   6 #ifndef __ARCH_FSL_LSCH2_IMMAP_H__
   7 #define __ARCH_FSL_LSCH2_IMMAP_H__
   8
   9 #include <fsl_immap.h>
  10 #ifndef __ASSEMBLY__
  11 #include <linux/bitops.h>
  12 #endif
  13
  14 #define CONFIG_SYS_DCSRBAR                      0x20000000
  15 #define CONFIG_SYS_DCSR_DCFG_ADDR       (CONFIG_SYS_DCSRBAR + 0x00140000)
  16 #define CONFIG_SYS_DCSR_COP_CCP_ADDR    (CONFIG_SYS_DCSRBAR + 0x02008040)
  17
  18 #define CONFIG_SYS_FSL_DDR_ADDR                 (CONFIG_SYS_IMMR + 0x00080000)
  19 #define CONFIG_SYS_GIC400_ADDR                  (CONFIG_SYS_IMMR + 0x00400000)
  20 #define CONFIG_SYS_IFC_ADDR                     (CONFIG_SYS_IMMR + 0x00530000)
  21 #define SYS_FSL_QSPI_ADDR                       (CONFIG_SYS_IMMR + 0x00550000)
  22 #define CONFIG_SYS_FSL_ESDHC_ADDR               (CONFIG_SYS_IMMR + 0x00560000)
  23 #define CONFIG_SYS_FSL_CSU_ADDR                 (CONFIG_SYS_IMMR + 0x00510000)
  24 #define CONFIG_SYS_FSL_GUTS_ADDR                (CONFIG_SYS_IMMR + 0x00ee0000)
  25 #define CONFIG_SYS_FSL_RST_ADDR                 (CONFIG_SYS_IMMR + 0x00ee00b0)
  26 #define CONFIG_SYS_FSL_SCFG_ADDR                (CONFIG_SYS_IMMR + 0x00570000)
  27 #define CONFIG_SYS_FSL_BMAN_ADDR                (CONFIG_SYS_IMMR + 0x00890000)
  28 #define CONFIG_SYS_FSL_QMAN_ADDR                (CONFIG_SYS_IMMR + 0x00880000)
  29 #define CONFIG_SYS_FSL_FMAN_ADDR                (CONFIG_SYS_IMMR + 0x00a00000)
  30 #define CONFIG_SYS_FSL_SERDES_ADDR              (CONFIG_SYS_IMMR + 0x00ea0000)
  31 #define CONFIG_SYS_FSL_DCFG_ADDR                (CONFIG_SYS_IMMR + 0x00ee0000)
  32 #define CONFIG_SYS_FSL_CLK_ADDR                 (CONFIG_SYS_IMMR + 0x00ee1000)
  33 #define CONFIG_SYS_NS16550_COM1                 (CONFIG_SYS_IMMR + 0x011c0500)
  34 #define CONFIG_SYS_NS16550_COM2                 (CONFIG_SYS_IMMR + 0x011c0600)
  35 #define CONFIG_SYS_NS16550_COM3                 (CONFIG_SYS_IMMR + 0x011d0500)
  36 #define CONFIG_SYS_NS16550_COM4                 (CONFIG_SYS_IMMR + 0x011d0600)
  37 #define CONFIG_SYS_XHCI_USB1_ADDR               (CONFIG_SYS_IMMR + 0x01f00000)
  38 #define CONFIG_SYS_XHCI_USB2_ADDR               (CONFIG_SYS_IMMR + 0x02000000)
  39 #define CONFIG_SYS_XHCI_USB3_ADDR               (CONFIG_SYS_IMMR + 0x02100000)
  40 #define CONFIG_SYS_EHCI_USB1_ADDR               (CONFIG_SYS_IMMR + 0x07600000)
  41 #define CONFIG_SYS_PCIE1_ADDR                   (CONFIG_SYS_IMMR + 0x2400000)
  42 #define CONFIG_SYS_PCIE2_ADDR                   (CONFIG_SYS_IMMR + 0x2500000)
  43 #define CONFIG_SYS_PCIE3_ADDR                   (CONFIG_SYS_IMMR + 0x2600000)
  44 #define CONFIG_SYS_SEC_MON_ADDR                 (CONFIG_SYS_IMMR + 0xe90000)
  45 #define CONFIG_SYS_SFP_ADDR                     (CONFIG_SYS_IMMR + 0xe80200)
  46
  47 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
  48 #define CONFIG_SYS_BMAN_MEM_BASE        0x508000000
  49 #define CONFIG_SYS_BMAN_MEM_PHYS        (0xf00000000ull + \
  50                                                 CONFIG_SYS_BMAN_MEM_BASE)
  51 #define CONFIG_SYS_BMAN_MEM_SIZE        0x08000000
  52 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x10000
  53 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x10000
  54 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
  55 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  56 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
  57                                         CONFIG_SYS_BMAN_CENA_SIZE)
  58 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  59 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0x3E80
  60 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
  61 #define CONFIG_SYS_QMAN_MEM_BASE        0x500000000
  62 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
  63 #define CONFIG_SYS_QMAN_MEM_SIZE        0x08000000
  64 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x10000
  65 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x10000
  66 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
  67 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  68 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
  69                                         CONFIG_SYS_QMAN_CENA_SIZE)
  70 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  71 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0x3680
  72
  73 #define CONFIG_SYS_FSL_TIMER_ADDR               0x02b00000
  74
  75 #define I2C1_BASE_ADDR                          (CONFIG_SYS_IMMR + 0x01180000)
  76 #define I2C2_BASE_ADDR                          (CONFIG_SYS_IMMR + 0x01190000)
  77 #define I2C3_BASE_ADDR                          (CONFIG_SYS_IMMR + 0x011a0000)
  78 #define I2C4_BASE_ADDR                          (CONFIG_SYS_IMMR + 0x011b0000)
  79
  80 #define WDOG1_BASE_ADDR                         (CONFIG_SYS_IMMR + 0x01ad0000)
  81
  82 #define QSPI0_BASE_ADDR                         (CONFIG_SYS_IMMR + 0x00550000)
  83 #define DSPI1_BASE_ADDR                         (CONFIG_SYS_IMMR + 0x01100000)
  84
  85 #define GPIO1_BASE_ADDR                         (CONFIG_SYS_IMMR + 0x1300000)
  86 #define GPIO2_BASE_ADDR                         (CONFIG_SYS_IMMR + 0x1310000)
  87 #define GPIO3_BASE_ADDR                         (CONFIG_SYS_IMMR + 0x1320000)
  88 #define GPIO4_BASE_ADDR                         (CONFIG_SYS_IMMR + 0x1330000)
  89
  90 #define QE_BASE_ADDR                            (CONFIG_SYS_IMMR + 0x1400000)
  91
  92 #define LPUART_BASE                             (CONFIG_SYS_IMMR + 0x01950000)
  93
  94 #define EDMA_BASE_ADDR                          (CONFIG_SYS_IMMR + 0x01c00000)
  95
  96 #define AHCI_BASE_ADDR                          (CONFIG_SYS_IMMR + 0x02200000)
  97
  98 #define QDMA_BASE_ADDR                          (CONFIG_SYS_IMMR + 0x07380000)
  99 #define QMAN_CQSIDR_REG                         0x20a80
 100
 101 #define CONFIG_SYS_PCIE1_PHYS_ADDR              0x4000000000ULL
 102 #define CONFIG_SYS_PCIE2_PHYS_ADDR              0x4800000000ULL
 103 #define CONFIG_SYS_PCIE3_PHYS_ADDR              0x5000000000ULL
 104 /* LUT registers */
 105 #ifdef CONFIG_ARCH_LS1012A
 106 #define PCIE_LUT_BASE                           0xC0000
 107 #else
 108 #define PCIE_LUT_BASE                           0x10000
 109 #endif
 110 #define PCIE_LUT_LCTRL0                         0x7F8
 111 #define PCIE_LUT_DBG                            0x7FC
 112
 113 /* TZ Address Space Controller Definitions */
 114 #define TZASC1_BASE                     0x01100000      /* as per CCSR map. */
 115 #define TZASC2_BASE                     0x01110000      /* as per CCSR map. */
 116 #define TZASC3_BASE                     0x01120000      /* as per CCSR map. */
 117 #define TZASC4_BASE                     0x01130000      /* as per CCSR map. */
 118 #define TZASC_BUILD_CONFIG_REG(x)       ((TZASC1_BASE + (x * 0x10000)))
 119 #define TZASC_ACTION_REG(x)             ((TZASC1_BASE + (x * 0x10000)) + 0x004)
 120 #define TZASC_GATE_KEEPER(x)            ((TZASC1_BASE + (x * 0x10000)) + 0x008)
 121 #define TZASC_REGION_BASE_LOW_0(x)      ((TZASC1_BASE + (x * 0x10000)) + 0x100)
 122 #define TZASC_REGION_BASE_HIGH_0(x)     ((TZASC1_BASE + (x * 0x10000)) + 0x104)
 123 #define TZASC_REGION_TOP_LOW_0(x)       ((TZASC1_BASE + (x * 0x10000)) + 0x108)
 124 #define TZASC_REGION_TOP_HIGH_0(x)      ((TZASC1_BASE + (x * 0x10000)) + 0x10C)
 125 #define TZASC_REGION_ATTRIBUTES_0(x)    ((TZASC1_BASE + (x * 0x10000)) + 0x110)
 126 #define TZASC_REGION_ID_ACCESS_0(x)     ((TZASC1_BASE + (x * 0x10000)) + 0x114)
 127
 128 #define TP_ITYP_AV              0x00000001      /* Initiator available */
 129 #define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1)      /* Initiator Type */
 130 #define TP_ITYP_TYPE_ARM        0x0
 131 #define TP_ITYP_TYPE_PPC        0x1             /* PowerPC */
 132 #define TP_ITYP_TYPE_OTHER      0x2             /* StarCore DSP */
 133 #define TP_ITYP_TYPE_HA         0x3             /* HW Accelerator */
 134 #define TP_ITYP_THDS(x) (((x) & 0x18) >> 3)     /* # threads */
 135 #define TP_ITYP_VER(x)  (((x) & 0xe0) >> 5)     /* Initiator Version */
 136 #define TY_ITYP_VER_A7          0x1
 137 #define TY_ITYP_VER_A53         0x2
 138 #define TY_ITYP_VER_A57         0x3
 139 #define TY_ITYP_VER_A72         0x4
 140
 141 #define TP_CLUSTER_EOC          0xc0000000      /* end of clusters */
 142 #define TP_CLUSTER_INIT_MASK    0x0000003f      /* initiator mask */
 143 #define TP_INIT_PER_CLUSTER     4
 144
 145 #ifndef CONFIG_SYS_CCSRBAR
 146 #define CONFIG_SYS_CCSRBAR              0x01000000
 147 #endif
 148
 149 #ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH
 150 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH    0
 151 #endif
 152
 153 #ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW
 154 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     0x01000000
 155 #endif
 156
 157 #define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
 158                                  CONFIG_SYS_CCSRBAR_PHYS_LOW)
 159
 160 struct sys_info {
 161         unsigned long freq_processor[CONFIG_MAX_CPUS];
 162         /* frequency of platform PLL */
 163         unsigned long freq_systembus;
 164         unsigned long freq_ddrbus;
 165         unsigned long freq_localbus;
 166         unsigned long freq_cga_m2;
 167 #ifdef CONFIG_SYS_DPAA_FMAN
 168         unsigned long freq_fman[CONFIG_SYS_NUM_FMAN];
 169 #endif
 170         unsigned long freq_qman;
 171 };
 172
 173 #define CONFIG_SYS_FSL_FM1_OFFSET               0xa00000
 174 #define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET        0xa88000
 175 #define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET        0xa89000
 176 #define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET        0xa8a000
 177 #define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET        0xa8b000
 178 #define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET        0xa8c000
 179 #define CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET        0xa8d000
 180
 181 #define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET        0xae0000
 182 #define CONFIG_SYS_FSL_FM1_ADDR                 \
 183                 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET)
 184 #define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR          \
 185                 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET)
 186
 187 #define CONFIG_SYS_FSL_SEC_OFFSET               0x700000ull
 188 #define CONFIG_SYS_FSL_JR0_OFFSET               0x710000ull
 189 #define FSL_SEC_JR0_OFFSET                      CONFIG_SYS_FSL_JR0_OFFSET
 190 #define FSL_SEC_JR1_OFFSET                      0x720000ull
 191 #define FSL_SEC_JR2_OFFSET                      0x730000ull
 192 #define FSL_SEC_JR3_OFFSET                      0x740000ull
 193 #define CONFIG_SYS_FSL_SEC_ADDR \
 194         (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
 195 #define CONFIG_SYS_FSL_JR0_ADDR \
 196         (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
 197 #define FSL_SEC_JR0_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR0_OFFSET)
 198 #define FSL_SEC_JR1_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR1_OFFSET)
 199 #define FSL_SEC_JR2_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR2_OFFSET)
 200 #define FSL_SEC_JR3_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR3_OFFSET)
 201
 202 /* Device Configuration and Pin Control */
 203 #define DCFG_DCSR_PORCR1                0x0
 204 #define DCFG_DCSR_ECCCR2                0x524
 205 #define DISABLE_PFE_ECC                 BIT(13)
 206
 207 struct ccsr_gur {
 208         u32     porsr1;         /* POR status 1 */
 209 #define FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK       0xFF800000
 210         u32     porsr2;         /* POR status 2 */
 211         u8      res_008[0x20-0x8];
 212         u32     gpporcr1;       /* General-purpose POR configuration */
 213         u32     gpporcr2;
 214 #define FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT      25
 215 #define FSL_CHASSIS2_DCFG_FUSESR_VID_MASK       0x1F
 216 #define FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT   20
 217 #define FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK    0x1F
 218         u32     dcfg_fusesr;    /* Fuse status register */
 219         u8      res_02c[0x70-0x2c];
 220         u32     devdisr;        /* Device disable control */
 221 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_1  0x80000000
 222 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_2  0x40000000
 223 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_3  0x20000000
 224 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_4  0x10000000
 225 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_5  0x08000000
 226 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_6  0x04000000
 227 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_9  0x00800000
 228 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_10 0x00400000
 229 #define FSL_CHASSIS2_DEVDISR2_10GEC1_1  0x00800000
 230 #define FSL_CHASSIS2_DEVDISR2_10GEC1_2  0x00400000
 231 #define FSL_CHASSIS2_DEVDISR2_10GEC1_3  0x80000000
 232 #define FSL_CHASSIS2_DEVDISR2_10GEC1_4  0x40000000
 233         u32     devdisr2;       /* Device disable control 2 */
 234         u32     devdisr3;       /* Device disable control 3 */
 235         u32     devdisr4;       /* Device disable control 4 */
 236         u32     devdisr5;       /* Device disable control 5 */
 237         u32     devdisr6;       /* Device disable control 6 */
 238         u32     devdisr7;       /* Device disable control 7 */
 239         u8      res_08c[0x94-0x8c];
 240         u32     coredisru;      /* uppper portion for support of 64 cores */
 241         u32     coredisrl;      /* lower portion for support of 64 cores */
 242         u8      res_09c[0xa0-0x9c];
 243         u32     pvr;            /* Processor version */
 244         u32     svr;            /* System version */
 245         u32     mvr;            /* Manufacturing version */
 246         u8      res_0ac[0xb0-0xac];
 247         u32     rstcr;          /* Reset control */
 248         u32     rstrqpblsr;     /* Reset request preboot loader status */
 249         u8      res_0b8[0xc0-0xb8];
 250         u32     rstrqmr1;       /* Reset request mask */
 251         u8      res_0c4[0xc8-0xc4];
 252         u32     rstrqsr1;       /* Reset request status */
 253         u8      res_0cc[0xd4-0xcc];
 254         u32     rstrqwdtmrl;    /* Reset request WDT mask */
 255         u8      res_0d8[0xdc-0xd8];
 256         u32     rstrqwdtsrl;    /* Reset request WDT status */
 257         u8      res_0e0[0xe4-0xe0];
 258         u32     brrl;           /* Boot release */
 259         u8      res_0e8[0x100-0xe8];
 260         u32     rcwsr[16];      /* Reset control word status */
 261 #define FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT   25
 262 #define FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK    0x1f
 263 #define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT   16
 264 #define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK    0x3f
 265 #define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK    0xffff0000
 266 #define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT   16
 267 #define FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK    0x0000ffff
 268 #define FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT   0
 269 #define RCW_SB_EN_REG_INDEX     7
 270 #define RCW_SB_EN_MASK          0x00200000
 271
 272         u8      res_140[0x200-0x140];
 273         u32     scratchrw[4];  /* Scratch Read/Write */
 274         u8      res_210[0x300-0x210];
 275         u32     scratchw1r[4];  /* Scratch Read (Write once) */
 276         u8      res_310[0x400-0x310];
 277         u32     crstsr[12];
 278         u8      res_430[0x500-0x430];
 279
 280         /* PCI Express n Logical I/O Device Number register */
 281         u32 dcfg_ccsr_pex1liodnr;
 282         u32 dcfg_ccsr_pex2liodnr;
 283         u32 dcfg_ccsr_pex3liodnr;
 284         u32 dcfg_ccsr_pex4liodnr;
 285         /* RIO n Logical I/O Device Number register */
 286         u32 dcfg_ccsr_rio1liodnr;
 287         u32 dcfg_ccsr_rio2liodnr;
 288         u32 dcfg_ccsr_rio3liodnr;
 289         u32 dcfg_ccsr_rio4liodnr;
 290         /* USB Logical I/O Device Number register */
 291         u32 dcfg_ccsr_usb1liodnr;
 292         u32 dcfg_ccsr_usb2liodnr;
 293         u32 dcfg_ccsr_usb3liodnr;
 294         u32 dcfg_ccsr_usb4liodnr;
 295         /* SD/MMC Logical I/O Device Number register */
 296         u32 dcfg_ccsr_sdmmc1liodnr;
 297         u32 dcfg_ccsr_sdmmc2liodnr;
 298         u32 dcfg_ccsr_sdmmc3liodnr;
 299         u32 dcfg_ccsr_sdmmc4liodnr;
 300         /* RIO Message Unit Logical I/O Device Number register */
 301         u32 dcfg_ccsr_riomaintliodnr;
 302
 303         u8      res_544[0x550-0x544];
 304         u32     sataliodnr[4];
 305         u8      res_560[0x570-0x560];
 306
 307         u32 dcfg_ccsr_misc1liodnr;
 308         u32 dcfg_ccsr_misc2liodnr;
 309         u32 dcfg_ccsr_misc3liodnr;
 310         u32 dcfg_ccsr_misc4liodnr;
 311         u32 dcfg_ccsr_dma1liodnr;
 312         u32 dcfg_ccsr_dma2liodnr;
 313         u32 dcfg_ccsr_dma3liodnr;
 314         u32 dcfg_ccsr_dma4liodnr;
 315         u32 dcfg_ccsr_spare1liodnr;
 316         u32 dcfg_ccsr_spare2liodnr;
 317         u32 dcfg_ccsr_spare3liodnr;
 318         u32 dcfg_ccsr_spare4liodnr;
 319         u8      res_5a0[0x600-0x5a0];
 320         u32 dcfg_ccsr_pblsr;
 321
 322         u32     pamubypenr;
 323         u32     dmacr1;
 324
 325         u8      res_60c[0x610-0x60c];
 326         u32 dcfg_ccsr_gensr1;
 327         u32 dcfg_ccsr_gensr2;
 328         u32 dcfg_ccsr_gensr3;
 329         u32 dcfg_ccsr_gensr4;
 330         u32 dcfg_ccsr_gencr1;
 331         u32 dcfg_ccsr_gencr2;
 332         u32 dcfg_ccsr_gencr3;
 333         u32 dcfg_ccsr_gencr4;
 334         u32 dcfg_ccsr_gencr5;
 335         u32 dcfg_ccsr_gencr6;
 336         u32 dcfg_ccsr_gencr7;
 337         u8      res_63c[0x658-0x63c];
 338         u32 dcfg_ccsr_cgensr1;
 339         u32 dcfg_ccsr_cgensr0;
 340         u8      res_660[0x678-0x660];
 341         u32 dcfg_ccsr_cgencr1;
 342
 343         u32 dcfg_ccsr_cgencr0;
 344         u8      res_680[0x700-0x680];
 345         u32 dcfg_ccsr_sriopstecr;
 346         u32 dcfg_ccsr_dcsrcr;
 347
 348         u8      res_708[0x740-0x708];   /* add more registers when needed */
 349         u32     tp_ityp[64];    /* Topology Initiator Type Register */
 350         struct {
 351                 u32     upper;
 352                 u32     lower;
 353         } tp_cluster[16];
 354         u8      res_8c0[0xa00-0x8c0];   /* add more registers when needed */
 355         u32 dcfg_ccsr_qmbm_warmrst;
 356         u8      res_a04[0xa20-0xa04];   /* add more registers when needed */
 357         u32 dcfg_ccsr_reserved0;
 358         u32 dcfg_ccsr_reserved1;
 359 };
 360
 361 #define SCFG_QSPI_CLKSEL                0x40100000
 362 #define SCFG_USBDRVVBUS_SELCR_USB1      0x00000000
 363 #define SCFG_USBDRVVBUS_SELCR_USB2      0x00000001
 364 #define SCFG_USBDRVVBUS_SELCR_USB3      0x00000002
 365 #define SCFG_USBPWRFAULT_INACTIVE       0x00000000
 366 #define SCFG_USBPWRFAULT_SHARED         0x00000001
 367 #define SCFG_USBPWRFAULT_DEDICATED      0x00000002
 368 #define SCFG_USBPWRFAULT_USB3_SHIFT     4
 369 #define SCFG_USBPWRFAULT_USB2_SHIFT     2
 370 #define SCFG_USBPWRFAULT_USB1_SHIFT     0
 371
 372 #define SCFG_BASE                       0x01570000
 373 #define SCFG_USB3PRM1CR_USB1            0x070
 374 #define SCFG_USB3PRM2CR_USB1            0x074
 375 #define SCFG_USB3PRM1CR_USB2            0x07C
 376 #define SCFG_USB3PRM2CR_USB2            0x080
 377 #define SCFG_USB3PRM1CR_USB3            0x088
 378 #define SCFG_USB3PRM2CR_USB3            0x08c
 379 #define SCFG_USB_TXVREFTUNE                     0x9
 380 #define SCFG_USB_SQRXTUNE_MASK          0x7
 381 #define SCFG_USB_PCSTXSWINGFULL         0x47
 382 #define SCFG_USB_PHY1                   0x084F0000
 383 #define SCFG_USB_PHY2                   0x08500000
 384 #define SCFG_USB_PHY3                   0x08510000
 385 #define SCFG_USB_PHY_RX_OVRD_IN_HI              0x200c
 386 #define USB_PHY_RX_EQ_VAL_1             0x0000
 387 #define USB_PHY_RX_EQ_VAL_2             0x0080
 388 #define USB_PHY_RX_EQ_VAL_3             0x0380
 389 #define USB_PHY_RX_EQ_VAL_4             0x0b80
 390
 391 #define SCFG_SNPCNFGCR_SECRDSNP         0x80000000
 392 #define SCFG_SNPCNFGCR_SECWRSNP         0x40000000
 393 #define SCFG_SNPCNFGCR_SATARDSNP        0x00800000
 394 #define SCFG_SNPCNFGCR_SATAWRSNP        0x00400000
 395 #define SCFG_SNPCNFGCR_USB1RDSNP        0x00200000
 396 #define SCFG_SNPCNFGCR_USB1WRSNP        0x00100000
 397 #define SCFG_SNPCNFGCR_USB2RDSNP        0x00008000
 398 #define SCFG_SNPCNFGCR_USB2WRSNP        0x00010000
 399 #define SCFG_SNPCNFGCR_USB3RDSNP        0x00002000
 400 #define SCFG_SNPCNFGCR_USB3WRSNP        0x00004000
 401
 402 /* RGMIIPCR bit definitions*/
 403 #define SCFG_RGMIIPCR_EN_AUTO           BIT(3)
 404 #define SCFG_RGMIIPCR_SETSP_1000M       BIT(2)
 405 #define SCFG_RGMIIPCR_SETSP_100M        0
 406 #define SCFG_RGMIIPCR_SETSP_10M         BIT(1)
 407 #define SCFG_RGMIIPCR_SETFD             BIT(0)
 408
 409 /* PFEASBCR bit definitions */
 410 #define SCFG_PFEASBCR_ARCACHE0          BIT(31)
 411 #define SCFG_PFEASBCR_AWCACHE0          BIT(30)
 412 #define SCFG_PFEASBCR_ARCACHE1          BIT(29)
 413 #define SCFG_PFEASBCR_AWCACHE1          BIT(28)
 414 #define SCFG_PFEASBCR_ARSNP             BIT(27)
 415 #define SCFG_PFEASBCR_AWSNP             BIT(26)
 416
 417 /* WR_QoS1 PFE bit definitions */
 418 #define SCFG_WR_QOS1_PFE1_QOS           GENMASK(27, 24)
 419 #define SCFG_WR_QOS1_PFE2_QOS           GENMASK(23, 20)
 420
 421 /* RD_QoS1 PFE bit definitions */
 422 #define SCFG_RD_QOS1_PFE1_QOS           GENMASK(27, 24)
 423 #define SCFG_RD_QOS1_PFE2_QOS           GENMASK(23, 20)
 424
 425 /* Supplemental Configuration Unit */
 426 struct ccsr_scfg {
 427         u8 res_000[0x100-0x000];
 428         u32 usb2_icid;
 429         u32 usb3_icid;
 430         u8 res_108[0x114-0x108];
 431         u32 dma_icid;
 432         u32 sata_icid;
 433         u32 usb1_icid;
 434         u32 qe_icid;
 435         u32 sdhc_icid;
 436         u32 edma_icid;
 437         u32 etr_icid;
 438         u32 core_sft_rst[4];
 439         u8 res_140[0x158-0x140];
 440         u32 altcbar;
 441         u32 qspi_cfg;
 442         u8 res_160[0x164 - 0x160];
 443         u32 wr_qos1;
 444         u32 wr_qos2;
 445         u32 rd_qos1;
 446         u32 rd_qos2;
 447         u8 res_174[0x180 - 0x174];
 448         u32 dmamcr;
 449         u8 res_184[0x188-0x184];
 450         u32 gic_align;
 451         u32 debug_icid;
 452         u8 res_190[0x1a4-0x190];
 453         u32 snpcnfgcr;
 454         u8 res_1a8[0x1ac-0x1a8];
 455         u32 intpcr;
 456         u8 res_1b0[0x204-0x1b0];
 457         u32 coresrencr;
 458         u8 res_208[0x220-0x208];
 459         u32 rvbar0_0;
 460         u32 rvbar0_1;
 461         u32 rvbar1_0;
 462         u32 rvbar1_1;
 463         u32 rvbar2_0;
 464         u32 rvbar2_1;
 465         u32 rvbar3_0;
 466         u32 rvbar3_1;
 467         u32 lpmcsr;
 468         u8 res_244[0x400-0x244];
 469         u32 qspidqscr;
 470         u32 ecgtxcmcr;
 471         u32 sdhciovselcr;
 472         u32 rcwpmuxcr0;
 473         u32 usbdrvvbus_selcr;
 474         u32 usbpwrfault_selcr;
 475         u32 usb_refclk_selcr1;
 476         u32 usb_refclk_selcr2;
 477         u32 usb_refclk_selcr3;
 478         u8 res_424[0x434 - 0x424];
 479         u32 rgmiipcr;
 480         u32 res_438;
 481         u32 rgmiipsr;
 482         u32 pfepfcssr1;
 483         u32 pfeintencr1;
 484         u32 pfepfcssr2;
 485         u32 pfeintencr2;
 486         u32 pfeerrcr;
 487         u32 pfeeerrintencr;
 488         u32 pfeasbcr;
 489         u32 pfebsbcr;
 490         u8 res_460[0x484 - 0x460];
 491         u32 mdioselcr;
 492         u8 res_468[0x600 - 0x488];
 493         u32 scratchrw[4];
 494         u8 res_610[0x680-0x610];
 495         u32 corebcr;
 496         u8 res_684[0x1000-0x684];
 497         u32 pex1msiir;
 498         u32 pex1msir;
 499         u8 res_1008[0x2000-0x1008];
 500         u32 pex2;
 501         u32 pex2msir;
 502         u8 res_2008[0x3000-0x2008];
 503         u32 pex3msiir;
 504         u32 pex3msir;
 505 };
 506
 507 /* Clocking */
 508 struct ccsr_clk {
 509         struct {
 510                 u32 clkcncsr;   /* core cluster n clock control status */
 511                 u8  res_004[0x0c];
 512                 u32 clkcghwacsr; /* Clock generator n hardware accelerator */
 513                 u8  res_014[0x0c];
 514         } clkcsr[4];
 515         u8      res_040[0x780]; /* 0x100 */
 516         struct {
 517                 u32 pllcngsr;
 518                 u8 res_804[0x1c];
 519         } pllcgsr[2];
 520         u8      res_840[0x1c0];
 521         u32     clkpcsr;        /* 0xa00 Platform clock domain control/status */
 522         u8      res_a04[0x1fc];
 523         u32     pllpgsr;        /* 0xc00 Platform PLL General Status */
 524         u8      res_c04[0x1c];
 525         u32     plldgsr;        /* 0xc20 DDR PLL General Status */
 526         u8      res_c24[0x3dc];
 527 };
 528
 529 /* System Counter */
 530 struct sctr_regs {
 531         u32 cntcr;
 532         u32 cntsr;
 533         u32 cntcv1;
 534         u32 cntcv2;
 535         u32 resv1[4];
 536         u32 cntfid0;
 537         u32 cntfid1;
 538         u32 resv2[1002];
 539         u32 counterid[12];
 540 };
 541
 542 #define SRDS_MAX_LANES          4
 543 struct ccsr_serdes {
 544         struct {
 545                 u32     rstctl; /* Reset Control Register */
 546 #define SRDS_RSTCTL_RST         0x80000000
 547 #define SRDS_RSTCTL_RSTDONE     0x40000000
 548 #define SRDS_RSTCTL_RSTERR      0x20000000
 549 #define SRDS_RSTCTL_SWRST       0x10000000
 550 #define SRDS_RSTCTL_SDEN        0x00000020
 551 #define SRDS_RSTCTL_SDRST_B     0x00000040
 552 #define SRDS_RSTCTL_PLLRST_B    0x00000080
 553                 u32     pllcr0; /* PLL Control Register 0 */
 554 #define SRDS_PLLCR0_POFF                0x80000000
 555 #define SRDS_PLLCR0_RFCK_SEL_MASK       0x70000000
 556 #define SRDS_PLLCR0_RFCK_SEL_100        0x00000000
 557 #define SRDS_PLLCR0_RFCK_SEL_125        0x10000000
 558 #define SRDS_PLLCR0_RFCK_SEL_156_25     0x20000000
 559 #define SRDS_PLLCR0_RFCK_SEL_150        0x30000000
 560 #define SRDS_PLLCR0_RFCK_SEL_161_13     0x40000000
 561 #define SRDS_PLLCR0_RFCK_SEL_122_88     0x50000000
 562 #define SRDS_PLLCR0_PLL_LCK             0x00800000
 563 #define SRDS_PLLCR0_FRATE_SEL_MASK      0x000f0000
 564 #define SRDS_PLLCR0_FRATE_SEL_5         0x00000000
 565 #define SRDS_PLLCR0_FRATE_SEL_3_75      0x00050000
 566 #define SRDS_PLLCR0_FRATE_SEL_5_15      0x00060000
 567 #define SRDS_PLLCR0_FRATE_SEL_4         0x00070000
 568 #define SRDS_PLLCR0_FRATE_SEL_3_12      0x00090000
 569 #define SRDS_PLLCR0_FRATE_SEL_3         0x000a0000
 570                 u32     pllcr1; /* PLL Control Register 1 */
 571 #define SRDS_PLLCR1_PLL_BWSEL   0x08000000
 572                 u32     res_0c; /* 0x00c */
 573                 u32     pllcr3;
 574                 u32     pllcr4;
 575                 u32     pllcr5; /* 0x018 SerDes PLL1 Control 5 */
 576                 u8      res_1c[0x20-0x1c];
 577         } bank[2];
 578         u8      res_40[0x90-0x40];
 579         u32     srdstcalcr;     /* 0x90 TX Calibration Control */
 580         u8      res_94[0xa0-0x94];
 581         u32     srdsrcalcr;     /* 0xa0 RX Calibration Control */
 582         u8      res_a4[0xb0-0xa4];
 583         u32     srdsgr0;        /* 0xb0 General Register 0 */
 584         u8      res_b4[0x100-0xb4];
 585         struct {
 586                 u32     lnpssr0;        /* 0x100, 0x120, 0x140, 0x160 */
 587                 u8      res_104[0x120-0x104];
 588         } lnpssr[4];    /* Lane A, B, C, D */
 589         u8      res_180[0x200-0x180];
 590         u32     srdspccr0;      /* 0x200 Protocol Configuration 0 */
 591         u32     srdspccr1;      /* 0x204 Protocol Configuration 1 */
 592         u32     srdspccr2;      /* 0x208 Protocol Configuration 2 */
 593         u32     srdspccr3;      /* 0x20c Protocol Configuration 3 */
 594         u32     srdspccr4;      /* 0x210 Protocol Configuration 4 */
 595         u32     srdspccr5;      /* 0x214 Protocol Configuration 5 */
 596         u32     srdspccr6;      /* 0x218 Protocol Configuration 6 */
 597         u32     srdspccr7;      /* 0x21c Protocol Configuration 7 */
 598         u32     srdspccr8;      /* 0x220 Protocol Configuration 8 */
 599         u32     srdspccr9;      /* 0x224 Protocol Configuration 9 */
 600         u32     srdspccra;      /* 0x228 Protocol Configuration A */
 601         u32     srdspccrb;      /* 0x22c Protocol Configuration B */
 602         u8      res_230[0x800-0x230];
 603         struct {
 604                 u32     gcr0;   /* 0x800 General Control Register 0 */
 605                 u32     gcr1;   /* 0x804 General Control Register 1 */
 606                 u32     gcr2;   /* 0x808 General Control Register 2 */
 607                 u32     sscr0;
 608                 u32     recr0;  /* 0x810 Receive Equalization Control */
 609                 u32     recr1;
 610                 u32     tecr0;  /* 0x818 Transmit Equalization Control */
 611                 u32     sscr1;
 612                 u32     ttlcr0; /* 0x820 Transition Tracking Loop Ctrl 0 */
 613                 u8      res_824[0x83c-0x824];
 614                 u32     tcsr3;
 615         } lane[4];      /* Lane A, B, C, D */
 616         u8      res_900[0x1000-0x900];  /* from 0x900 to 0xfff */
 617         struct {
 618                 u32     srdspexcr0;     /* 0x1000, 0x1040, 0x1080 */
 619                 u8      res_1004[0x1040-0x1004];
 620         } pcie[3];
 621         u8      res_10c0[0x1800-0x10c0];
 622         struct {
 623                 u8      res_1800[0x1804-0x1800];
 624                 u32     srdssgmiicr1;   /* 0x1804 SGMII Protocol Control 1 */
 625                 u8      res_1808[0x180c-0x1808];
 626                 u32     srdssgmiicr3;   /* 0x180c SGMII Protocol Control 3 */
 627         } sgmii[4];     /* Lane A, B, C, D */
 628         u8      res_1840[0x1880-0x1840];
 629         struct {
 630                 u8      res_1880[0x1884-0x1880];
 631                 u32     srdsqsgmiicr1;  /* 0x1884 QSGMII Protocol Control 1 */
 632                 u8      res_1888[0x188c-0x1888];
 633                 u32     srdsqsgmiicr3;  /* 0x188c QSGMII Protocol Control 3 */
 634         } qsgmii[2];    /* Lane A, B */
 635         u8      res_18a0[0x1980-0x18a0];
 636         struct {
 637                 u8      res_1980[0x1984-0x1980];
 638                 u32     srdsxficr1;     /* 0x1984 XFI Protocol Control 1 */
 639                 u8      res_1988[0x198c-0x1988];
 640                 u32     srdsxficr3;     /* 0x198c XFI Protocol Control 3 */
 641         } xfi[2];       /* Lane A, B */
 642         u8      res_19a0[0x2000-0x19a0];        /* from 0x19a0 to 0x1fff */
 643 };
 644
 645 struct ccsr_gpio {
 646         u32     gpdir;
 647         u32     gpodr;
 648         u32     gpdat;
 649         u32     gpier;
 650         u32     gpimr;
 651         u32     gpicr;
 652         u32     gpibe;
 653 };
 654
 655 /* MMU 500 */
 656 #define SMMU_SCR0                       (SMMU_BASE + 0x0)
 657 #define SMMU_SCR1                       (SMMU_BASE + 0x4)
 658 #define SMMU_SCR2                       (SMMU_BASE + 0x8)
 659 #define SMMU_SACR                       (SMMU_BASE + 0x10)
 660 #define SMMU_IDR0                       (SMMU_BASE + 0x20)
 661 #define SMMU_IDR1                       (SMMU_BASE + 0x24)
 662
 663 #define SMMU_NSCR0                      (SMMU_BASE + 0x400)
 664 #define SMMU_NSCR2                      (SMMU_BASE + 0x408)
 665 #define SMMU_NSACR                      (SMMU_BASE + 0x410)
 666
 667 #define SCR0_CLIENTPD_MASK              0x00000001
 668 #define SCR0_USFCFG_MASK                0x00000400
 669
 670 #ifdef CONFIG_TFABOOT
 671 #define RCW_SRC_MASK                    (0xFF800000)
 672 #define RCW_SRC_BIT                     23
 673
 674 /* RCW SRC NAND */
 675 #define RCW_SRC_NAND_MASK               (0x100)
 676 #define RCW_SRC_NAND_VAL                (0x100)
 677 #define NAND_RESERVED_MASK              (0xFC)
 678 #define NAND_RESERVED_1                 (0x0)
 679 #define NAND_RESERVED_2                 (0x80)
 680
 681 /* RCW SRC NOR */
 682 #define RCW_SRC_NOR_MASK                (0x1F0)
 683 #define NOR_8B_VAL                      (0x10)
 684 #define NOR_16B_VAL                     (0x20)
 685 #define SD_VAL                          (0x40)
 686 #define QSPI_VAL1                       (0x44)
 687 #define QSPI_VAL2                       (0x45)
 688 #endif
 689
 690 uint get_svr(void);
 691
 692 #endif  /* __ARCH_FSL_LSCH2_IMMAP_H__*/