arch/arm/include/asm/arch-fsl-layerscape/cpu.h

   1 /*
   2  * Copyright 2017 NXP
   3  * Copyright 2014-2015, Freescale Semiconductor
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #ifndef _FSL_LAYERSCAPE_CPU_H
   9 #define _FSL_LAYERSCAPE_CPU_H
  10
  11 static struct cpu_type cpu_type_list[] = {
  12         CPU_TYPE_ENTRY(LS2080A, LS2080A, 8),
  13         CPU_TYPE_ENTRY(LS2085A, LS2085A, 8),
  14         CPU_TYPE_ENTRY(LS2045A, LS2045A, 4),
  15         CPU_TYPE_ENTRY(LS2088A, LS2088A, 8),
  16         CPU_TYPE_ENTRY(LS2084A, LS2084A, 8),
  17         CPU_TYPE_ENTRY(LS2048A, LS2048A, 4),
  18         CPU_TYPE_ENTRY(LS2044A, LS2044A, 4),
  19         CPU_TYPE_ENTRY(LS2081A, LS2081A, 8),
  20         CPU_TYPE_ENTRY(LS2041A, LS2041A, 4),
  21         CPU_TYPE_ENTRY(LS1043A, LS1043A, 4),
  22         CPU_TYPE_ENTRY(LS1023A, LS1023A, 2),
  23         CPU_TYPE_ENTRY(LS1046A, LS1046A, 4),
  24         CPU_TYPE_ENTRY(LS1026A, LS1026A, 2),
  25         CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
  26         CPU_TYPE_ENTRY(LS1012A, LS1012A, 1),
  27         CPU_TYPE_ENTRY(LS1088A, LS1088A, 8),
  28         CPU_TYPE_ENTRY(LS1084A, LS1084A, 8),
  29         CPU_TYPE_ENTRY(LS1048A, LS1048A, 4),
  30         CPU_TYPE_ENTRY(LS1044A, LS1044A, 4),
  31 };
  32
  33 #ifndef CONFIG_SYS_DCACHE_OFF
  34
  35 #ifdef CONFIG_FSL_LSCH3
  36 #define CONFIG_SYS_FSL_CCSR_BASE        0x00000000
  37 #define CONFIG_SYS_FSL_CCSR_SIZE        0x10000000
  38 #define CONFIG_SYS_FSL_QSPI_BASE1       0x20000000
  39 #define CONFIG_SYS_FSL_QSPI_SIZE1       0x10000000
  40 #define CONFIG_SYS_FSL_IFC_BASE1        0x30000000
  41 #define CONFIG_SYS_FSL_IFC_SIZE1        0x10000000
  42 #define CONFIG_SYS_FSL_IFC_SIZE1_1      0x400000
  43 #define CONFIG_SYS_FSL_DRAM_BASE1       0x80000000
  44 #define CONFIG_SYS_FSL_DRAM_SIZE1       0x80000000
  45 #define CONFIG_SYS_FSL_QSPI_BASE2       0x400000000
  46 #define CONFIG_SYS_FSL_QSPI_SIZE2       0x100000000
  47 #define CONFIG_SYS_FSL_IFC_BASE2        0x500000000
  48 #define CONFIG_SYS_FSL_IFC_SIZE2        0x100000000
  49 #define CONFIG_SYS_FSL_DCSR_BASE        0x700000000
  50 #define CONFIG_SYS_FSL_DCSR_SIZE        0x40000000
  51 #define CONFIG_SYS_FSL_MC_BASE          0x80c000000
  52 #define CONFIG_SYS_FSL_MC_SIZE          0x4000000
  53 #define CONFIG_SYS_FSL_NI_BASE          0x810000000
  54 #define CONFIG_SYS_FSL_NI_SIZE          0x8000000
  55 #define CONFIG_SYS_FSL_QBMAN_BASE       0x818000000
  56 #define CONFIG_SYS_FSL_QBMAN_SIZE       0x8000000
  57 #define CONFIG_SYS_FSL_QBMAN_SIZE_1     0x4000000
  58 #define CONFIG_SYS_PCIE1_PHYS_SIZE      0x200000000
  59 #define CONFIG_SYS_PCIE2_PHYS_SIZE      0x200000000
  60 #define CONFIG_SYS_PCIE3_PHYS_SIZE      0x200000000
  61 #define CONFIG_SYS_PCIE4_PHYS_SIZE      0x200000000
  62 #define CONFIG_SYS_FSL_WRIOP1_BASE      0x4300000000
  63 #define CONFIG_SYS_FSL_WRIOP1_SIZE      0x100000000
  64 #define CONFIG_SYS_FSL_AIOP1_BASE       0x4b00000000
  65 #define CONFIG_SYS_FSL_AIOP1_SIZE       0x100000000
  66 #define CONFIG_SYS_FSL_PEBUF_BASE       0x4c00000000
  67 #define CONFIG_SYS_FSL_PEBUF_SIZE       0x400000000
  68 #define CONFIG_SYS_FSL_DRAM_BASE2       0x8080000000
  69 #define CONFIG_SYS_FSL_DRAM_SIZE2       0x7F80000000
  70 #elif defined(CONFIG_FSL_LSCH2)
  71 #define CONFIG_SYS_FSL_BOOTROM_BASE     0x0
  72 #define CONFIG_SYS_FSL_BOOTROM_SIZE     0x1000000
  73 #define CONFIG_SYS_FSL_CCSR_BASE        0x1000000
  74 #define CONFIG_SYS_FSL_CCSR_SIZE        0xf000000
  75 #define CONFIG_SYS_FSL_DCSR_BASE        0x20000000
  76 #define CONFIG_SYS_FSL_DCSR_SIZE        0x4000000
  77 #define CONFIG_SYS_FSL_QSPI_BASE        0x40000000
  78 #define CONFIG_SYS_FSL_QSPI_SIZE        0x20000000
  79 #define CONFIG_SYS_FSL_IFC_BASE         0x60000000
  80 #define CONFIG_SYS_FSL_IFC_SIZE         0x20000000
  81 #define CONFIG_SYS_FSL_DRAM_BASE1       0x80000000
  82 #define CONFIG_SYS_FSL_DRAM_SIZE1       0x80000000
  83 #define CONFIG_SYS_FSL_QBMAN_BASE       0x500000000
  84 #define CONFIG_SYS_FSL_QBMAN_SIZE       0x10000000
  85 #define CONFIG_SYS_FSL_DRAM_BASE2       0x880000000
  86 #define CONFIG_SYS_FSL_DRAM_SIZE2       0x780000000     /* 30GB */
  87 #define CONFIG_SYS_PCIE1_PHYS_SIZE      0x800000000
  88 #define CONFIG_SYS_PCIE2_PHYS_SIZE      0x800000000
  89 #define CONFIG_SYS_PCIE3_PHYS_SIZE      0x800000000
  90 #define CONFIG_SYS_FSL_DRAM_BASE3       0x8800000000
  91 #define CONFIG_SYS_FSL_DRAM_SIZE3       0x7800000000    /* 480GB */
  92 #endif
  93
  94 #define EARLY_PGTABLE_SIZE 0x5000
  95 static struct mm_region early_map[] = {
  96 #ifdef CONFIG_FSL_LSCH3
  97         { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
  98           CONFIG_SYS_FSL_CCSR_SIZE,
  99           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 100           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 101         },
 102         { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
 103           SYS_FSL_OCRAM_SPACE_SIZE,
 104           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
 105         },
 106         { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
 107           CONFIG_SYS_FSL_QSPI_SIZE1,
 108           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE},
 109         /* For IFC Region #1, only the first 4MB is cache-enabled */
 110         { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
 111           CONFIG_SYS_FSL_IFC_SIZE1_1,
 112           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
 113         },
 114         { CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
 115           CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
 116           CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1,
 117           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 118         },
 119         { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
 120           CONFIG_SYS_FSL_IFC_SIZE1,
 121           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 122         },
 123         { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
 124           CONFIG_SYS_FSL_DRAM_SIZE1,
 125 #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
 126           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 127 #else   /* Start with nGnRnE and PXN and UXN to prevent speculative access */
 128           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
 129 #endif
 130           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 131         },
 132         /* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */
 133         { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
 134           CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2,
 135           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 136         },
 137         { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
 138           CONFIG_SYS_FSL_DCSR_SIZE,
 139           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 140           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 141         },
 142         { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
 143           CONFIG_SYS_FSL_DRAM_SIZE2,
 144           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
 145           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 146         },
 147 #elif defined(CONFIG_FSL_LSCH2)
 148         { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
 149           CONFIG_SYS_FSL_CCSR_SIZE,
 150           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 151           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 152         },
 153         { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
 154           SYS_FSL_OCRAM_SPACE_SIZE,
 155           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
 156         },
 157         { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
 158           CONFIG_SYS_FSL_DCSR_SIZE,
 159           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 160           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 161         },
 162         { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
 163           CONFIG_SYS_FSL_QSPI_SIZE,
 164           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 165         },
 166         { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
 167           CONFIG_SYS_FSL_IFC_SIZE,
 168           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 169         },
 170         { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
 171           CONFIG_SYS_FSL_DRAM_SIZE1,
 172 #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
 173           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 174 #else   /* Start with nGnRnE and PXN and UXN to prevent speculative access */
 175           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
 176 #endif
 177           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 178         },
 179         { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
 180           CONFIG_SYS_FSL_DRAM_SIZE2,
 181           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
 182           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 183         },
 184 #endif
 185         {},     /* list terminator */
 186 };
 187
 188 static struct mm_region final_map[] = {
 189 #ifdef CONFIG_FSL_LSCH3
 190         { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
 191           CONFIG_SYS_FSL_CCSR_SIZE,
 192           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 193           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 194         },
 195         { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
 196           SYS_FSL_OCRAM_SPACE_SIZE,
 197           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
 198         },
 199         { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
 200           CONFIG_SYS_FSL_DRAM_SIZE1,
 201           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 202           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 203         },
 204         { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
 205           CONFIG_SYS_FSL_QSPI_SIZE1,
 206           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 207           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 208         },
 209         { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
 210           CONFIG_SYS_FSL_QSPI_SIZE2,
 211           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 212           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 213         },
 214         { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
 215           CONFIG_SYS_FSL_IFC_SIZE2,
 216           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 217           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 218         },
 219         { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
 220           CONFIG_SYS_FSL_DCSR_SIZE,
 221           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 222           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 223         },
 224         { CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE,
 225           CONFIG_SYS_FSL_MC_SIZE,
 226           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 227           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 228         },
 229         { CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE,
 230           CONFIG_SYS_FSL_NI_SIZE,
 231           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 232           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 233         },
 234         /* For QBMAN portal, only the first 64MB is cache-enabled */
 235         { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
 236           CONFIG_SYS_FSL_QBMAN_SIZE_1,
 237           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 238           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_NS
 239         },
 240         { CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
 241           CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
 242           CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1,
 243           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 244           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 245         },
 246         { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
 247           CONFIG_SYS_PCIE1_PHYS_SIZE,
 248           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 249           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 250         },
 251         { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
 252           CONFIG_SYS_PCIE2_PHYS_SIZE,
 253           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 254           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 255         },
 256         { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
 257           CONFIG_SYS_PCIE3_PHYS_SIZE,
 258           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 259           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 260         },
 261 #ifdef CONFIG_ARCH_LS2080A
 262         { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
 263           CONFIG_SYS_PCIE4_PHYS_SIZE,
 264           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 265           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 266         },
 267 #endif
 268         { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE,
 269           CONFIG_SYS_FSL_WRIOP1_SIZE,
 270           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 271           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 272         },
 273         { CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE,
 274           CONFIG_SYS_FSL_AIOP1_SIZE,
 275           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 276           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 277         },
 278         { CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE,
 279           CONFIG_SYS_FSL_PEBUF_SIZE,
 280           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 281           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 282         },
 283         { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
 284           CONFIG_SYS_FSL_DRAM_SIZE2,
 285           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 286           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 287         },
 288 #elif defined(CONFIG_FSL_LSCH2)
 289         { CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE,
 290           CONFIG_SYS_FSL_BOOTROM_SIZE,
 291           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 292           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 293         },
 294         { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
 295           CONFIG_SYS_FSL_CCSR_SIZE,
 296           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 297           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 298         },
 299         { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
 300           SYS_FSL_OCRAM_SPACE_SIZE,
 301           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
 302         },
 303         { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
 304           CONFIG_SYS_FSL_DCSR_SIZE,
 305           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 306           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 307         },
 308         { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
 309           CONFIG_SYS_FSL_QSPI_SIZE,
 310           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 311           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 312         },
 313         { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
 314           CONFIG_SYS_FSL_IFC_SIZE,
 315           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 316         },
 317         { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
 318           CONFIG_SYS_FSL_DRAM_SIZE1,
 319           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 320           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 321         },
 322         { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
 323           CONFIG_SYS_FSL_QBMAN_SIZE,
 324           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 325           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 326         },
 327         { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
 328           CONFIG_SYS_FSL_DRAM_SIZE2,
 329           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 330           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 331         },
 332         { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
 333           CONFIG_SYS_PCIE1_PHYS_SIZE,
 334           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 335           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 336         },
 337         { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
 338           CONFIG_SYS_PCIE2_PHYS_SIZE,
 339           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 340           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 341         },
 342         { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
 343           CONFIG_SYS_PCIE3_PHYS_SIZE,
 344           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 345           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 346         },
 347         { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
 348           CONFIG_SYS_FSL_DRAM_SIZE3,
 349           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 350           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 351         },
 352 #endif
 353 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
 354         {},     /* space holder for secure mem */
 355 #endif
 356         {},
 357 };
 358 #endif  /* !CONFIG_SYS_DCACHE_OFF */
 359
 360 int fsl_qoriq_core_to_cluster(unsigned int core);
 361 u32 cpu_mask(void);
 362
 363 #endif /* _FSL_LAYERSCAPE_CPU_H */