1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2016-2018 NXP
4 * Copyright 2015, Freescale Semiconductor
7 #ifndef _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_
8 #define _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_
10 #include <linux/kconfig.h>
11 #include <fsl_ddrc_version.h>
13 #define CONFIG_STANDALONE_LOAD_ADDR 0x80300000
16 * Reserve secure memory
17 * To be aligned with MMU block size
19 #define CONFIG_SYS_MEM_RESERVE_SECURE (66 * 1024 * 1024) /* 66MB */
20 #define SPL_TLB_SETBACK 0x1000000 /* 16MB under effective memory top */
22 #ifdef CONFIG_ARCH_LS2080A
23 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 }
24 #define SRDS_MAX_LANES 8
25 #define CONFIG_SYS_PAGE_SIZE 0x10000
26 #ifndef L1_CACHE_BYTES
27 #define L1_CACHE_SHIFT 6
28 #define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT)
29 #define CONFIG_FSL_TZASC_400
32 #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
33 #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
34 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
37 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
38 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
40 #define CONFIG_SYS_FSL_CCSR_GUR_LE
41 #define CONFIG_SYS_FSL_CCSR_SCFG_LE
42 #define CONFIG_SYS_FSL_ESDHC_LE
43 #define CONFIG_SYS_FSL_IFC_LE
44 #define CONFIG_SYS_FSL_PEX_LUT_LE
46 #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
48 /* Generic Interrupt Controller Definitions */
49 #define GICD_BASE 0x06000000
50 #define GICR_BASE 0x06100000
53 #define SMMU_BASE 0x05000000 /* GR0 Base */
56 #define CONFIG_SYS_FSL_SFP_VER_3_4
57 #define CONFIG_SYS_FSL_SFP_LE
58 #define CONFIG_SYS_FSL_SRK_LE
60 /* Security Monitor */
61 #define CONFIG_SYS_FSL_SEC_MON_LE
64 #define CONFIG_ESBC_HDR_LS
67 #define CONFIG_SYS_FSL_CCSR_GUR_LE
69 /* Cache Coherent Interconnect */
70 #define CCI_MN_BASE 0x04000000
71 #define CCI_MN_RNF_NODEID_LIST 0x180
72 #define CCI_MN_DVM_DOMAIN_CTL 0x200
73 #define CCI_MN_DVM_DOMAIN_CTL_SET 0x210
75 #define CCI_HN_F_0_BASE (CCI_MN_BASE + 0x200000)
76 #define CCI_HN_F_1_BASE (CCI_MN_BASE + 0x210000)
77 #define CCN_HN_F_SAM_CTL 0x8 /* offset on base HN_F base */
78 #define CCN_HN_F_SAM_NODEID_MASK 0x7f
79 #define CCN_HN_F_SAM_NODEID_DDR0 0x4
80 #define CCN_HN_F_SAM_NODEID_DDR1 0xe
82 #define CCI_RN_I_0_BASE (CCI_MN_BASE + 0x800000)
83 #define CCI_RN_I_2_BASE (CCI_MN_BASE + 0x820000)
84 #define CCI_RN_I_6_BASE (CCI_MN_BASE + 0x860000)
85 #define CCI_RN_I_12_BASE (CCI_MN_BASE + 0x8C0000)
86 #define CCI_RN_I_16_BASE (CCI_MN_BASE + 0x900000)
87 #define CCI_RN_I_20_BASE (CCI_MN_BASE + 0x940000)
89 #define CCI_S0_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x10)
90 #define CCI_S1_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x110)
91 #define CCI_S2_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x210)
93 #define CCI_AUX_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x0500)
95 /* TZ Protection Controller Definitions */
96 #define TZPC_BASE 0x02200000
97 #define TZPCR0SIZE_BASE (TZPC_BASE)
98 #define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800)
99 #define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
100 #define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808)
101 #define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C)
102 #define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810)
103 #define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814)
104 #define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818)
105 #define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C)
106 #define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820)
108 #define DCSR_CGACRE5 0x700070914ULL
109 #define EPU_EPCMPR5 0x700060914ULL
110 #define EPU_EPCCR5 0x700060814ULL
111 #define EPU_EPSMCR5 0x700060228ULL
112 #define EPU_EPECR5 0x700060314ULL
113 #define EPU_EPCTR5 0x700060a14ULL
114 #define EPU_EPGCR 0x700060000ULL
116 #define CONFIG_SYS_FSL_ERRATUM_A008751
118 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
120 #elif defined(CONFIG_ARCH_LS1088A)
121 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3
122 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
124 #define CONFIG_FSL_TZPC_BP147
125 #define CONFIG_FSL_TZASC_400
126 #define CONFIG_SYS_PAGE_SIZE 0x10000
128 #define SRDS_MAX_LANES 4
130 /* TZ Protection Controller Definitions */
131 #define TZPC_BASE 0x02200000
132 #define TZPCR0SIZE_BASE (TZPC_BASE)
133 #define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800)
134 #define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
135 #define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808)
136 #define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C)
137 #define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810)
138 #define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814)
139 #define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818)
140 #define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C)
141 #define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820)
143 /* Generic Interrupt Controller Definitions */
144 #define GICD_BASE 0x06000000
145 #define GICR_BASE 0x06100000
147 /* SMMU Defintions */
148 #define SMMU_BASE 0x05000000 /* GR0 Base */
151 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
152 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
154 #define CONFIG_SYS_FSL_CCSR_GUR_LE
155 #define CONFIG_SYS_FSL_CCSR_SCFG_LE
156 #define CONFIG_SYS_FSL_ESDHC_LE
157 #define CONFIG_SYS_FSL_IFC_LE
158 #define CONFIG_SYS_FSL_PEX_LUT_LE
160 #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
163 #define CONFIG_SYS_FSL_SFP_VER_3_4
164 #define CONFIG_SYS_FSL_SFP_LE
165 #define CONFIG_SYS_FSL_SRK_LE
167 /* Security Monitor */
168 #define CONFIG_SYS_FSL_SEC_MON_LE
171 #define CONFIG_ESBC_HDR_LS
174 #define CONFIG_SYS_FSL_CCSR_GUR_LE
175 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
176 #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
177 #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
178 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
180 /* LX2160A Soc Support */
181 #elif defined(CONFIG_ARCH_LX2160A)
182 #define TZPC_BASE 0x02200000
183 #define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
184 #define CONFIG_SYS_I2C
185 #define CONFIG_SYS_I2C_EARLY_INIT
186 #define SRDS_MAX_LANES 8
187 #ifndef L1_CACHE_BYTES
188 #define L1_CACHE_SHIFT 6
189 #define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT)
191 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2
192 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1, 4, 4, 4, 4 }
193 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4
195 #define CONFIG_SYS_PAGE_SIZE 0x10000
197 #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
198 #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
199 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */
202 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
203 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
205 #define CONFIG_SYS_FSL_CCSR_GUR_LE
206 #define CONFIG_SYS_FSL_CCSR_SCFG_LE
207 #define CONFIG_SYS_FSL_ESDHC_LE
208 #define CONFIG_SYS_FSL_PEX_LUT_LE
210 #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
212 /* Generic Interrupt Controller Definitions */
213 #define GICD_BASE 0x06000000
214 #define GICR_BASE 0x06200000
216 /* SMMU Definitions */
217 #define SMMU_BASE 0x05000000 /* GR0 Base */
220 #define CONFIG_SYS_FSL_SFP_VER_3_4
221 #define CONFIG_SYS_FSL_SFP_LE
222 #define CONFIG_SYS_FSL_SRK_LE
224 /* Security Monitor */
225 #define CONFIG_SYS_FSL_SEC_MON_LE
228 #define CONFIG_ESBC_HDR_LS
231 #define CONFIG_SYS_FSL_CCSR_GUR_LE
233 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
235 #elif defined(CONFIG_FSL_LSCH2)
236 #define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */
237 #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
238 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
240 #define DCSR_DCFG_SBEESR2 0x20140534
241 #define DCSR_DCFG_MBEESR2 0x20140544
243 #define CONFIG_SYS_FSL_CCSR_SCFG_BE
244 #define CONFIG_SYS_FSL_ESDHC_BE
245 #define CONFIG_SYS_FSL_WDOG_BE
246 #define CONFIG_SYS_FSL_DSPI_BE
247 #define CONFIG_SYS_FSL_QSPI_BE
248 #define CONFIG_SYS_FSL_CCSR_GUR_BE
249 #define CONFIG_SYS_FSL_PEX_LUT_BE
252 #ifdef CONFIG_ARCH_LS1043A
253 #define CONFIG_SYS_FMAN_V3
254 #define CONFIG_SYS_FSL_QMAN_V3
255 #define CONFIG_SYS_NUM_FMAN 1
256 #define CONFIG_SYS_NUM_FM1_DTSEC 7
257 #define CONFIG_SYS_NUM_FM1_10GEC 1
258 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
259 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
261 #define QE_MURAM_SIZE 0x6000UL
262 #define MAX_QE_RISC 1
263 #define QE_NUM_OF_SNUM 28
265 #define CONFIG_SYS_FSL_IFC_BE
266 #define CONFIG_SYS_FSL_SFP_VER_3_2
267 #define CONFIG_SYS_FSL_SEC_MON_BE
268 #define CONFIG_SYS_FSL_SFP_BE
269 #define CONFIG_SYS_FSL_SRK_LE
270 #define CONFIG_KEY_REVOCATION
272 /* SMMU Defintions */
273 #define SMMU_BASE 0x09000000
275 /* Generic Interrupt Controller Definitions */
276 #define GICD_BASE 0x01401000
277 #define GICC_BASE 0x01402000
278 #define GICH_BASE 0x01404000
279 #define GICV_BASE 0x01406000
280 #define GICD_SIZE 0x1000
281 #define GICC_SIZE 0x2000
282 #define GICH_SIZE 0x2000
283 #define GICV_SIZE 0x2000
284 #ifdef CONFIG_HAS_FEATURE_GIC64K_ALIGN
285 #define GICD_BASE_64K 0x01410000
286 #define GICC_BASE_64K 0x01420000
287 #define GICH_BASE_64K 0x01440000
288 #define GICV_BASE_64K 0x01460000
289 #define GICD_SIZE_64K 0x10000
290 #define GICC_SIZE_64K 0x20000
291 #define GICH_SIZE_64K 0x20000
292 #define GICV_SIZE_64K 0x20000
295 #define DCFG_CCSR_SVR 0x1ee00a4
298 #define GIC_ADDR_BIT 31
299 #define SCFG_GIC400_ALIGN 0x1570188
301 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
303 #elif defined(CONFIG_ARCH_LS1012A)
304 #define GICD_BASE 0x01401000
305 #define GICC_BASE 0x01402000
306 #define CONFIG_SYS_FSL_SFP_VER_3_2
307 #define CONFIG_SYS_FSL_SEC_MON_BE
308 #define CONFIG_SYS_FSL_SFP_BE
309 #define CONFIG_SYS_FSL_SRK_LE
310 #define CONFIG_KEY_REVOCATION
311 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
312 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
313 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
315 #elif defined(CONFIG_ARCH_LS1046A)
316 #define CONFIG_SYS_FMAN_V3
317 #define CONFIG_SYS_FSL_QMAN_V3
318 #define CONFIG_SYS_NUM_FMAN 1
319 #define CONFIG_SYS_NUM_FM1_DTSEC 8
320 #define CONFIG_SYS_NUM_FM1_10GEC 2
321 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
322 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
324 #define CONFIG_SYS_FSL_IFC_BE
325 #define CONFIG_SYS_FSL_SFP_VER_3_2
326 #define CONFIG_SYS_FSL_SEC_MON_BE
327 #define CONFIG_SYS_FSL_SFP_BE
328 #define CONFIG_SYS_FSL_SRK_LE
329 #define CONFIG_KEY_REVOCATION
331 /* SMMU Defintions */
332 #define SMMU_BASE 0x09000000
334 /* Generic Interrupt Controller Definitions */
335 #define GICD_BASE 0x01410000
336 #define GICC_BASE 0x01420000
338 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
340 #error SoC not defined
344 #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ */