1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2016-2018 NXP
4 * Copyright 2015, Freescale Semiconductor
7 #ifndef _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_
8 #define _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_
10 #include <linux/kconfig.h>
11 #include <fsl_ddrc_version.h>
13 #define CONFIG_STANDALONE_LOAD_ADDR 0x80300000
16 * Reserve secure memory
17 * To be aligned with MMU block size
19 #define CONFIG_SYS_MEM_RESERVE_SECURE (66 * 1024 * 1024) /* 66MB */
20 #define SPL_TLB_SETBACK 0x1000000 /* 16MB under effective memory top */
22 #ifdef CONFIG_ARCH_LS2080A
23 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 }
24 #define SRDS_MAX_LANES 8
25 #define CONFIG_SYS_PAGE_SIZE 0x10000
26 #ifndef L1_CACHE_BYTES
27 #define L1_CACHE_SHIFT 6
28 #define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT)
31 #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
32 #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
33 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
36 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
37 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
39 #define CONFIG_SYS_FSL_CCSR_GUR_LE
40 #define CONFIG_SYS_FSL_CCSR_SCFG_LE
41 #define CONFIG_SYS_FSL_ESDHC_LE
42 #define CONFIG_SYS_FSL_IFC_LE
43 #define CONFIG_SYS_FSL_PEX_LUT_LE
45 #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
47 /* Generic Interrupt Controller Definitions */
48 #define GICD_BASE 0x06000000
49 #define GICR_BASE 0x06100000
52 #define SMMU_BASE 0x05000000 /* GR0 Base */
55 #define CONFIG_SYS_FSL_SFP_VER_3_4
56 #define CONFIG_SYS_FSL_SFP_LE
57 #define CONFIG_SYS_FSL_SRK_LE
59 /* Security Monitor */
60 #define CONFIG_SYS_FSL_SEC_MON_LE
63 #define CONFIG_ESBC_HDR_LS
66 #define CONFIG_SYS_FSL_CCSR_GUR_LE
68 /* Cache Coherent Interconnect */
69 #define CCI_MN_BASE 0x04000000
70 #define CCI_MN_RNF_NODEID_LIST 0x180
71 #define CCI_MN_DVM_DOMAIN_CTL 0x200
72 #define CCI_MN_DVM_DOMAIN_CTL_SET 0x210
74 #define CCI_HN_F_0_BASE (CCI_MN_BASE + 0x200000)
75 #define CCI_HN_F_1_BASE (CCI_MN_BASE + 0x210000)
76 #define CCN_HN_F_SAM_CTL 0x8 /* offset on base HN_F base */
77 #define CCN_HN_F_SAM_NODEID_MASK 0x7f
78 #define CCN_HN_F_SAM_NODEID_DDR0 0x4
79 #define CCN_HN_F_SAM_NODEID_DDR1 0xe
81 #define CCI_RN_I_0_BASE (CCI_MN_BASE + 0x800000)
82 #define CCI_RN_I_2_BASE (CCI_MN_BASE + 0x820000)
83 #define CCI_RN_I_6_BASE (CCI_MN_BASE + 0x860000)
84 #define CCI_RN_I_12_BASE (CCI_MN_BASE + 0x8C0000)
85 #define CCI_RN_I_16_BASE (CCI_MN_BASE + 0x900000)
86 #define CCI_RN_I_20_BASE (CCI_MN_BASE + 0x940000)
88 #define CCI_S0_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x10)
89 #define CCI_S1_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x110)
90 #define CCI_S2_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x210)
92 #define CCI_AUX_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x0500)
94 /* TZ Protection Controller Definitions */
95 #define TZPC_BASE 0x02200000
96 #define TZPCR0SIZE_BASE (TZPC_BASE)
97 #define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800)
98 #define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
99 #define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808)
100 #define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C)
101 #define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810)
102 #define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814)
103 #define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818)
104 #define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C)
105 #define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820)
107 #define DCSR_CGACRE5 0x700070914ULL
108 #define EPU_EPCMPR5 0x700060914ULL
109 #define EPU_EPCCR5 0x700060814ULL
110 #define EPU_EPSMCR5 0x700060228ULL
111 #define EPU_EPECR5 0x700060314ULL
112 #define EPU_EPCTR5 0x700060a14ULL
113 #define EPU_EPGCR 0x700060000ULL
115 #define CONFIG_SYS_FSL_ERRATUM_A008751
117 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
119 #elif defined(CONFIG_ARCH_LS1088A)
120 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3
121 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
123 #define CONFIG_SYS_PAGE_SIZE 0x10000
125 #define SRDS_MAX_LANES 4
126 #define SRDS_BITS_PER_LANE 4
128 /* TZ Protection Controller Definitions */
129 #define TZPC_BASE 0x02200000
130 #define TZPCR0SIZE_BASE (TZPC_BASE)
131 #define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800)
132 #define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
133 #define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808)
134 #define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C)
135 #define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810)
136 #define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814)
137 #define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818)
138 #define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C)
139 #define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820)
141 /* Generic Interrupt Controller Definitions */
142 #define GICD_BASE 0x06000000
143 #define GICR_BASE 0x06100000
145 /* SMMU Defintions */
146 #define SMMU_BASE 0x05000000 /* GR0 Base */
149 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
150 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
152 #define CONFIG_SYS_FSL_CCSR_GUR_LE
153 #define CONFIG_SYS_FSL_CCSR_SCFG_LE
154 #define CONFIG_SYS_FSL_ESDHC_LE
155 #define CONFIG_SYS_FSL_IFC_LE
156 #define CONFIG_SYS_FSL_PEX_LUT_LE
158 #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
161 #define CONFIG_SYS_FSL_SFP_VER_3_4
162 #define CONFIG_SYS_FSL_SFP_LE
163 #define CONFIG_SYS_FSL_SRK_LE
165 /* Security Monitor */
166 #define CONFIG_SYS_FSL_SEC_MON_LE
169 #define CONFIG_ESBC_HDR_LS
172 #define CONFIG_SYS_FSL_CCSR_GUR_LE
173 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
174 #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
175 #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
176 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
178 /* LX2160A Soc Support */
179 #elif defined(CONFIG_ARCH_LX2160A)
180 #define TZPC_BASE 0x02200000
181 #define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
182 #if !defined(CONFIG_DM_I2C)
183 #define CONFIG_SYS_I2C
184 #define CONFIG_SYS_I2C_EARLY_INIT
186 #define SRDS_MAX_LANES 8
187 #ifndef L1_CACHE_BYTES
188 #define L1_CACHE_SHIFT 6
189 #define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT)
191 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2
192 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1, 4, 4, 4, 4 }
193 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4
195 #define CONFIG_SYS_PAGE_SIZE 0x10000
197 #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
198 #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
199 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */
202 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
203 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
205 #define CONFIG_SYS_FSL_CCSR_GUR_LE
206 #define CONFIG_SYS_FSL_CCSR_SCFG_LE
207 #define CONFIG_SYS_FSL_ESDHC_LE
208 #define CONFIG_SYS_FSL_PEX_LUT_LE
210 #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
212 /* Generic Interrupt Controller Definitions */
213 #define GICD_BASE 0x06000000
214 #define GICR_BASE 0x06200000
216 /* SMMU Definitions */
217 #define SMMU_BASE 0x05000000 /* GR0 Base */
220 #define CONFIG_SYS_FSL_SFP_VER_3_4
221 #define CONFIG_SYS_FSL_SFP_LE
222 #define CONFIG_SYS_FSL_SRK_LE
224 /* Security Monitor */
225 #define CONFIG_SYS_FSL_SEC_MON_LE
228 #define CONFIG_ESBC_HDR_LS
231 #define CONFIG_SYS_FSL_CCSR_GUR_LE
233 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
235 #elif defined(CONFIG_ARCH_LS1028A)
236 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3
237 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
239 #define CONFIG_FSL_TZPC_BP147
240 #define CONFIG_FSL_TZASC_400
242 /* TZ Protection Controller Definitions */
243 #define TZPC_BASE 0x02200000
244 #define TZPCR0SIZE_BASE (TZPC_BASE)
245 #define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800)
246 #define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
247 #define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808)
248 #define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C)
249 #define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810)
250 #define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814)
251 #define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818)
252 #define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C)
253 #define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820)
255 #define SRDS_MAX_LANES 4
256 #define SRDS_BITS_PER_LANE 4
258 #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
259 #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M */
260 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */
262 /* Generic Interrupt Controller Definitions */
263 #define GICD_BASE 0x06000000
264 #define GICR_BASE 0x06040000
266 /* SMMU Definitions */
267 #define SMMU_BASE 0x05000000 /* GR0 Base */
270 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
271 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
273 #define CONFIG_SYS_FSL_CCSR_GUR_LE
274 #define CONFIG_SYS_FSL_CCSR_SCFG_LE
275 #define CONFIG_SYS_FSL_ESDHC_LE
276 #define CONFIG_SYS_FSL_PEX_LUT_LE
278 #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
281 #define CONFIG_SYS_FSL_SFP_VER_3_4
282 #define CONFIG_SYS_FSL_SFP_LE
283 #define CONFIG_SYS_FSL_SRK_LE
286 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
288 /* Security Monitor */
289 #define CONFIG_SYS_FSL_SEC_MON_LE
292 #define CONFIG_ESBC_HDR_LS
295 #define CONFIG_SYS_FSL_CCSR_GUR_LE
297 #elif defined(CONFIG_FSL_LSCH2)
298 #define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */
299 #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
300 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
302 #define DCSR_DCFG_SBEESR2 0x20140534
303 #define DCSR_DCFG_MBEESR2 0x20140544
305 #define CONFIG_SYS_FSL_CCSR_SCFG_BE
306 #define CONFIG_SYS_FSL_ESDHC_BE
307 #define CONFIG_SYS_FSL_WDOG_BE
308 #define CONFIG_SYS_FSL_DSPI_BE
309 #define CONFIG_SYS_FSL_CCSR_GUR_BE
310 #define CONFIG_SYS_FSL_PEX_LUT_BE
313 #ifdef CONFIG_ARCH_LS1043A
314 #define CONFIG_SYS_FMAN_V3
315 #define CONFIG_SYS_FSL_QMAN_V3
316 #define CONFIG_SYS_NUM_FMAN 1
317 #define CONFIG_SYS_NUM_FM1_DTSEC 7
318 #define CONFIG_SYS_NUM_FM1_10GEC 1
319 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
320 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
322 #define QE_MURAM_SIZE 0x6000UL
323 #define MAX_QE_RISC 1
324 #define QE_NUM_OF_SNUM 28
326 #define CONFIG_SYS_FSL_IFC_BE
327 #define CONFIG_SYS_FSL_SFP_VER_3_2
328 #define CONFIG_SYS_FSL_SEC_MON_BE
329 #define CONFIG_SYS_FSL_SFP_BE
330 #define CONFIG_SYS_FSL_SRK_LE
331 #define CONFIG_KEY_REVOCATION
333 /* SMMU Defintions */
334 #define SMMU_BASE 0x09000000
336 /* Generic Interrupt Controller Definitions */
337 #define GICD_BASE 0x01401000
338 #define GICC_BASE 0x01402000
339 #define GICH_BASE 0x01404000
340 #define GICV_BASE 0x01406000
341 #define GICD_SIZE 0x1000
342 #define GICC_SIZE 0x2000
343 #define GICH_SIZE 0x2000
344 #define GICV_SIZE 0x2000
345 #ifdef CONFIG_HAS_FEATURE_GIC64K_ALIGN
346 #define GICD_BASE_64K 0x01410000
347 #define GICC_BASE_64K 0x01420000
348 #define GICH_BASE_64K 0x01440000
349 #define GICV_BASE_64K 0x01460000
350 #define GICD_SIZE_64K 0x10000
351 #define GICC_SIZE_64K 0x20000
352 #define GICH_SIZE_64K 0x20000
353 #define GICV_SIZE_64K 0x20000
356 #define DCFG_CCSR_SVR 0x1ee00a4
359 #define GIC_ADDR_BIT 31
360 #define SCFG_GIC400_ALIGN 0x1570188
362 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
364 #elif defined(CONFIG_ARCH_LS1012A)
365 #define GICD_BASE 0x01401000
366 #define GICC_BASE 0x01402000
367 #define CONFIG_SYS_FSL_SFP_VER_3_2
368 #define CONFIG_SYS_FSL_SEC_MON_BE
369 #define CONFIG_SYS_FSL_SFP_BE
370 #define CONFIG_SYS_FSL_SRK_LE
371 #define CONFIG_KEY_REVOCATION
372 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
373 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
374 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
376 #elif defined(CONFIG_ARCH_LS1046A)
377 #define CONFIG_SYS_FMAN_V3
378 #define CONFIG_SYS_FSL_QMAN_V3
379 #define CONFIG_SYS_NUM_FMAN 1
380 #define CONFIG_SYS_NUM_FM1_DTSEC 8
381 #define CONFIG_SYS_NUM_FM1_10GEC 2
382 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
383 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
385 #define CONFIG_SYS_FSL_IFC_BE
386 #define CONFIG_SYS_FSL_SFP_VER_3_2
387 #define CONFIG_SYS_FSL_SEC_MON_BE
388 #define CONFIG_SYS_FSL_SFP_BE
389 #define CONFIG_SYS_FSL_SRK_LE
390 #define CONFIG_KEY_REVOCATION
392 /* SMMU Defintions */
393 #define SMMU_BASE 0x09000000
395 /* Generic Interrupt Controller Definitions */
396 #define GICD_BASE 0x01410000
397 #define GICC_BASE 0x01420000
399 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
401 #error SoC not defined
405 #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ */