2 * Copyright 2015, Freescale Semiconductor
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_
8 #define _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_
10 #include <fsl_ddrc_version.h>
12 #define CONFIG_STANDALONE_LOAD_ADDR 0x80300000
14 #ifdef CONFIG_SYS_FSL_DDR4
15 #define CONFIG_SYS_FSL_DDRC_GEN4
17 #define CONFIG_SYS_FSL_DDRC_ARM_GEN3 /* Enable Freescale ARM DDR3 driver */
21 #define CONFIG_SYS_FSL_MMDC /* Freescale MMDC driver */
23 #define CONFIG_SYS_FSL_DDR /* Freescale DDR driver */
24 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
28 * Reserve secure memory
29 * To be aligned with MMU block size
31 #define CONFIG_SYS_MEM_RESERVE_SECURE (2048 * 1024) /* 2MB */
34 #define CONFIG_MAX_CPUS 16
35 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
36 #define CONFIG_NUM_DDR_CONTROLLERS 3
37 #define CONFIG_SYS_FSL_HAS_DP_DDR /* Runtime check to confirm */
38 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 }
39 #define SRDS_MAX_LANES 8
40 #define CONFIG_SYS_FSL_SRDS_1
41 #define CONFIG_SYS_FSL_SRDS_2
42 #define CONFIG_SYS_PAGE_SIZE 0x10000
43 #ifndef L1_CACHE_BYTES
44 #define L1_CACHE_SHIFT 6
45 #define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT)
48 #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
49 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */
52 #define CONFIG_SYS_FSL_DDR_LE
53 #define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
54 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS2_DDR_BLOCK1_SIZE
56 #define CONFIG_SYS_FSL_CCSR_GUR_LE
57 #define CONFIG_SYS_FSL_CCSR_SCFG_LE
58 #define CONFIG_SYS_FSL_ESDHC_LE
59 #define CONFIG_SYS_FSL_IFC_LE
60 #define CONFIG_SYS_FSL_PEX_LUT_LE
62 #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
64 /* Generic Interrupt Controller Definitions */
65 #define GICD_BASE 0x06000000
66 #define GICR_BASE 0x06100000
69 #define SMMU_BASE 0x05000000 /* GR0 Base */
72 #define CONFIG_SYS_FSL_SFP_VER_3_4
73 #define CONFIG_SYS_FSL_SFP_LE
74 #define CONFIG_SYS_FSL_SRK_LE
77 #define CONFIG_SYS_FSL_SEC_LE
78 #define CONFIG_SYS_FSL_SEC_COMPAT 5
80 /* Security Monitor */
81 #define CONFIG_SYS_FSL_SEC_MON_LE
84 #define CONFIG_ESBC_HDR_LS
87 #define CONFIG_SYS_FSL_CCSR_GUR_LE
89 /* Cache Coherent Interconnect */
90 #define CCI_MN_BASE 0x04000000
91 #define CCI_MN_RNF_NODEID_LIST 0x180
92 #define CCI_MN_DVM_DOMAIN_CTL 0x200
93 #define CCI_MN_DVM_DOMAIN_CTL_SET 0x210
95 #define CCI_HN_F_0_BASE (CCI_MN_BASE + 0x200000)
96 #define CCI_HN_F_1_BASE (CCI_MN_BASE + 0x210000)
97 #define CCN_HN_F_SAM_CTL 0x8 /* offset on base HN_F base */
98 #define CCN_HN_F_SAM_NODEID_MASK 0x7f
99 #define CCN_HN_F_SAM_NODEID_DDR0 0x4
100 #define CCN_HN_F_SAM_NODEID_DDR1 0xe
102 #define CCI_RN_I_0_BASE (CCI_MN_BASE + 0x800000)
103 #define CCI_RN_I_2_BASE (CCI_MN_BASE + 0x820000)
104 #define CCI_RN_I_6_BASE (CCI_MN_BASE + 0x860000)
105 #define CCI_RN_I_12_BASE (CCI_MN_BASE + 0x8C0000)
106 #define CCI_RN_I_16_BASE (CCI_MN_BASE + 0x900000)
107 #define CCI_RN_I_20_BASE (CCI_MN_BASE + 0x940000)
109 #define CCI_S0_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x10)
110 #define CCI_S1_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x110)
111 #define CCI_S2_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x210)
113 #define CCI_AUX_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x0500)
115 /* TZ Protection Controller Definitions */
116 #define TZPC_BASE 0x02200000
117 #define TZPCR0SIZE_BASE (TZPC_BASE)
118 #define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800)
119 #define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
120 #define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808)
121 #define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C)
122 #define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810)
123 #define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814)
124 #define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818)
125 #define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C)
126 #define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820)
128 #define DCSR_CGACRE5 0x700070914ULL
129 #define EPU_EPCMPR5 0x700060914ULL
130 #define EPU_EPCCR5 0x700060814ULL
131 #define EPU_EPSMCR5 0x700060228ULL
132 #define EPU_EPECR5 0x700060314ULL
133 #define EPU_EPCTR5 0x700060a14ULL
134 #define EPU_EPGCR 0x700060000ULL
136 #define CONFIG_SYS_FSL_ERRATUM_A008336
137 #define CONFIG_SYS_FSL_ERRATUM_A008511
138 #define CONFIG_SYS_FSL_ERRATUM_A008514
139 #define CONFIG_SYS_FSL_ERRATUM_A008585
140 #define CONFIG_SYS_FSL_ERRATUM_A008751
141 #define CONFIG_SYS_FSL_ERRATUM_A009635
142 #define CONFIG_SYS_FSL_ERRATUM_A009663
143 #define CONFIG_SYS_FSL_ERRATUM_A009801
144 #define CONFIG_SYS_FSL_ERRATUM_A009803
145 #define CONFIG_SYS_FSL_ERRATUM_A009942
146 #define CONFIG_SYS_FSL_ERRATUM_A010165
148 /* ARM A57 CORE ERRATA */
149 #define CONFIG_ARM_ERRATA_826974
150 #define CONFIG_ARM_ERRATA_828024
151 #define CONFIG_ARM_ERRATA_829520
152 #define CONFIG_ARM_ERRATA_833471
154 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
155 #elif defined(CONFIG_FSL_LSCH2)
156 #define CONFIG_NUM_DDR_CONTROLLERS 1
157 #define CONFIG_SYS_FSL_SEC_COMPAT 5
158 #define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */
159 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */
160 #define CONFIG_SYS_CCSRBAR_DEFAULT 0x01000000
162 #define CONFIG_SYS_FSL_CCSR_SCFG_BE
163 #define CONFIG_SYS_FSL_ESDHC_BE
164 #define CONFIG_SYS_FSL_WDOG_BE
165 #define CONFIG_SYS_FSL_DSPI_BE
166 #define CONFIG_SYS_FSL_QSPI_BE
167 #define CONFIG_SYS_FSL_CCSR_GUR_BE
168 #define CONFIG_SYS_FSL_PEX_LUT_BE
169 #define CONFIG_SYS_FSL_SEC_BE
171 #define CONFIG_SYS_FSL_SRDS_1
173 #define CONFIG_SYS_FSL_ERRATUM_A010315
175 #ifdef CONFIG_LS1043A
176 #define CONFIG_MAX_CPUS 4
177 #define CONFIG_SYS_FMAN_V3
178 #define CONFIG_SYS_NUM_FMAN 1
179 #define CONFIG_SYS_NUM_FM1_DTSEC 7
180 #define CONFIG_SYS_NUM_FM1_10GEC 1
181 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
182 #define CONFIG_SYS_FSL_DDR_BE
183 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
184 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
186 #define QE_MURAM_SIZE 0x6000UL
187 #define MAX_QE_RISC 1
188 #define QE_NUM_OF_SNUM 28
190 #define CONFIG_SYS_FSL_IFC_BE
191 #define CONFIG_SYS_FSL_SFP_VER_3_2
192 #define CONFIG_SYS_FSL_SEC_MON_BE
193 #define CONFIG_SYS_FSL_SFP_BE
194 #define CONFIG_SYS_FSL_SRK_LE
195 #define CONFIG_KEY_REVOCATION
197 /* SMMU Defintions */
198 #define SMMU_BASE 0x09000000
200 /* Generic Interrupt Controller Definitions */
201 #define GICD_BASE 0x01401000
202 #define GICC_BASE 0x01402000
204 #define CONFIG_SYS_FSL_ERRATUM_A008850
205 #define CONFIG_SYS_FSL_ERRATUM_A009663
206 #define CONFIG_SYS_FSL_ERRATUM_A009929
207 #define CONFIG_SYS_FSL_ERRATUM_A009942
208 #define CONFIG_SYS_FSL_ERRATUM_A009660
209 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
210 #elif defined(CONFIG_LS1012A)
211 #define CONFIG_MAX_CPUS 1
212 #undef CONFIG_SYS_FSL_DDRC_ARM_GEN3
214 #define GICD_BASE 0x01401000
215 #define GICC_BASE 0x01402000
216 #elif defined(CONFIG_LS1046A)
217 #define CONFIG_MAX_CPUS 4
218 #define CONFIG_SYS_FMAN_V3
219 #define CONFIG_SYS_NUM_FMAN 1
220 #define CONFIG_SYS_NUM_FM1_DTSEC 8
221 #define CONFIG_SYS_NUM_FM1_10GEC 2
222 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
223 #define CONFIG_SYS_FSL_DDR_BE
224 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
225 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
227 #define CONFIG_SYS_FSL_SRDS_2
228 #define CONFIG_SYS_FSL_IFC_BE
229 #define CONFIG_SYS_FSL_SFP_VER_3_2
230 #define CONFIG_SYS_FSL_SNVS_LE
231 #define CONFIG_SYS_FSL_SFP_BE
232 #define CONFIG_SYS_FSL_SRK_LE
233 #define CONFIG_KEY_REVOCATION
235 /* SMMU Defintions */
236 #define SMMU_BASE 0x09000000
238 /* Generic Interrupt Controller Definitions */
239 #define GICD_BASE 0x01410000
240 #define GICC_BASE 0x01420000
242 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
244 #define CONFIG_SYS_FSL_ERRATUM_A008511
245 #define CONFIG_SYS_FSL_ERRATUM_A009801
246 #define CONFIG_SYS_FSL_ERRATUM_A009803
247 #define CONFIG_SYS_FSL_ERRATUM_A009942
248 #define CONFIG_SYS_FSL_ERRATUM_A010165
250 #error SoC not defined
254 #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ */