1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2016-2018, 2020 NXP
4 * Copyright 2015, Freescale Semiconductor
7 #ifndef _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_
8 #define _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_
10 #include <linux/kconfig.h>
11 #include <fsl_ddrc_version.h>
14 #include <linux/bitops.h>
18 * Reserve secure memory
19 * To be aligned with MMU block size
21 #define CFG_SYS_MEM_RESERVE_SECURE (66 * 1024 * 1024) /* 66MB */
22 #define SPL_TLB_SETBACK 0x1000000 /* 16MB under effective memory top */
24 #ifdef CONFIG_ARCH_LS2080A
25 #define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 }
26 #define SRDS_MAX_LANES 8
27 #define CFG_SYS_PAGE_SIZE 0x10000
28 #ifndef L1_CACHE_BYTES
29 #define L1_CACHE_SHIFT 6
30 #define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT)
33 #define CFG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
34 #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
35 #define CFG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
38 #define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
39 #define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE
41 /* Generic Interrupt Controller Definitions */
42 #define GICD_BASE 0x06000000
43 #define GICR_BASE 0x06100000
46 #define SMMU_BASE 0x05000000 /* GR0 Base */
48 /* Cache Coherent Interconnect */
49 #define CCI_MN_BASE 0x04000000
50 #define CCI_MN_RNF_NODEID_LIST 0x180
51 #define CCI_MN_DVM_DOMAIN_CTL 0x200
52 #define CCI_MN_DVM_DOMAIN_CTL_SET 0x210
54 #define CCI_HN_F_0_BASE (CCI_MN_BASE + 0x200000)
55 #define CCI_HN_F_1_BASE (CCI_MN_BASE + 0x210000)
56 #define CCN_HN_F_SAM_CTL 0x8 /* offset on base HN_F base */
57 #define CCN_HN_F_SAM_NODEID_MASK 0x7f
58 #define CCN_HN_F_SAM_NODEID_DDR0 0x4
59 #define CCN_HN_F_SAM_NODEID_DDR1 0xe
61 #define CCI_RN_I_0_BASE (CCI_MN_BASE + 0x800000)
62 #define CCI_RN_I_2_BASE (CCI_MN_BASE + 0x820000)
63 #define CCI_RN_I_6_BASE (CCI_MN_BASE + 0x860000)
64 #define CCI_RN_I_12_BASE (CCI_MN_BASE + 0x8C0000)
65 #define CCI_RN_I_16_BASE (CCI_MN_BASE + 0x900000)
66 #define CCI_RN_I_20_BASE (CCI_MN_BASE + 0x940000)
68 #define CCI_S0_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x10)
69 #define CCI_S1_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x110)
70 #define CCI_S2_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x210)
72 #define CCI_AUX_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x0500)
74 /* TZ Protection Controller Definitions */
75 #define TZPC_BASE 0x02200000
76 #define TZPCR0SIZE_BASE (TZPC_BASE)
77 #define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800)
78 #define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
79 #define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808)
80 #define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C)
81 #define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810)
82 #define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814)
83 #define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818)
84 #define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C)
85 #define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820)
87 #define DCSR_CGACRE5 0x700070914ULL
88 #define EPU_EPCMPR5 0x700060914ULL
89 #define EPU_EPCCR5 0x700060814ULL
90 #define EPU_EPSMCR5 0x700060228ULL
91 #define EPU_EPECR5 0x700060314ULL
92 #define EPU_EPCTR5 0x700060a14ULL
93 #define EPU_EPGCR 0x700060000ULL
95 #elif defined(CONFIG_ARCH_LS1088A)
96 #define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
97 #define CFG_SYS_PAGE_SIZE 0x10000
99 #define SRDS_MAX_LANES 4
100 #define SRDS_BITS_PER_LANE 4
102 /* TZ Protection Controller Definitions */
103 #define TZPC_BASE 0x02200000
104 #define TZPCR0SIZE_BASE (TZPC_BASE)
105 #define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800)
106 #define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
107 #define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808)
108 #define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C)
109 #define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810)
110 #define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814)
111 #define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818)
112 #define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C)
113 #define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820)
115 /* Generic Interrupt Controller Definitions */
116 #define GICD_BASE 0x06000000
117 #define GICR_BASE 0x06100000
119 /* SMMU Defintions */
120 #define SMMU_BASE 0x05000000 /* GR0 Base */
123 #define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
124 #define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE
127 #define CFG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
128 #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
129 #define CFG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
131 /* LX2160A/LX2162A Soc Support */
132 #elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
133 #define TZPC_BASE 0x02200000
134 #define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
135 #define SRDS_MAX_LANES 8
136 #ifndef L1_CACHE_BYTES
137 #define L1_CACHE_SHIFT 6
138 #define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT)
140 #define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1, 4, 4, 4, 4 }
142 #define CFG_SYS_PAGE_SIZE 0x10000
144 #define CFG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
145 #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
146 #define CFG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */
149 #define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
150 #define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE
152 /* Generic Interrupt Controller Definitions */
153 #define GICD_BASE 0x06000000
154 #define GICR_BASE 0x06200000
156 /* SMMU Definitions */
157 #define SMMU_BASE 0x05000000 /* GR0 Base */
161 #elif defined(CONFIG_ARCH_LS1028A)
162 #define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
163 #define CONFIG_FSL_TZASC_400
165 /* TZ Protection Controller Definitions */
166 #define TZPC_BASE 0x02200000
167 #define TZPCR0SIZE_BASE (TZPC_BASE)
168 #define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800)
169 #define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
170 #define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808)
171 #define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C)
172 #define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810)
173 #define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814)
174 #define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818)
175 #define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C)
176 #define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820)
178 #define SRDS_MAX_LANES 4
179 #define SRDS_BITS_PER_LANE 4
181 #define CFG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
182 #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M */
183 #define CFG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */
185 /* Generic Interrupt Controller Definitions */
186 #define GICD_BASE 0x06000000
187 #define GICR_BASE 0x06040000
189 /* SMMU Definitions */
190 #define SMMU_BASE 0x05000000 /* GR0 Base */
193 #define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
194 #define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE
200 #elif defined(CONFIG_FSL_LSCH2)
201 #define CFG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */
202 #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
203 #define CFG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
205 #define DCSR_DCFG_SBEESR2 0x20140534
206 #define DCSR_DCFG_MBEESR2 0x20140544
209 #ifdef CONFIG_ARCH_LS1043A
210 #define CFG_SYS_NUM_FMAN 1
211 #define CFG_SYS_NUM_FM1_DTSEC 7
212 #define CFG_SYS_NUM_FM1_10GEC 1
213 #define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
214 #define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE
216 #define QE_MURAM_SIZE 0x6000UL
217 #define MAX_QE_RISC 1
218 #define QE_NUM_OF_SNUM 28
220 /* SMMU Defintions */
221 #define SMMU_BASE 0x09000000
223 /* Generic Interrupt Controller Definitions */
224 #define GICD_BASE 0x01401000
225 #define GICC_BASE 0x01402000
226 #define GICH_BASE 0x01404000
227 #define GICV_BASE 0x01406000
228 #define GICD_SIZE 0x1000
229 #define GICC_SIZE 0x2000
230 #define GICH_SIZE 0x2000
231 #define GICV_SIZE 0x2000
232 #ifdef CONFIG_HAS_FEATURE_GIC64K_ALIGN
233 #define GICD_BASE_64K 0x01410000
234 #define GICC_BASE_64K 0x01420000
235 #define GICH_BASE_64K 0x01440000
236 #define GICV_BASE_64K 0x01460000
237 #define GICD_SIZE_64K 0x10000
238 #define GICC_SIZE_64K 0x20000
239 #define GICH_SIZE_64K 0x20000
240 #define GICV_SIZE_64K 0x20000
243 #define DCFG_CCSR_SVR 0x1ee00a4
246 #define GIC_ADDR_BIT 31
247 #define SCFG_GIC400_ALIGN 0x1570188
249 #elif defined(CONFIG_ARCH_LS1012A)
250 #define GICD_BASE 0x01401000
251 #define GICC_BASE 0x01402000
252 #define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
253 #define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE
255 #elif defined(CONFIG_ARCH_LS1046A)
256 #define CFG_SYS_NUM_FMAN 1
257 #define CFG_SYS_NUM_FM1_DTSEC 8
258 #define CFG_SYS_NUM_FM1_10GEC 2
259 #define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
260 #define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE
262 /* SMMU Defintions */
263 #define SMMU_BASE 0x09000000
265 /* Generic Interrupt Controller Definitions */
266 #define GICD_BASE 0x01410000
267 #define GICC_BASE 0x01420000
269 #error SoC not defined
273 #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ */