1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2016-2018, 2020 NXP
4 * Copyright 2015, Freescale Semiconductor
7 #ifndef _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_
8 #define _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_
10 #include <linux/kconfig.h>
11 #include <fsl_ddrc_version.h>
14 #include <linux/bitops.h>
17 #define CONFIG_STANDALONE_LOAD_ADDR 0x80300000
20 * Reserve secure memory
21 * To be aligned with MMU block size
23 #define CONFIG_SYS_MEM_RESERVE_SECURE (66 * 1024 * 1024) /* 66MB */
24 #define SPL_TLB_SETBACK 0x1000000 /* 16MB under effective memory top */
26 #ifdef CONFIG_ARCH_LS2080A
27 #define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 }
28 #define SRDS_MAX_LANES 8
29 #define CONFIG_SYS_PAGE_SIZE 0x10000
30 #ifndef L1_CACHE_BYTES
31 #define L1_CACHE_SHIFT 6
32 #define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT)
35 #define CFG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
36 #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
37 #define CFG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
40 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
41 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
43 /* Generic Interrupt Controller Definitions */
44 #define GICD_BASE 0x06000000
45 #define GICR_BASE 0x06100000
48 #define SMMU_BASE 0x05000000 /* GR0 Base */
50 /* Cache Coherent Interconnect */
51 #define CCI_MN_BASE 0x04000000
52 #define CCI_MN_RNF_NODEID_LIST 0x180
53 #define CCI_MN_DVM_DOMAIN_CTL 0x200
54 #define CCI_MN_DVM_DOMAIN_CTL_SET 0x210
56 #define CCI_HN_F_0_BASE (CCI_MN_BASE + 0x200000)
57 #define CCI_HN_F_1_BASE (CCI_MN_BASE + 0x210000)
58 #define CCN_HN_F_SAM_CTL 0x8 /* offset on base HN_F base */
59 #define CCN_HN_F_SAM_NODEID_MASK 0x7f
60 #define CCN_HN_F_SAM_NODEID_DDR0 0x4
61 #define CCN_HN_F_SAM_NODEID_DDR1 0xe
63 #define CCI_RN_I_0_BASE (CCI_MN_BASE + 0x800000)
64 #define CCI_RN_I_2_BASE (CCI_MN_BASE + 0x820000)
65 #define CCI_RN_I_6_BASE (CCI_MN_BASE + 0x860000)
66 #define CCI_RN_I_12_BASE (CCI_MN_BASE + 0x8C0000)
67 #define CCI_RN_I_16_BASE (CCI_MN_BASE + 0x900000)
68 #define CCI_RN_I_20_BASE (CCI_MN_BASE + 0x940000)
70 #define CCI_S0_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x10)
71 #define CCI_S1_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x110)
72 #define CCI_S2_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x210)
74 #define CCI_AUX_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x0500)
76 /* TZ Protection Controller Definitions */
77 #define TZPC_BASE 0x02200000
78 #define TZPCR0SIZE_BASE (TZPC_BASE)
79 #define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800)
80 #define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
81 #define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808)
82 #define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C)
83 #define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810)
84 #define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814)
85 #define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818)
86 #define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C)
87 #define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820)
89 #define DCSR_CGACRE5 0x700070914ULL
90 #define EPU_EPCMPR5 0x700060914ULL
91 #define EPU_EPCCR5 0x700060814ULL
92 #define EPU_EPSMCR5 0x700060228ULL
93 #define EPU_EPECR5 0x700060314ULL
94 #define EPU_EPCTR5 0x700060a14ULL
95 #define EPU_EPGCR 0x700060000ULL
97 #elif defined(CONFIG_ARCH_LS1088A)
98 #define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
99 #define CONFIG_SYS_PAGE_SIZE 0x10000
101 #define SRDS_MAX_LANES 4
102 #define SRDS_BITS_PER_LANE 4
104 /* TZ Protection Controller Definitions */
105 #define TZPC_BASE 0x02200000
106 #define TZPCR0SIZE_BASE (TZPC_BASE)
107 #define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800)
108 #define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
109 #define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808)
110 #define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C)
111 #define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810)
112 #define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814)
113 #define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818)
114 #define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C)
115 #define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820)
117 /* Generic Interrupt Controller Definitions */
118 #define GICD_BASE 0x06000000
119 #define GICR_BASE 0x06100000
121 /* SMMU Defintions */
122 #define SMMU_BASE 0x05000000 /* GR0 Base */
125 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
126 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
129 #define CFG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
130 #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
131 #define CFG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
133 /* LX2160A/LX2162A Soc Support */
134 #elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
135 #define TZPC_BASE 0x02200000
136 #define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
137 #define SRDS_MAX_LANES 8
138 #ifndef L1_CACHE_BYTES
139 #define L1_CACHE_SHIFT 6
140 #define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT)
142 #define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1, 4, 4, 4, 4 }
144 #define CONFIG_SYS_PAGE_SIZE 0x10000
146 #define CFG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
147 #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
148 #define CFG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */
151 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
152 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
154 /* Generic Interrupt Controller Definitions */
155 #define GICD_BASE 0x06000000
156 #define GICR_BASE 0x06200000
158 /* SMMU Definitions */
159 #define SMMU_BASE 0x05000000 /* GR0 Base */
163 #elif defined(CONFIG_ARCH_LS1028A)
164 #define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
165 #define CONFIG_FSL_TZASC_400
167 /* TZ Protection Controller Definitions */
168 #define TZPC_BASE 0x02200000
169 #define TZPCR0SIZE_BASE (TZPC_BASE)
170 #define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800)
171 #define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
172 #define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808)
173 #define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C)
174 #define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810)
175 #define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814)
176 #define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818)
177 #define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C)
178 #define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820)
180 #define SRDS_MAX_LANES 4
181 #define SRDS_BITS_PER_LANE 4
183 #define CFG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
184 #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M */
185 #define CFG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */
187 /* Generic Interrupt Controller Definitions */
188 #define GICD_BASE 0x06000000
189 #define GICR_BASE 0x06040000
191 /* SMMU Definitions */
192 #define SMMU_BASE 0x05000000 /* GR0 Base */
195 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
196 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
202 #elif defined(CONFIG_FSL_LSCH2)
203 #define CFG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */
204 #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
205 #define CFG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
207 #define DCSR_DCFG_SBEESR2 0x20140534
208 #define DCSR_DCFG_MBEESR2 0x20140544
211 #ifdef CONFIG_ARCH_LS1043A
212 #define CFG_SYS_NUM_FMAN 1
213 #define CFG_SYS_NUM_FM1_DTSEC 7
214 #define CFG_SYS_NUM_FM1_10GEC 1
215 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
216 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
218 #define QE_MURAM_SIZE 0x6000UL
219 #define MAX_QE_RISC 1
220 #define QE_NUM_OF_SNUM 28
222 /* SMMU Defintions */
223 #define SMMU_BASE 0x09000000
225 /* Generic Interrupt Controller Definitions */
226 #define GICD_BASE 0x01401000
227 #define GICC_BASE 0x01402000
228 #define GICH_BASE 0x01404000
229 #define GICV_BASE 0x01406000
230 #define GICD_SIZE 0x1000
231 #define GICC_SIZE 0x2000
232 #define GICH_SIZE 0x2000
233 #define GICV_SIZE 0x2000
234 #ifdef CONFIG_HAS_FEATURE_GIC64K_ALIGN
235 #define GICD_BASE_64K 0x01410000
236 #define GICC_BASE_64K 0x01420000
237 #define GICH_BASE_64K 0x01440000
238 #define GICV_BASE_64K 0x01460000
239 #define GICD_SIZE_64K 0x10000
240 #define GICC_SIZE_64K 0x20000
241 #define GICH_SIZE_64K 0x20000
242 #define GICV_SIZE_64K 0x20000
245 #define DCFG_CCSR_SVR 0x1ee00a4
248 #define GIC_ADDR_BIT 31
249 #define SCFG_GIC400_ALIGN 0x1570188
251 #elif defined(CONFIG_ARCH_LS1012A)
252 #define GICD_BASE 0x01401000
253 #define GICC_BASE 0x01402000
254 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
255 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
257 #elif defined(CONFIG_ARCH_LS1046A)
258 #define CFG_SYS_NUM_FMAN 1
259 #define CFG_SYS_NUM_FM1_DTSEC 8
260 #define CFG_SYS_NUM_FM1_10GEC 2
261 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
262 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
264 /* SMMU Defintions */
265 #define SMMU_BASE 0x09000000
267 /* Generic Interrupt Controller Definitions */
268 #define GICD_BASE 0x01410000
269 #define GICC_BASE 0x01420000
271 #error SoC not defined
275 #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ */