arch/arm/include/asm/arch-bcm281xx/sysmap.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2013 Broadcom Corporation.
   4  */
   5
   6 #ifndef __ARCH_BCM281XX_SYSMAP_H
   7
   8 #define BSC1_BASE_ADDR          0x3e016000
   9 #define BSC2_BASE_ADDR          0x3e017000
  10 #define BSC3_BASE_ADDR          0x3e018000
  11 #define DWDMA_AHB_BASE_ADDR     0x38100000
  12 #define ESUB_CLK_BASE_ADDR      0x38000000
  13 #define ESW_CONTRL_BASE_ADDR    0x38200000
  14 #define GPIO2_BASE_ADDR         0x35003000
  15 #define HSOTG_BASE_ADDR         0x3f120000
  16 #define HSOTG_CTRL_BASE_ADDR    0x3f130000
  17 #define KONA_MST_CLK_BASE_ADDR  0x3f001000
  18 #define KONA_SLV_CLK_BASE_ADDR  0x3e011000
  19 #define PMU_BSC_BASE_ADDR       0x3500d000
  20 #define PWRMGR_BASE_ADDR        0x35010000
  21 #define SDIO1_BASE_ADDR         0x3f180000
  22 #define SDIO2_BASE_ADDR         0x3f190000
  23 #define SDIO3_BASE_ADDR         0x3f1a0000
  24 #define SDIO4_BASE_ADDR         0x3f1b0000
  25 #define SECWD_BASE_ADDR         0x3500c000
  26 #define SECWD2_BASE_ADDR        0x35002f40
  27 #define TIMER_BASE_ADDR         0x3e00d000
  28
  29 #define HSOTG_DCTL_OFFSET                                       0x00000804
  30 #define    HSOTG_DCTL_SFTDISCON_MASK                            0x00000002
  31
  32 #define HSOTG_CTRL_PHY_P1CTL_OFFSET                             0x00000008
  33 #define    HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK                 0x00000002
  34 #define    HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK                0x00000001
  35
  36 #endif