1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (c) 2016 Google, Inc
5 #ifndef _ASM_ARCH_SCU_AST2500_H
6 #define _ASM_ARCH_SCU_AST2500_H
8 #define SCU_UNLOCK_VALUE 0x1688a8a8
10 #define SCU_HWSTRAP_VGAMEM_SHIFT 2
11 #define SCU_HWSTRAP_VGAMEM_MASK (3 << SCU_HWSTRAP_VGAMEM_SHIFT)
12 #define SCU_HWSTRAP_MAC1_RGMII (1 << 6)
13 #define SCU_HWSTRAP_MAC2_RGMII (1 << 7)
14 #define SCU_HWSTRAP_DDR4 (1 << 24)
15 #define SCU_HWSTRAP_CLKIN_25MHZ (1 << 23)
17 #define SCU_MPLL_DENUM_SHIFT 0
18 #define SCU_MPLL_DENUM_MASK 0x1f
19 #define SCU_MPLL_NUM_SHIFT 5
20 #define SCU_MPLL_NUM_MASK (0xff << SCU_MPLL_NUM_SHIFT)
21 #define SCU_MPLL_POST_SHIFT 13
22 #define SCU_MPLL_POST_MASK (0x3f << SCU_MPLL_POST_SHIFT)
23 #define SCU_PCLK_DIV_SHIFT 23
24 #define SCU_PCLK_DIV_MASK (7 << SCU_PCLK_DIV_SHIFT)
25 #define SCU_SDCLK_DIV_SHIFT 12
26 #define SCU_SDCLK_DIV_MASK (7 << SCU_SDCLK_DIV_SHIFT)
27 #define SCU_HPLL_DENUM_SHIFT 0
28 #define SCU_HPLL_DENUM_MASK 0x1f
29 #define SCU_HPLL_NUM_SHIFT 5
30 #define SCU_HPLL_NUM_MASK (0xff << SCU_HPLL_NUM_SHIFT)
31 #define SCU_HPLL_POST_SHIFT 13
32 #define SCU_HPLL_POST_MASK (0x3f << SCU_HPLL_POST_SHIFT)
34 #define SCU_MACCLK_SHIFT 16
35 #define SCU_MACCLK_MASK (7 << SCU_MACCLK_SHIFT)
37 #define SCU_MISC2_RGMII_HPLL (1 << 23)
38 #define SCU_MISC2_RGMII_CLKDIV_SHIFT 20
39 #define SCU_MISC2_RGMII_CLKDIV_MASK (3 << SCU_MISC2_RGMII_CLKDIV_SHIFT)
40 #define SCU_MISC2_RMII_MPLL (1 << 19)
41 #define SCU_MISC2_RMII_CLKDIV_SHIFT 16
42 #define SCU_MISC2_RMII_CLKDIV_MASK (3 << SCU_MISC2_RMII_CLKDIV_SHIFT)
43 #define SCU_MISC2_UARTCLK_SHIFT 24
45 #define SCU_MISC_D2PLL_OFF (1 << 4)
46 #define SCU_MISC_UARTCLK_DIV13 (1 << 12)
47 #define SCU_MISC_GCRT_USB20CLK (1 << 21)
49 #define SCU_MICDS_MAC1RGMII_TXDLY_SHIFT 0
50 #define SCU_MICDS_MAC1RGMII_TXDLY_MASK (0x3f\
51 << SCU_MICDS_MAC1RGMII_TXDLY_SHIFT)
52 #define SCU_MICDS_MAC2RGMII_TXDLY_SHIFT 6
53 #define SCU_MICDS_MAC2RGMII_TXDLY_MASK (0x3f\
54 << SCU_MICDS_MAC2RGMII_TXDLY_SHIFT)
55 #define SCU_MICDS_MAC1RMII_RDLY_SHIFT 12
56 #define SCU_MICDS_MAC1RMII_RDLY_MASK (0x3f << SCU_MICDS_MAC1RMII_RDLY_SHIFT)
57 #define SCU_MICDS_MAC2RMII_RDLY_SHIFT 18
58 #define SCU_MICDS_MAC2RMII_RDLY_MASK (0x3f << SCU_MICDS_MAC2RMII_RDLY_SHIFT)
59 #define SCU_MICDS_MAC1RMII_TXFALL (1 << 24)
60 #define SCU_MICDS_MAC2RMII_TXFALL (1 << 25)
61 #define SCU_MICDS_RMII1_RCLKEN (1 << 29)
62 #define SCU_MICDS_RMII2_RCLKEN (1 << 30)
63 #define SCU_MICDS_RGMIIPLL (1 << 31)
66 * SYSRESET is actually more like a Power register,
67 * except that corresponding bit set to 1 means that
68 * the peripheral is off.
70 #define SCU_SYSRESET_XDMA (1 << 25)
71 #define SCU_SYSRESET_MCTP (1 << 24)
72 #define SCU_SYSRESET_ADC (1 << 23)
73 #define SCU_SYSRESET_JTAG (1 << 22)
74 #define SCU_SYSRESET_MIC (1 << 18)
75 #define SCU_SYSRESET_SDIO (1 << 16)
76 #define SCU_SYSRESET_USB11HOST (1 << 15)
77 #define SCU_SYSRESET_USBHUB (1 << 14)
78 #define SCU_SYSRESET_CRT (1 << 13)
79 #define SCU_SYSRESET_MAC2 (1 << 12)
80 #define SCU_SYSRESET_MAC1 (1 << 11)
81 #define SCU_SYSRESET_PECI (1 << 10)
82 #define SCU_SYSRESET_PWM (1 << 9)
83 #define SCU_SYSRESET_PCI_VGA (1 << 8)
84 #define SCU_SYSRESET_2D (1 << 7)
85 #define SCU_SYSRESET_VIDEO (1 << 6)
86 #define SCU_SYSRESET_LPC (1 << 5)
87 #define SCU_SYSRESET_HAC (1 << 4)
88 #define SCU_SYSRESET_USBHID (1 << 3)
89 #define SCU_SYSRESET_I2C (1 << 2)
90 #define SCU_SYSRESET_AHB (1 << 1)
91 #define SCU_SYSRESET_SDRAM_WDT (1 << 0)
93 /* Bits 16-27 in the register control pin functions for I2C devices 3-14 */
94 #define SCU_PINMUX_CTRL5_I2C (1 << 16)
97 * The values are grouped by function, not by register.
98 * They are actually scattered across multiple loosely related registers.
100 #define SCU_PIN_FUN_MAC1_MDC (1 << 30)
101 #define SCU_PIN_FUN_MAC1_MDIO (1 << 31)
102 #define SCU_PIN_FUN_MAC1_PHY_LINK (1 << 0)
103 #define SCU_PIN_FUN_MAC2_MDIO (1 << 2)
104 #define SCU_PIN_FUN_MAC2_PHY_LINK (1 << 1)
105 #define SCU_PIN_FUN_SCL1 (1 << 12)
106 #define SCU_PIN_FUN_SCL2 (1 << 14)
107 #define SCU_PIN_FUN_SDA1 (1 << 13)
108 #define SCU_PIN_FUN_SDA2 (1 << 15)
110 #define SCU_CLKSTOP_MAC1 (1 << 20)
111 #define SCU_CLKSTOP_MAC2 (1 << 21)
112 #define SCU_CLKSTOP_SDCLK (1 << 27)
114 #define SCU_D2PLL_EXT1_OFF (1 << 0)
115 #define SCU_D2PLL_EXT1_BYPASS (1 << 1)
116 #define SCU_D2PLL_EXT1_RESET (1 << 2)
117 #define SCU_D2PLL_EXT1_MODE_SHIFT 3
118 #define SCU_D2PLL_EXT1_MODE_MASK (3 << SCU_D2PLL_EXT1_MODE_SHIFT)
119 #define SCU_D2PLL_EXT1_PARAM_SHIFT 5
120 #define SCU_D2PLL_EXT1_PARAM_MASK (0x1ff << SCU_D2PLL_EXT1_PARAM_SHIFT)
122 #define SCU_D2PLL_NUM_SHIFT 0
123 #define SCU_D2PLL_NUM_MASK (0xff << SCU_D2PLL_NUM_SHIFT)
124 #define SCU_D2PLL_DENUM_SHIFT 8
125 #define SCU_D2PLL_DENUM_MASK (0x1f << SCU_D2PLL_DENUM_SHIFT)
126 #define SCU_D2PLL_POST_SHIFT 13
127 #define SCU_D2PLL_POST_MASK (0x3f << SCU_D2PLL_POST_SHIFT)
128 #define SCU_D2PLL_ODIV_SHIFT 19
129 #define SCU_D2PLL_ODIV_MASK (7 << SCU_D2PLL_ODIV_SHIFT)
130 #define SCU_D2PLL_SIC_SHIFT 22
131 #define SCU_D2PLL_SIC_MASK (0x1f << SCU_D2PLL_SIC_SHIFT)
132 #define SCU_D2PLL_SIP_SHIFT 27
133 #define SCU_D2PLL_SIP_MASK (0x1f << SCU_D2PLL_SIP_SHIFT)
135 #define SCU_CLKDUTY_DCLK_SHIFT 0
136 #define SCU_CLKDUTY_DCLK_MASK (0x3f << SCU_CLKDUTY_DCLK_SHIFT)
137 #define SCU_CLKDUTY_RGMII1TXCK_SHIFT 8
138 #define SCU_CLKDUTY_RGMII1TXCK_MASK (0x7f << SCU_CLKDUTY_RGMII1TXCK_SHIFT)
139 #define SCU_CLKDUTY_RGMII2TXCK_SHIFT 16
140 #define SCU_CLKDUTY_RGMII2TXCK_MASK (0x7f << SCU_CLKDUTY_RGMII2TXCK_SHIFT)
144 struct ast2500_clk_priv {
145 struct ast2500_scu *scu;
153 u32 freq_counter_ctrl;
154 u32 freq_counter_cmp;
163 u32 vga_handshake[2];
176 u32 mac_clk_delay_100M;
177 u32 mac_clk_delay_10M;
185 u32 freerun_counter_ext;
186 u32 clk_duty_meas_ctrl;
187 u32 clk_duty_meas_res;
189 /* The next registers are not key-protected */
190 struct ast2500_cpu2 {
196 u32 d_pll_ext_param[3];
197 u32 d2_pll_ext_param[3];
198 u32 mh_pll_ext_param;
206 u32 reloc_ctrl_decode[2];
208 u32 shared_sram_decode[2];
217 * ast_get_clk() - get a pointer to Clock Driver
219 * @devp, OUT - pointer to Clock Driver
220 * @return zero on success, error code (< 0) otherwise.
222 int ast_get_clk(struct udevice **devp);
225 * ast_get_scu() - get a pointer to SCU registers
227 * @return pointer to struct ast2500_scu on success, ERR_PTR otherwise
229 void *ast_get_scu(void);
232 * ast_scu_unlock() - unlock protected registers
234 * @scu, pointer to ast2500_scu
236 void ast_scu_unlock(struct ast2500_scu *scu);
239 * ast_scu_lock() - lock protected registers
241 * @scu, pointer to ast2500_scu
243 void ast_scu_lock(struct ast2500_scu *scu);
245 #endif /* __ASSEMBLY__ */
247 #endif /* _ASM_ARCH_SCU_AST2500_H */