arm: am437: Fix offset for USB registers
[platform/kernel/u-boot.git] / arch / arm / include / asm / arch-am33xx / hardware_am43xx.h
1 /*
2  * hardware_am43xx.h
3  *
4  * AM43xx hardware specific header
5  *
6  * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
7  *
8  * SPDX-License-Identifier:     GPL-2.0+
9  */
10
11 #ifndef __AM43XX_HARDWARE_AM43XX_H
12 #define __AM43XX_HARDWARE_AM43XX_H
13
14 /* Module base addresses */
15
16 /* UART Base Address */
17 #define UART0_BASE                      0x44E09000
18
19 /* GPIO Base address */
20 #define GPIO2_BASE                      0x481AC000
21
22 /* Watchdog Timer */
23 #define WDT_BASE                        0x44E35000
24
25 /* Control Module Base Address */
26 #define CTRL_BASE                       0x44E10000
27 #define CTRL_DEVICE_BASE                0x44E10600
28
29 /* PRCM Base Address */
30 #define PRCM_BASE                       0x44DF0000
31 #define CM_WKUP                         0x44DF2800
32 #define CM_PER                          0x44DF8800
33
34 #define PRM_RSTCTRL                     (PRCM_BASE + 0x4000)
35 #define PRM_RSTST                       (PRM_RSTCTRL + 4)
36
37 /* VTP Base address */
38 #define VTP0_CTRL_ADDR                  0x44E10E0C
39 #define VTP1_CTRL_ADDR                  0x48140E10
40
41 /* DDR Base address */
42 #define DDR_PHY_CMD_ADDR                0x44E12000
43 #define DDR_PHY_DATA_ADDR               0x44E120C8
44 #define DDR_PHY_CMD_ADDR2               0x47C0C800
45 #define DDR_PHY_DATA_ADDR2              0x47C0C8C8
46 #define DDR_DATA_REGS_NR                2
47
48 /* CPSW Config space */
49 #define CPSW_MDIO_BASE                  0x4A101000
50
51 /* RTC base address */
52 #define RTC_BASE                        0x44E3E000
53
54 /* USB Clock Control */
55 #define PRM_PER_USB_OTG_SS0_CLKCTRL (CM_PER + 0x260)
56 #define PRM_PER_USB_OTG_SS1_CLKCTRL (CM_PER + 0x268)
57 #define USBOTGSSX_CLKCTRL_MODULE_EN     (1 << 1)
58 #define USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960 (1 << 8)
59
60 #define PRM_PER_USBPHYOCP2SCP0_CLKCTRL (CM_PER + 0x5b8)
61 #define PRM_PER_USBPHYOCP2SCP1_CLKCTRL (CM_PER + 0x5c0)
62 #define USBPHYOCPSCP_MODULE_EN  (1 << 1)
63
64 #endif /* __AM43XX_HARDWARE_AM43XX_H */