4 * AM33xx specific header file
6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
8 * SPDX-License-Identifier: GPL-2.0+
14 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
15 #include <asm/types.h>
16 #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
18 #include <asm/arch/hardware.h>
20 #define CL_BIT(x) (0 << x)
22 /* Timer register bits */
23 #define TCLR_ST BIT(0) /* Start=1 Stop=0 */
24 #define TCLR_AR BIT(1) /* Auto reload */
25 #define TCLR_PRE BIT(5) /* Pre-scaler enable */
26 #define TCLR_PTV_SHIFT (2) /* Pre-scaler shift value */
27 #define TCLR_PRE_DISABLE CL_BIT(5) /* Pre-scalar disable */
28 #define TCLR_CE BIT(6) /* compare mode enable */
29 #define TCLR_SCPWM BIT(7) /* pwm outpin behaviour */
30 #define TCLR_TCM BIT(8) /* edge detection of input pin*/
31 #define TCLR_TRG_SHIFT (10) /* trigmode on pwm outpin */
32 #define TCLR_PT BIT(12) /* pulse/toggle mode of outpin*/
33 #define TCLR_CAPTMODE BIT(13) /* capture mode */
34 #define TCLR_GPOCFG BIT(14) /* 0=output,1=input */
36 #define TCFG_RESET BIT(0) /* software reset */
37 #define TCFG_EMUFREE BIT(1) /* behaviour of tmr on debug */
38 #define TCFG_IDLEMOD_SHIFT (2) /* power management */
40 /* cpu-id for AM43XX AM33XX and TI81XX family */
44 #define DEVICE_ID (CTRL_BASE + 0x0600)
45 #define DEVICE_ID_MASK 0x1FFF
46 #define PACKAGE_TYPE_SHIFT 16
47 #define PACKAGE_TYPE_MASK (3 << 16)
50 #define PACKAGE_TYPE_UNDEFINED 0x0
51 #define PACKAGE_TYPE_ZCZ 0x1
52 #define PACKAGE_TYPE_ZCE 0x2
53 #define PACKAGE_TYPE_RESERVED 0x3
55 /* MPU max frequencies */
56 #define AM335X_ZCZ_300 0x1FEF
57 #define AM335X_ZCZ_600 0x1FAF
58 #define AM335X_ZCZ_720 0x1F2F
59 #define AM335X_ZCZ_800 0x1E2F
60 #define AM335X_ZCZ_1000 0x1C2F
61 #define AM335X_ZCE_300 0x1FDF
62 #define AM335X_ZCE_600 0x1F9F
64 /* This gives the status of the boot mode pins on the evm */
65 #define SYSBOOT_MASK (BIT(0) | BIT(1) | BIT(2)\
68 #define PRM_RSTCTRL_RESET 0x01
69 #define PRM_RSTST_WARM_RESET_MASK 0x232
71 #ifndef __KERNEL_STRICT_NAMES
73 #include <asm/ti-common/omap_wdt.h>
76 /* Encapsulating core pll registers */
78 unsigned int wkclkstctrl; /* offset 0x00 */
79 unsigned int wkctrlclkctrl; /* offset 0x04 */
80 unsigned int wkgpio0clkctrl; /* offset 0x08 */
81 unsigned int wkl4wkclkctrl; /* offset 0x0c */
82 unsigned int timer0clkctrl; /* offset 0x10 */
83 unsigned int resv2[3];
84 unsigned int idlestdpllmpu; /* offset 0x20 */
85 unsigned int sscdeltamstepdllmpu; /* off 0x24 */
86 unsigned int sscmodfreqdivdpllmpu; /* off 0x28 */
87 unsigned int clkseldpllmpu; /* offset 0x2c */
88 unsigned int resv4[1];
89 unsigned int idlestdpllddr; /* offset 0x34 */
90 unsigned int resv5[2];
91 unsigned int clkseldpllddr; /* offset 0x40 */
92 unsigned int resv6[4];
93 unsigned int clkseldplldisp; /* offset 0x54 */
94 unsigned int resv7[1];
95 unsigned int idlestdpllcore; /* offset 0x5c */
96 unsigned int resv8[2];
97 unsigned int clkseldpllcore; /* offset 0x68 */
98 unsigned int resv9[1];
99 unsigned int idlestdpllper; /* offset 0x70 */
100 unsigned int resv10[2];
101 unsigned int clkdcoldodpllper; /* offset 0x7c */
102 unsigned int divm4dpllcore; /* offset 0x80 */
103 unsigned int divm5dpllcore; /* offset 0x84 */
104 unsigned int clkmoddpllmpu; /* offset 0x88 */
105 unsigned int clkmoddpllper; /* offset 0x8c */
106 unsigned int clkmoddpllcore; /* offset 0x90 */
107 unsigned int clkmoddpllddr; /* offset 0x94 */
108 unsigned int clkmoddplldisp; /* offset 0x98 */
109 unsigned int clkseldpllper; /* offset 0x9c */
110 unsigned int divm2dpllddr; /* offset 0xA0 */
111 unsigned int divm2dplldisp; /* offset 0xA4 */
112 unsigned int divm2dpllmpu; /* offset 0xA8 */
113 unsigned int divm2dpllper; /* offset 0xAC */
114 unsigned int resv11[1];
115 unsigned int wkup_uart0ctrl; /* offset 0xB4 */
116 unsigned int wkup_i2c0ctrl; /* offset 0xB8 */
117 unsigned int wkup_adctscctrl; /* offset 0xBC */
119 unsigned int timer1clkctrl; /* offset 0xC4 */
120 unsigned int resv13[4];
121 unsigned int divm6dpllcore; /* offset 0xD8 */
125 * Encapsulating peripheral functional clocks
129 unsigned int l4lsclkstctrl; /* offset 0x00 */
130 unsigned int l3sclkstctrl; /* offset 0x04 */
131 unsigned int l4fwclkstctrl; /* offset 0x08 */
132 unsigned int l3clkstctrl; /* offset 0x0c */
134 unsigned int cpgmac0clkctrl; /* offset 0x14 */
135 unsigned int lcdclkctrl; /* offset 0x18 */
136 unsigned int usb0clkctrl; /* offset 0x1C */
138 unsigned int tptc0clkctrl; /* offset 0x24 */
139 unsigned int emifclkctrl; /* offset 0x28 */
140 unsigned int ocmcramclkctrl; /* offset 0x2c */
141 unsigned int gpmcclkctrl; /* offset 0x30 */
142 unsigned int mcasp0clkctrl; /* offset 0x34 */
143 unsigned int uart5clkctrl; /* offset 0x38 */
144 unsigned int mmc0clkctrl; /* offset 0x3C */
145 unsigned int elmclkctrl; /* offset 0x40 */
146 unsigned int i2c2clkctrl; /* offset 0x44 */
147 unsigned int i2c1clkctrl; /* offset 0x48 */
148 unsigned int spi0clkctrl; /* offset 0x4C */
149 unsigned int spi1clkctrl; /* offset 0x50 */
150 unsigned int resv3[3];
151 unsigned int l4lsclkctrl; /* offset 0x60 */
152 unsigned int l4fwclkctrl; /* offset 0x64 */
153 unsigned int mcasp1clkctrl; /* offset 0x68 */
154 unsigned int uart1clkctrl; /* offset 0x6C */
155 unsigned int uart2clkctrl; /* offset 0x70 */
156 unsigned int uart3clkctrl; /* offset 0x74 */
157 unsigned int uart4clkctrl; /* offset 0x78 */
158 unsigned int timer7clkctrl; /* offset 0x7C */
159 unsigned int timer2clkctrl; /* offset 0x80 */
160 unsigned int timer3clkctrl; /* offset 0x84 */
161 unsigned int timer4clkctrl; /* offset 0x88 */
162 unsigned int resv4[8];
163 unsigned int gpio1clkctrl; /* offset 0xAC */
164 unsigned int gpio2clkctrl; /* offset 0xB0 */
165 unsigned int gpio3clkctrl; /* offset 0xB4 */
167 unsigned int tpccclkctrl; /* offset 0xBC */
168 unsigned int dcan0clkctrl; /* offset 0xC0 */
169 unsigned int dcan1clkctrl; /* offset 0xC4 */
171 unsigned int epwmss1clkctrl; /* offset 0xCC */
172 unsigned int emiffwclkctrl; /* offset 0xD0 */
173 unsigned int epwmss0clkctrl; /* offset 0xD4 */
174 unsigned int epwmss2clkctrl; /* offset 0xD8 */
175 unsigned int l3instrclkctrl; /* offset 0xDC */
176 unsigned int l3clkctrl; /* Offset 0xE0 */
177 unsigned int resv8[2];
178 unsigned int timer5clkctrl; /* offset 0xEC */
179 unsigned int timer6clkctrl; /* offset 0xF0 */
180 unsigned int mmc1clkctrl; /* offset 0xF4 */
181 unsigned int mmc2clkctrl; /* offset 0xF8 */
182 unsigned int resv9[8];
183 unsigned int l4hsclkstctrl; /* offset 0x11C */
184 unsigned int l4hsclkctrl; /* offset 0x120 */
185 unsigned int resv10[8];
186 unsigned int cpswclkstctrl; /* offset 0x144 */
187 unsigned int lcdcclkstctrl; /* offset 0x148 */
190 /* Encapsulating Display pll registers */
193 unsigned int clktimer7clk; /* offset 0x04 */
194 unsigned int clktimer2clk; /* offset 0x08 */
195 unsigned int clktimer3clk; /* offset 0x0C */
196 unsigned int clktimer4clk; /* offset 0x10 */
198 unsigned int clktimer5clk; /* offset 0x18 */
199 unsigned int clktimer6clk; /* offset 0x1C */
200 unsigned int resv3[2];
201 unsigned int clktimer1clk; /* offset 0x28 */
202 unsigned int resv4[2];
203 unsigned int clklcdcpixelclk; /* offset 0x34 */
206 struct prm_device_inst {
207 unsigned int prm_rstctrl;
208 unsigned int prm_rsttime;
209 unsigned int prm_rstst;
212 /* Encapsulating core pll registers */
214 unsigned int resv0[136];
215 unsigned int wkl4wkclkctrl; /* offset 0x220 */
216 unsigned int resv1[7];
217 unsigned int usbphy0clkctrl; /* offset 0x240 */
218 unsigned int resv112;
219 unsigned int usbphy1clkctrl; /* offset 0x248 */
220 unsigned int resv113[45];
221 unsigned int wkclkstctrl; /* offset 0x300 */
222 unsigned int resv2[15];
223 unsigned int wkup_i2c0ctrl; /* offset 0x340 */
225 unsigned int wkup_uart0ctrl; /* offset 0x348 */
226 unsigned int resv4[5];
227 unsigned int wkctrlclkctrl; /* offset 0x360 */
229 unsigned int wkgpio0clkctrl; /* offset 0x368 */
231 unsigned int resv6[109];
232 unsigned int clkmoddpllcore; /* offset 0x520 */
233 unsigned int idlestdpllcore; /* offset 0x524 */
235 unsigned int clkseldpllcore; /* offset 0x52C */
236 unsigned int resv7[2];
237 unsigned int divm4dpllcore; /* offset 0x538 */
238 unsigned int divm5dpllcore; /* offset 0x53C */
239 unsigned int divm6dpllcore; /* offset 0x540 */
241 unsigned int resv8[7];
242 unsigned int clkmoddpllmpu; /* offset 0x560 */
243 unsigned int idlestdpllmpu; /* offset 0x564 */
245 unsigned int clkseldpllmpu; /* offset 0x56c */
246 unsigned int divm2dpllmpu; /* offset 0x570 */
248 unsigned int resv10[11];
249 unsigned int clkmoddpllddr; /* offset 0x5A0 */
250 unsigned int idlestdpllddr; /* offset 0x5A4 */
252 unsigned int clkseldpllddr; /* offset 0x5AC */
253 unsigned int divm2dpllddr; /* offset 0x5B0 */
255 unsigned int resv12[11];
256 unsigned int clkmoddpllper; /* offset 0x5E0 */
257 unsigned int idlestdpllper; /* offset 0x5E4 */
259 unsigned int clkseldpllper; /* offset 0x5EC */
260 unsigned int divm2dpllper; /* offset 0x5F0 */
261 unsigned int resv14[8];
262 unsigned int clkdcoldodpllper; /* offset 0x614 */
264 unsigned int resv15[2];
265 unsigned int clkmoddplldisp; /* offset 0x620 */
266 unsigned int resv16[2];
267 unsigned int clkseldplldisp; /* offset 0x62C */
268 unsigned int divm2dplldisp; /* offset 0x630 */
272 * Encapsulating peripheral functional clocks
276 unsigned int l3clkstctrl; /* offset 0x00 */
277 unsigned int resv0[7];
278 unsigned int l3clkctrl; /* Offset 0x20 */
279 unsigned int resv112[7];
280 unsigned int l3instrclkctrl; /* offset 0x40 */
281 unsigned int resv2[3];
282 unsigned int ocmcramclkctrl; /* offset 0x50 */
283 unsigned int resv3[9];
284 unsigned int tpccclkctrl; /* offset 0x78 */
286 unsigned int tptc0clkctrl; /* offset 0x80 */
288 unsigned int resv5[7];
289 unsigned int l4hsclkctrl; /* offset 0x0A0 */
291 unsigned int l4fwclkctrl; /* offset 0x0A8 */
292 unsigned int resv7[85];
293 unsigned int l3sclkstctrl; /* offset 0x200 */
294 unsigned int resv8[7];
295 unsigned int gpmcclkctrl; /* offset 0x220 */
296 unsigned int resv9[5];
297 unsigned int mcasp0clkctrl; /* offset 0x238 */
299 unsigned int mcasp1clkctrl; /* offset 0x240 */
301 unsigned int mmc2clkctrl; /* offset 0x248 */
302 unsigned int resv12[3];
303 unsigned int qspiclkctrl; /* offset 0x258 */
304 unsigned int resv121;
305 unsigned int usb0clkctrl; /* offset 0x260 */
306 unsigned int resv122;
307 unsigned int usb1clkctrl; /* offset 0x268 */
308 unsigned int resv13[101];
309 unsigned int l4lsclkstctrl; /* offset 0x400 */
310 unsigned int resv14[7];
311 unsigned int l4lsclkctrl; /* offset 0x420 */
313 unsigned int dcan0clkctrl; /* offset 0x428 */
315 unsigned int dcan1clkctrl; /* offset 0x430 */
316 unsigned int resv17[13];
317 unsigned int elmclkctrl; /* offset 0x468 */
319 unsigned int resv18[3];
320 unsigned int gpio1clkctrl; /* offset 0x478 */
322 unsigned int gpio2clkctrl; /* offset 0x480 */
324 unsigned int gpio3clkctrl; /* offset 0x488 */
326 unsigned int gpio4clkctrl; /* offset 0x490 */
328 unsigned int gpio5clkctrl; /* offset 0x498 */
329 unsigned int resv21[3];
331 unsigned int i2c1clkctrl; /* offset 0x4A8 */
333 unsigned int i2c2clkctrl; /* offset 0x4B0 */
334 unsigned int resv23[3];
335 unsigned int mmc0clkctrl; /* offset 0x4C0 */
337 unsigned int mmc1clkctrl; /* offset 0x4C8 */
339 unsigned int resv25[13];
340 unsigned int spi0clkctrl; /* offset 0x500 */
342 unsigned int spi1clkctrl; /* offset 0x508 */
343 unsigned int resv27[9];
344 unsigned int timer2clkctrl; /* offset 0x530 */
346 unsigned int timer3clkctrl; /* offset 0x538 */
348 unsigned int timer4clkctrl; /* offset 0x540 */
349 unsigned int resv30[5];
350 unsigned int timer7clkctrl; /* offset 0x558 */
352 unsigned int resv31[9];
353 unsigned int uart1clkctrl; /* offset 0x580 */
355 unsigned int uart2clkctrl; /* offset 0x588 */
357 unsigned int uart3clkctrl; /* offset 0x590 */
359 unsigned int uart4clkctrl; /* offset 0x598 */
361 unsigned int uart5clkctrl; /* offset 0x5A0 */
362 unsigned int resv36[5];
363 unsigned int usbphyocp2scp0clkctrl; /* offset 0x5B8 */
364 unsigned int resv361;
365 unsigned int usbphyocp2scp1clkctrl; /* offset 0x5C0 */
366 unsigned int resv3611[79];
368 unsigned int emifclkstctrl; /* offset 0x700 */
369 unsigned int resv362[7];
370 unsigned int emifclkctrl; /* offset 0x720 */
371 unsigned int resv37[3];
372 unsigned int emiffwclkctrl; /* offset 0x730 */
373 unsigned int resv371;
374 unsigned int otfaemifclkctrl; /* offset 0x738 */
375 unsigned int resv38[57];
376 unsigned int lcdclkctrl; /* offset 0x820 */
377 unsigned int resv39[183];
378 unsigned int cpswclkstctrl; /* offset 0xB00 */
379 unsigned int resv40[7];
380 unsigned int cpgmac0clkctrl; /* offset 0xB20 */
383 struct cm_device_inst {
384 unsigned int cm_clkout1_ctrl;
385 unsigned int cm_dll_ctrl;
388 struct prm_device_inst {
389 unsigned int prm_rstctrl;
390 unsigned int prm_rstst;
395 unsigned int clktimer2clk; /* offset 0x04 */
396 unsigned int resv2[11];
397 unsigned int clkselmacclk; /* offset 0x34 */
399 #endif /* CONFIG_AM43XX */
401 /* Control Module RTC registers */
403 unsigned int rtcclkctrl; /* offset 0x0 */
404 unsigned int clkstctrl; /* offset 0x4 */
407 /* Timer 32 bit registers */
409 unsigned int tidr; /* offset 0x00 */
410 unsigned char res1[12];
411 unsigned int tiocp_cfg; /* offset 0x10 */
412 unsigned char res2[12];
413 unsigned int tier; /* offset 0x20 */
414 unsigned int tistatr; /* offset 0x24 */
415 unsigned int tistat; /* offset 0x28 */
416 unsigned int tisr; /* offset 0x2c */
417 unsigned int tcicr; /* offset 0x30 */
418 unsigned int twer; /* offset 0x34 */
419 unsigned int tclr; /* offset 0x38 */
420 unsigned int tcrr; /* offset 0x3c */
421 unsigned int tldr; /* offset 0x40 */
422 unsigned int ttgr; /* offset 0x44 */
423 unsigned int twpc; /* offset 0x48 */
424 unsigned int tmar; /* offset 0x4c */
425 unsigned int tcar1; /* offset 0x50 */
426 unsigned int tscir; /* offset 0x54 */
427 unsigned int tcar2; /* offset 0x58 */
432 unsigned int resv1[21];
433 unsigned int uartsyscfg; /* offset 0x54 */
434 unsigned int uartsyssts; /* offset 0x58 */
439 unsigned int vtp0ctrlreg;
442 /* Control Status Register */
444 unsigned int resv1[16];
445 unsigned int statusreg; /* ofset 0x40 */
446 unsigned int resv2[51];
447 unsigned int secure_emif_sdram_config; /* offset 0x0110 */
448 unsigned int resv3[319];
449 unsigned int dev_attr;
452 /* AM33XX GPIO registers */
453 #define OMAP_GPIO_REVISION 0x0000
454 #define OMAP_GPIO_SYSCONFIG 0x0010
455 #define OMAP_GPIO_SYSSTATUS 0x0114
456 #define OMAP_GPIO_IRQSTATUS1 0x002c
457 #define OMAP_GPIO_IRQSTATUS2 0x0030
458 #define OMAP_GPIO_IRQSTATUS_SET_0 0x0034
459 #define OMAP_GPIO_IRQSTATUS_SET_1 0x0038
460 #define OMAP_GPIO_CTRL 0x0130
461 #define OMAP_GPIO_OE 0x0134
462 #define OMAP_GPIO_DATAIN 0x0138
463 #define OMAP_GPIO_DATAOUT 0x013c
464 #define OMAP_GPIO_LEVELDETECT0 0x0140
465 #define OMAP_GPIO_LEVELDETECT1 0x0144
466 #define OMAP_GPIO_RISINGDETECT 0x0148
467 #define OMAP_GPIO_FALLINGDETECT 0x014c
468 #define OMAP_GPIO_DEBOUNCE_EN 0x0150
469 #define OMAP_GPIO_DEBOUNCE_VAL 0x0154
470 #define OMAP_GPIO_CLEARDATAOUT 0x0190
471 #define OMAP_GPIO_SETDATAOUT 0x0194
473 /* Control Device Register */
475 /* Control Device Register */
476 #define MREQPRIO_0_SAB_INIT1_MASK 0xFFFFFF8F
477 #define MREQPRIO_0_SAB_INIT0_MASK 0xFFFFFFF8
478 #define MREQPRIO_1_DSS_MASK 0xFFFFFF8F
481 unsigned int deviceid; /* offset 0x00 */
482 unsigned int resv1[7];
483 unsigned int usb_ctrl0; /* offset 0x20 */
485 unsigned int usb_ctrl1; /* offset 0x28 */
487 unsigned int macid0l; /* offset 0x30 */
488 unsigned int macid0h; /* offset 0x34 */
489 unsigned int macid1l; /* offset 0x38 */
490 unsigned int macid1h; /* offset 0x3c */
491 unsigned int resv4[4];
492 unsigned int miisel; /* offset 0x50 */
493 unsigned int resv5[7];
494 unsigned int mreqprio_0; /* offset 0x70 */
495 unsigned int mreqprio_1; /* offset 0x74 */
496 unsigned int resv6[97];
497 unsigned int efuse_sma; /* offset 0x1FC */
500 /* Bandwidth Limiter Portion of the L3Fast Configuration Register */
501 #define BW_LIMITER_BW_FRAC_MASK 0xFFFFFFE0
502 #define BW_LIMITER_BW_INT_MASK 0xFFFFFFF0
503 #define BW_LIMITER_BW_WATERMARK_MASK 0xFFFFF800
505 struct l3f_cfg_bwlimiter {
507 u32 modena_init0_bw_fractional;
508 u32 modena_init0_bw_integer;
509 u32 modena_init0_watermark_0;
512 /* gmii_sel register defines */
513 #define GMII1_SEL_MII 0x0
514 #define GMII1_SEL_RMII 0x1
515 #define GMII1_SEL_RGMII 0x2
516 #define GMII2_SEL_MII 0x0
517 #define GMII2_SEL_RMII 0x4
518 #define GMII2_SEL_RGMII 0x8
519 #define RGMII1_IDMODE BIT(4)
520 #define RGMII2_IDMODE BIT(5)
521 #define RMII1_IO_CLK_EN BIT(6)
522 #define RMII2_IO_CLK_EN BIT(7)
524 #define MII_MODE_ENABLE (GMII1_SEL_MII | GMII2_SEL_MII)
525 #define RMII_MODE_ENABLE (GMII1_SEL_RMII | GMII2_SEL_RMII)
526 #define RGMII_MODE_ENABLE (GMII1_SEL_RGMII | GMII2_SEL_RGMII)
527 #define RGMII_INT_DELAY (RGMII1_IDMODE | RGMII2_IDMODE)
528 #define RMII_CHIPCKL_ENABLE (RMII1_IO_CLK_EN | RMII2_IO_CLK_EN)
533 unsigned int sysconfig;
534 unsigned int clkconfig;
535 unsigned int clkstatus;
537 #define ECAP_CLK_EN BIT(0)
538 #define ECAP_CLK_STOP_REQ BIT(1)
539 #define EPWM_CLK_EN BIT(8)
540 #define EPWM_CLK_STOP_REQ BIT(9)
542 struct pwmss_ecap_regs {
549 unsigned int resv1[4];
550 unsigned short ecctl1;
551 unsigned short ecctl2;
554 struct pwmss_epwm_regs {
555 unsigned short tbctl;
556 unsigned short tbsts;
557 unsigned short tbphshr;
558 unsigned short tbphs;
559 unsigned short tbcnt;
560 unsigned short tbprd;
562 unsigned short cmpctl;
563 unsigned short cmpahr;
566 unsigned short aqctla;
567 unsigned short aqctlb;
568 unsigned short aqsfrc;
569 unsigned short aqcsfrc;
570 unsigned short dbctl;
571 unsigned short dbred;
572 unsigned short dbfed;
573 unsigned short tzsel;
574 unsigned short tzctl;
575 unsigned short tzflg;
576 unsigned short tzclr;
577 unsigned short tzfrc;
578 unsigned short etsel;
580 unsigned short etflg;
581 unsigned short etclr;
582 unsigned short etfrc;
583 unsigned short pcctl;
584 unsigned int res2[66];
585 unsigned short hrcnfg;
588 /* Capture Control register 2 */
589 #define ECTRL2_SYNCOSEL_MASK (0x03 << 6)
590 #define ECTRL2_MDSL_ECAP BIT(9)
591 #define ECTRL2_CTRSTP_FREERUN BIT(4)
592 #define ECTRL2_PLSL_LOW BIT(10)
593 #define ECTRL2_SYNC_EN BIT(5)
595 #endif /* __ASSEMBLY__ */
596 #endif /* __KERNEL_STRICT_NAMES */
598 #endif /* _AM33XX_CPU_H */