arch/arm/imx-common/ddrmc-vf610.c

   1 /*
   2  * Copyright 2015 Toradex, Inc.
   3  *
   4  * Based on vf610twr:
   5  * Copyright 2013 Freescale Semiconductor, Inc.
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <asm/io.h>
  11 #include <asm/arch/imx-regs.h>
  12 #include <asm/arch/iomux-vf610.h>
  13 #include <asm/arch/ddrmc-vf610.h>
  14
  15 void ddrmc_setup_iomux(void)
  16 {
  17         static const iomux_v3_cfg_t ddr_pads[] = {
  18                 VF610_PAD_DDR_A15__DDR_A_15,
  19                 VF610_PAD_DDR_A14__DDR_A_14,
  20                 VF610_PAD_DDR_A13__DDR_A_13,
  21                 VF610_PAD_DDR_A12__DDR_A_12,
  22                 VF610_PAD_DDR_A11__DDR_A_11,
  23                 VF610_PAD_DDR_A10__DDR_A_10,
  24                 VF610_PAD_DDR_A9__DDR_A_9,
  25                 VF610_PAD_DDR_A8__DDR_A_8,
  26                 VF610_PAD_DDR_A7__DDR_A_7,
  27                 VF610_PAD_DDR_A6__DDR_A_6,
  28                 VF610_PAD_DDR_A5__DDR_A_5,
  29                 VF610_PAD_DDR_A4__DDR_A_4,
  30                 VF610_PAD_DDR_A3__DDR_A_3,
  31                 VF610_PAD_DDR_A2__DDR_A_2,
  32                 VF610_PAD_DDR_A1__DDR_A_1,
  33                 VF610_PAD_DDR_A0__DDR_A_0,
  34                 VF610_PAD_DDR_BA2__DDR_BA_2,
  35                 VF610_PAD_DDR_BA1__DDR_BA_1,
  36                 VF610_PAD_DDR_BA0__DDR_BA_0,
  37                 VF610_PAD_DDR_CAS__DDR_CAS_B,
  38                 VF610_PAD_DDR_CKE__DDR_CKE_0,
  39                 VF610_PAD_DDR_CLK__DDR_CLK_0,
  40                 VF610_PAD_DDR_CS__DDR_CS_B_0,
  41                 VF610_PAD_DDR_D15__DDR_D_15,
  42                 VF610_PAD_DDR_D14__DDR_D_14,
  43                 VF610_PAD_DDR_D13__DDR_D_13,
  44                 VF610_PAD_DDR_D12__DDR_D_12,
  45                 VF610_PAD_DDR_D11__DDR_D_11,
  46                 VF610_PAD_DDR_D10__DDR_D_10,
  47                 VF610_PAD_DDR_D9__DDR_D_9,
  48                 VF610_PAD_DDR_D8__DDR_D_8,
  49                 VF610_PAD_DDR_D7__DDR_D_7,
  50                 VF610_PAD_DDR_D6__DDR_D_6,
  51                 VF610_PAD_DDR_D5__DDR_D_5,
  52                 VF610_PAD_DDR_D4__DDR_D_4,
  53                 VF610_PAD_DDR_D3__DDR_D_3,
  54                 VF610_PAD_DDR_D2__DDR_D_2,
  55                 VF610_PAD_DDR_D1__DDR_D_1,
  56                 VF610_PAD_DDR_D0__DDR_D_0,
  57                 VF610_PAD_DDR_DQM1__DDR_DQM_1,
  58                 VF610_PAD_DDR_DQM0__DDR_DQM_0,
  59                 VF610_PAD_DDR_DQS1__DDR_DQS_1,
  60                 VF610_PAD_DDR_DQS0__DDR_DQS_0,
  61                 VF610_PAD_DDR_RAS__DDR_RAS_B,
  62                 VF610_PAD_DDR_WE__DDR_WE_B,
  63                 VF610_PAD_DDR_ODT1__DDR_ODT_0,
  64                 VF610_PAD_DDR_ODT0__DDR_ODT_1,
  65                 VF610_PAD_DDR_RESETB,
  66         };
  67
  68         imx_iomux_v3_setup_multiple_pads(ddr_pads, ARRAY_SIZE(ddr_pads));
  69 }
  70
  71 void ddrmc_phy_init(void)
  72 {
  73         struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
  74
  75         writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[0]);
  76         writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[16]);
  77         writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[32]);
  78
  79         writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[1]);
  80         writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[17]);
  81
  82         writel(DDRMC_PHY_CTRL, &ddrmr->phy[2]);
  83         writel(DDRMC_PHY_CTRL, &ddrmr->phy[18]);
  84         writel(DDRMC_PHY_CTRL, &ddrmr->phy[34]);
  85
  86         writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[3]);
  87         writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[19]);
  88         writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[35]);
  89
  90         writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[4]);
  91         writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[20]);
  92         writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[36]);
  93
  94         /* LPDDR2 only parameter */
  95         writel(DDRMC_PHY_OFF, &ddrmr->phy[49]);
  96
  97         writel(DDRMC_PHY50_DDR3_MODE |
  98                    DDRMC_PHY50_EN_SW_HALF_CYCLE, &ddrmr->phy[50]);
  99
 100         /* Processor Pad ODT settings */
 101         writel(DDRMC_PHY_PROC_PAD_ODT, &ddrmr->phy[52]);
 102 }
 103
 104 static void ddrmc_ctrl_lvl_init(struct ddrmc_lvl_info *lvl)
 105 {
 106         struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
 107         u32 cr102 = 0, cr105 = 0, cr106 = 0, cr110 = 0;
 108
 109         if (lvl->wrlvl_reg_en) {
 110                 writel(DDRMC_CR97_WRLVL_EN, &ddrmr->cr[97]);
 111                 writel(DDRMC_CR98_WRLVL_DL_0(lvl->wrlvl_dl_0), &ddrmr->cr[98]);
 112                 writel(DDRMC_CR99_WRLVL_DL_1(lvl->wrlvl_dl_1), &ddrmr->cr[99]);
 113         }
 114
 115         if (lvl->rdlvl_reg_en) {
 116                 cr102 |= DDRMC_CR102_RDLVL_REG_EN;
 117                 cr105 |= DDRMC_CR105_RDLVL_DL_0(lvl->rdlvl_dl_0);
 118                 cr110 |= DDRMC_CR110_RDLVL_DL_1(lvl->rdlvl_dl_1);
 119         }
 120
 121         if (lvl->rdlvl_gt_reg_en) {
 122                 cr102 |= DDRMC_CR102_RDLVL_GT_REGEN;
 123                 cr106 |= DDRMC_CR106_RDLVL_GTDL_0(lvl->rdlvl_gt_dl_0);
 124                 cr110 |= DDRMC_CR110_RDLVL_GTDL_1(lvl->rdlvl_gt_dl_1);
 125         }
 126
 127         writel(cr102, &ddrmr->cr[102]);
 128         writel(cr105, &ddrmr->cr[105]);
 129         writel(cr106, &ddrmr->cr[106]);
 130         writel(cr110, &ddrmr->cr[110]);
 131 }
 132
 133 void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
 134                                                   struct ddrmc_lvl_info *lvl,
 135                                                   int col_diff, int row_diff)
 136 {
 137         struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
 138
 139         writel(DDRMC_CR00_DRAM_CLASS_DDR3, &ddrmr->cr[0]);
 140         writel(DDRMC_CR02_DRAM_TINIT(timings->tinit), &ddrmr->cr[2]);
 141         writel(DDRMC_CR10_TRST_PWRON(timings->trst_pwron), &ddrmr->cr[10]);
 142
 143         writel(DDRMC_CR11_CKE_INACTIVE(timings->cke_inactive), &ddrmr->cr[11]);
 144         writel(DDRMC_CR12_WRLAT(timings->wrlat) |
 145                    DDRMC_CR12_CASLAT_LIN(timings->caslat_lin), &ddrmr->cr[12]);
 146         writel(DDRMC_CR13_TRC(timings->trc) | DDRMC_CR13_TRRD(timings->trrd) |
 147                    DDRMC_CR13_TCCD(timings->tccd), &ddrmr->cr[13]);
 148         writel(DDRMC_CR14_TFAW(timings->tfaw) | DDRMC_CR14_TRP(timings->trp) |
 149                    DDRMC_CR14_TWTR(timings->twtr) |
 150                    DDRMC_CR14_TRAS_MIN(timings->tras_min), &ddrmr->cr[14]);
 151         writel(DDRMC_CR16_TMRD(timings->tmrd) |
 152                    DDRMC_CR16_TRTP(timings->trtp), &ddrmr->cr[16]);
 153         writel(DDRMC_CR17_TRAS_MAX(timings->tras_max) |
 154                    DDRMC_CR17_TMOD(timings->tmod), &ddrmr->cr[17]);
 155         writel(DDRMC_CR18_TCKESR(timings->tckesr) |
 156                    DDRMC_CR18_TCKE(timings->tcke), &ddrmr->cr[18]);
 157
 158         writel(DDRMC_CR20_AP_EN, &ddrmr->cr[20]);
 159         writel(DDRMC_CR21_TRCD_INT(timings->trcd_int) |
 160                    DDRMC_CR21_CCMAP_EN, &ddrmr->cr[21]);
 161
 162         writel(DDRMC_CR22_TDAL(timings->tdal), &ddrmr->cr[22]);
 163         writel(DDRMC_CR23_BSTLEN(3) |
 164                    DDRMC_CR23_TDLL(timings->tdll), &ddrmr->cr[23]);
 165         writel(DDRMC_CR24_TRP_AB(timings->trp_ab), &ddrmr->cr[24]);
 166
 167         writel(DDRMC_CR25_TREF_EN, &ddrmr->cr[25]);
 168         writel(DDRMC_CR26_TREF(timings->tref) |
 169                    DDRMC_CR26_TRFC(timings->trfc), &ddrmr->cr[26]);
 170         writel(DDRMC_CR28_TREF_INT(0), &ddrmr->cr[28]);
 171         writel(DDRMC_CR29_TPDEX(timings->tpdex), &ddrmr->cr[29]);
 172
 173         writel(DDRMC_CR30_TXPDLL(timings->txpdll), &ddrmr->cr[30]);
 174         writel(DDRMC_CR31_TXSNR(timings->txsnr) |
 175                    DDRMC_CR31_TXSR(timings->txsr), &ddrmr->cr[31]);
 176         writel(DDRMC_CR33_EN_QK_SREF, &ddrmr->cr[33]);
 177         writel(DDRMC_CR34_CKSRX(timings->cksrx) |
 178                    DDRMC_CR34_CKSRE(timings->cksre), &ddrmr->cr[34]);
 179
 180         writel(DDRMC_CR38_FREQ_CHG_EN(0), &ddrmr->cr[38]);
 181         writel(DDRMC_CR39_PHY_INI_COM(1024) | DDRMC_CR39_PHY_INI_STA(16) |
 182                    DDRMC_CR39_FRQ_CH_DLLOFF(2), &ddrmr->cr[39]);
 183
 184         writel(DDRMC_CR41_PHY_INI_STRT_INI_DIS, &ddrmr->cr[41]);
 185         writel(DDRMC_CR48_MR1_DA_0(70) |
 186                    DDRMC_CR48_MR0_DA_0(1056), &ddrmr->cr[48]);
 187
 188         writel(DDRMC_CR66_ZQCL(timings->zqcl) |
 189                    DDRMC_CR66_ZQINIT(timings->zqinit), &ddrmr->cr[66]);
 190         writel(DDRMC_CR67_ZQCS(timings->zqcs), &ddrmr->cr[67]);
 191         writel(DDRMC_CR69_ZQ_ON_SREF_EX(2), &ddrmr->cr[69]);
 192
 193         writel(DDRMC_CR70_REF_PER_ZQ(timings->ref_per_zq), &ddrmr->cr[70]);
 194         writel(DDRMC_CR72_ZQCS_ROTATE(0), &ddrmr->cr[72]);
 195
 196         writel(DDRMC_CR73_APREBIT(timings->aprebit) |
 197                    DDRMC_CR73_COL_DIFF(col_diff) |
 198                    DDRMC_CR73_ROW_DIFF(row_diff), &ddrmr->cr[73]);
 199         writel(DDRMC_CR74_BANKSPLT_EN | DDRMC_CR74_ADDR_CMP_EN |
 200                    DDRMC_CR74_CMD_AGE_CNT(64) | DDRMC_CR74_AGE_CNT(64),
 201                    &ddrmr->cr[74]);
 202         writel(DDRMC_CR75_RW_PG_EN | DDRMC_CR75_RW_EN | DDRMC_CR75_PRI_EN |
 203                    DDRMC_CR75_PLEN, &ddrmr->cr[75]);
 204         writel(DDRMC_CR76_NQENT_ACTDIS(3) | DDRMC_CR76_D_RW_G_BKCN(3) |
 205                    DDRMC_CR76_W2R_SPLT_EN, &ddrmr->cr[76]);
 206         writel(DDRMC_CR77_CS_MAP | DDRMC_CR77_DI_RD_INTLEAVE |
 207                    DDRMC_CR77_SWAP_EN, &ddrmr->cr[77]);
 208         writel(DDRMC_CR78_Q_FULLNESS(7) |
 209                    DDRMC_CR78_BUR_ON_FLY_BIT(12), &ddrmr->cr[78]);
 210         writel(DDRMC_CR79_CTLUPD_AREF(0), &ddrmr->cr[79]);
 211
 212         writel(DDRMC_CR82_INT_MASK, &ddrmr->cr[82]);
 213
 214         writel(DDRMC_CR87_ODT_WR_MAPCS0, &ddrmr->cr[87]);
 215         writel(DDRMC_CR88_TODTL_CMD(4), &ddrmr->cr[88]);
 216         writel(DDRMC_CR89_AODT_RWSMCS(2), &ddrmr->cr[89]);
 217
 218         writel(DDRMC_CR91_R2W_SMCSDL(2), &ddrmr->cr[91]);
 219         writel(DDRMC_CR96_WLMRD(timings->wlmrd) |
 220                    DDRMC_CR96_WLDQSEN(timings->wldqsen), &ddrmr->cr[96]);
 221
 222         if (lvl != NULL)
 223                 ddrmc_ctrl_lvl_init(lvl);
 224
 225         writel(DDRMC_CR117_AXI0_W_PRI(0) |
 226                    DDRMC_CR117_AXI0_R_PRI(0), &ddrmr->cr[117]);
 227         writel(DDRMC_CR118_AXI1_W_PRI(1) |
 228                    DDRMC_CR118_AXI1_R_PRI(1), &ddrmr->cr[118]);
 229
 230         writel(DDRMC_CR120_AXI0_PRI1_RPRI(2) |
 231                    DDRMC_CR120_AXI0_PRI0_RPRI(2), &ddrmr->cr[120]);
 232         writel(DDRMC_CR121_AXI0_PRI3_RPRI(2) |
 233                    DDRMC_CR121_AXI0_PRI2_RPRI(2), &ddrmr->cr[121]);
 234         writel(DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) |
 235                    DDRMC_CR122_AXI0_PRIRLX(100), &ddrmr->cr[122]);
 236         writel(DDRMC_CR123_AXI1_P_ODR_EN | DDRMC_CR123_AXI1_PRI3_RPRI(1) |
 237                    DDRMC_CR123_AXI1_PRI2_RPRI(1), &ddrmr->cr[123]);
 238         writel(DDRMC_CR124_AXI1_PRIRLX(100), &ddrmr->cr[124]);
 239
 240         writel(DDRMC_CR126_PHY_RDLAT(8), &ddrmr->cr[126]);
 241         writel(DDRMC_CR132_WRLAT_ADJ(5) |
 242                    DDRMC_CR132_RDLAT_ADJ(6), &ddrmr->cr[132]);
 243         writel(DDRMC_CR137_PHYCTL_DL(2), &ddrmr->cr[137]);
 244         writel(DDRMC_CR138_PHY_WRLV_MXDL(256) |
 245                    DDRMC_CR138_PHYDRAM_CK_EN(1), &ddrmr->cr[138]);
 246         writel(DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) |
 247                    DDRMC_CR139_PHY_WRLV_DLL(3) |
 248                    DDRMC_CR139_PHY_WRLV_EN(3), &ddrmr->cr[139]);
 249         writel(DDRMC_CR140_PHY_WRLV_WW(64), &ddrmr->cr[140]);
 250         writel(DDRMC_CR143_RDLV_GAT_MXDL(1536) |
 251                    DDRMC_CR143_RDLV_MXDL(128), &ddrmr->cr[143]);
 252         writel(DDRMC_CR144_PHY_RDLVL_RES(4) | DDRMC_CR144_PHY_RDLV_LOAD(7) |
 253                    DDRMC_CR144_PHY_RDLV_DLL(3) |
 254                    DDRMC_CR144_PHY_RDLV_EN(3), &ddrmr->cr[144]);
 255         writel(DDRMC_CR145_PHY_RDLV_RR(64), &ddrmr->cr[145]);
 256         writel(DDRMC_CR146_PHY_RDLVL_RESP(64), &ddrmr->cr[146]);
 257         writel(DDRMC_CR147_RDLV_RESP_MASK(983040), &ddrmr->cr[147]);
 258         writel(DDRMC_CR148_RDLV_GATE_RESP_MASK(983040), &ddrmr->cr[148]);
 259         writel(DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT(1) |
 260                    DDRMC_CR151_RDLVL_DQ_ZERO_CNT(1), &ddrmr->cr[151]);
 261
 262         writel(DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) |
 263                    DDRMC_CR154_PAD_ZQ_MODE(1) |
 264                    DDRMC_CR154_DDR_SEL_PAD_CONTR(3) |
 265                    DDRMC_CR154_PAD_ZQ_HW_FOR(1), &ddrmr->cr[154]);
 266         writel(DDRMC_CR155_PAD_ODT_BYTE1(2) |
 267                    DDRMC_CR155_PAD_ODT_BYTE0(2), &ddrmr->cr[155]);
 268         writel(DDRMC_CR158_TWR(6), &ddrmr->cr[158]);
 269         writel(DDRMC_CR161_ODT_EN(1) | DDRMC_CR161_TODTH_RD(2) |
 270                    DDRMC_CR161_TODTH_WR(2), &ddrmr->cr[161]);
 271
 272         ddrmc_phy_init();
 273
 274         writel(DDRMC_CR00_DRAM_CLASS_DDR3 | DDRMC_CR00_START, &ddrmr->cr[0]);
 275
 276         while (!(readl(&ddrmr->cr[80]) && 0x100))
 277                 udelay(10);
 278 }