arch/arm/dts/zynqmp.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * dts file for Xilinx ZynqMP
   4  *
   5  * (C) Copyright 2014 - 2021, Xilinx, Inc.
   6  *
   7  * Michal Simek <michal.simek@amd.com>
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  */
  14
  15 #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
  16 #include <dt-bindings/gpio/gpio.h>
  17 #include <dt-bindings/power/xlnx-zynqmp-power.h>
  18 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
  19
  20 / {
  21         compatible = "xlnx,zynqmp";
  22         #address-cells = <2>;
  23         #size-cells = <2>;
  24
  25         cpus {
  26                 #address-cells = <1>;
  27                 #size-cells = <0>;
  28
  29                 cpu0: cpu@0 {
  30                         compatible = "arm,cortex-a53";
  31                         device_type = "cpu";
  32                         enable-method = "psci";
  33                         operating-points-v2 = <&cpu_opp_table>;
  34                         reg = <0x0>;
  35                         cpu-idle-states = <&CPU_SLEEP_0>;
  36                         next-level-cache = <&L2>;
  37                 };
  38
  39                 cpu1: cpu@1 {
  40                         compatible = "arm,cortex-a53";
  41                         device_type = "cpu";
  42                         enable-method = "psci";
  43                         reg = <0x1>;
  44                         operating-points-v2 = <&cpu_opp_table>;
  45                         cpu-idle-states = <&CPU_SLEEP_0>;
  46                         next-level-cache = <&L2>;
  47                 };
  48
  49                 cpu2: cpu@2 {
  50                         compatible = "arm,cortex-a53";
  51                         device_type = "cpu";
  52                         enable-method = "psci";
  53                         reg = <0x2>;
  54                         operating-points-v2 = <&cpu_opp_table>;
  55                         cpu-idle-states = <&CPU_SLEEP_0>;
  56                         next-level-cache = <&L2>;
  57                 };
  58
  59                 cpu3: cpu@3 {
  60                         compatible = "arm,cortex-a53";
  61                         device_type = "cpu";
  62                         enable-method = "psci";
  63                         reg = <0x3>;
  64                         operating-points-v2 = <&cpu_opp_table>;
  65                         cpu-idle-states = <&CPU_SLEEP_0>;
  66                         next-level-cache = <&L2>;
  67                 };
  68
  69                 L2: l2-cache {
  70                         compatible = "cache";
  71                         cache-level = <2>;
  72                         cache-unified;
  73                 };
  74
  75                 idle-states {
  76                         entry-method = "psci";
  77
  78                         CPU_SLEEP_0: cpu-sleep-0 {
  79                                 compatible = "arm,idle-state";
  80                                 arm,psci-suspend-param = <0x40000000>;
  81                                 local-timer-stop;
  82                                 entry-latency-us = <300>;
  83                                 exit-latency-us = <600>;
  84                                 min-residency-us = <10000>;
  85                         };
  86                 };
  87         };
  88
  89         cpu_opp_table: opp-table-cpu {
  90                 compatible = "operating-points-v2";
  91                 opp-shared;
  92                 opp00 {
  93                         opp-hz = /bits/ 64 <1199999988>;
  94                         opp-microvolt = <1000000>;
  95                         clock-latency-ns = <500000>;
  96                 };
  97                 opp01 {
  98                         opp-hz = /bits/ 64 <599999994>;
  99                         opp-microvolt = <1000000>;
 100                         clock-latency-ns = <500000>;
 101                 };
 102                 opp02 {
 103                         opp-hz = /bits/ 64 <399999996>;
 104                         opp-microvolt = <1000000>;
 105                         clock-latency-ns = <500000>;
 106                 };
 107                 opp03 {
 108                         opp-hz = /bits/ 64 <299999997>;
 109                         opp-microvolt = <1000000>;
 110                         clock-latency-ns = <500000>;
 111                 };
 112         };
 113
 114         zynqmp_ipi: zynqmp_ipi {
 115                 bootph-all;
 116                 compatible = "xlnx,zynqmp-ipi-mailbox";
 117                 interrupt-parent = <&gic>;
 118                 interrupts = <0 35 4>;
 119                 xlnx,ipi-id = <0>;
 120                 #address-cells = <2>;
 121                 #size-cells = <2>;
 122                 ranges;
 123
 124                 ipi_mailbox_pmu1: mailbox@ff9905c0 {
 125                         bootph-all;
 126                         reg = <0x0 0xff9905c0 0x0 0x20>,
 127                               <0x0 0xff9905e0 0x0 0x20>,
 128                               <0x0 0xff990e80 0x0 0x20>,
 129                               <0x0 0xff990ea0 0x0 0x20>;
 130                         reg-names = "local_request_region",
 131                                     "local_response_region",
 132                                     "remote_request_region",
 133                                     "remote_response_region";
 134                         #mbox-cells = <1>;
 135                         xlnx,ipi-id = <4>;
 136                 };
 137         };
 138
 139         dcc: dcc {
 140                 compatible = "arm,dcc";
 141                 status = "disabled";
 142                 bootph-all;
 143         };
 144
 145         pmu {
 146                 compatible = "arm,armv8-pmuv3";
 147                 interrupt-parent = <&gic>;
 148                 interrupts = <0 143 4>,
 149                              <0 144 4>,
 150                              <0 145 4>,
 151                              <0 146 4>;
 152                 interrupt-affinity = <&cpu0>,
 153                                      <&cpu1>,
 154                                      <&cpu2>,
 155                                      <&cpu3>;
 156         };
 157
 158         psci {
 159                 compatible = "arm,psci-0.2";
 160                 method = "smc";
 161         };
 162
 163         firmware {
 164                 optee: optee  {
 165                         compatible = "linaro,optee-tz";
 166                         method = "smc";
 167                 };
 168
 169                 zynqmp_firmware: zynqmp-firmware {
 170                         compatible = "xlnx,zynqmp-firmware";
 171                         #power-domain-cells = <1>;
 172                         method = "smc";
 173                         bootph-all;
 174
 175                         zynqmp_power: zynqmp-power {
 176                                 bootph-all;
 177                                 compatible = "xlnx,zynqmp-power";
 178                                 interrupt-parent = <&gic>;
 179                                 interrupts = <0 35 4>;
 180                                 mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>;
 181                                 mbox-names = "tx", "rx";
 182                         };
 183
 184                         nvmem_firmware {
 185                                 compatible = "xlnx,zynqmp-nvmem-fw";
 186                                 #address-cells = <1>;
 187                                 #size-cells = <1>;
 188
 189                                 soc_revision: soc_revision@0 {
 190                                         reg = <0x0 0x4>;
 191                                 };
 192                         };
 193
 194                         zynqmp_pcap: pcap {
 195                                 compatible = "xlnx,zynqmp-pcap-fpga";
 196                         };
 197
 198                         xlnx_aes: zynqmp-aes {
 199                                 compatible = "xlnx,zynqmp-aes";
 200                         };
 201
 202                         zynqmp_reset: reset-controller {
 203                                 compatible = "xlnx,zynqmp-reset";
 204                                 #reset-cells = <1>;
 205                         };
 206
 207                         pinctrl0: pinctrl {
 208                                 compatible = "xlnx,zynqmp-pinctrl";
 209                                 status = "disabled";
 210                         };
 211
 212                         modepin_gpio: gpio {
 213                                 compatible = "xlnx,zynqmp-gpio-modepin";
 214                                 gpio-controller;
 215                                 #gpio-cells = <2>;
 216                         };
 217                 };
 218         };
 219
 220         timer {
 221                 compatible = "arm,armv8-timer";
 222                 interrupt-parent = <&gic>;
 223                 interrupts = <1 13 0xf08>,
 224                              <1 14 0xf08>,
 225                              <1 11 0xf08>,
 226                              <1 10 0xf08>;
 227         };
 228
 229         edac {
 230                 compatible = "arm,cortex-a53-edac";
 231         };
 232
 233         fpga_full: fpga-full {
 234                 compatible = "fpga-region";
 235                 fpga-mgr = <&zynqmp_pcap>;
 236                 #address-cells = <2>;
 237                 #size-cells = <2>;
 238                 ranges;
 239                 power-domains = <&zynqmp_firmware PD_PL>;
 240         };
 241
 242         amba: axi {
 243                 compatible = "simple-bus";
 244                 bootph-all;
 245                 #address-cells = <2>;
 246                 #size-cells = <2>;
 247                 ranges;
 248
 249                 can0: can@ff060000 {
 250                         compatible = "xlnx,zynq-can-1.0";
 251                         status = "disabled";
 252                         clock-names = "can_clk", "pclk";
 253                         reg = <0x0 0xff060000 0x0 0x1000>;
 254                         interrupts = <0 23 4>;
 255                         interrupt-parent = <&gic>;
 256                         tx-fifo-depth = <0x40>;
 257                         rx-fifo-depth = <0x40>;
 258                         power-domains = <&zynqmp_firmware PD_CAN_0>;
 259                 };
 260
 261                 can1: can@ff070000 {
 262                         compatible = "xlnx,zynq-can-1.0";
 263                         status = "disabled";
 264                         clock-names = "can_clk", "pclk";
 265                         reg = <0x0 0xff070000 0x0 0x1000>;
 266                         interrupts = <0 24 4>;
 267                         interrupt-parent = <&gic>;
 268                         tx-fifo-depth = <0x40>;
 269                         rx-fifo-depth = <0x40>;
 270                         power-domains = <&zynqmp_firmware PD_CAN_1>;
 271                 };
 272
 273                 cci: cci@fd6e0000 {
 274                         compatible = "arm,cci-400";
 275                         status = "disabled";
 276                         reg = <0x0 0xfd6e0000 0x0 0x9000>;
 277                         ranges = <0x0 0x0 0xfd6e0000 0x10000>;
 278                         #address-cells = <1>;
 279                         #size-cells = <1>;
 280
 281                         pmu@9000 {
 282                                 compatible = "arm,cci-400-pmu,r1";
 283                                 reg = <0x9000 0x5000>;
 284                                 interrupt-parent = <&gic>;
 285                                 interrupts = <0 123 4>,
 286                                              <0 123 4>,
 287                                              <0 123 4>,
 288                                              <0 123 4>,
 289                                              <0 123 4>;
 290                         };
 291                 };
 292
 293                 /* GDMA */
 294                 fpd_dma_chan1: dma-controller@fd500000 {
 295                         status = "disabled";
 296                         compatible = "xlnx,zynqmp-dma-1.0";
 297                         reg = <0x0 0xfd500000 0x0 0x1000>;
 298                         interrupt-parent = <&gic>;
 299                         interrupts = <0 124 4>;
 300                         clock-names = "clk_main", "clk_apb";
 301                         #dma-cells = <1>;
 302                         xlnx,bus-width = <128>;
 303                         iommus = <&smmu 0x14e8>;
 304                         power-domains = <&zynqmp_firmware PD_GDMA>;
 305                 };
 306
 307                 fpd_dma_chan2: dma-controller@fd510000 {
 308                         status = "disabled";
 309                         compatible = "xlnx,zynqmp-dma-1.0";
 310                         reg = <0x0 0xfd510000 0x0 0x1000>;
 311                         interrupt-parent = <&gic>;
 312                         interrupts = <0 125 4>;
 313                         clock-names = "clk_main", "clk_apb";
 314                         #dma-cells = <1>;
 315                         xlnx,bus-width = <128>;
 316                         iommus = <&smmu 0x14e9>;
 317                         power-domains = <&zynqmp_firmware PD_GDMA>;
 318                 };
 319
 320                 fpd_dma_chan3: dma-controller@fd520000 {
 321                         status = "disabled";
 322                         compatible = "xlnx,zynqmp-dma-1.0";
 323                         reg = <0x0 0xfd520000 0x0 0x1000>;
 324                         interrupt-parent = <&gic>;
 325                         interrupts = <0 126 4>;
 326                         clock-names = "clk_main", "clk_apb";
 327                         #dma-cells = <1>;
 328                         xlnx,bus-width = <128>;
 329                         iommus = <&smmu 0x14ea>;
 330                         power-domains = <&zynqmp_firmware PD_GDMA>;
 331                 };
 332
 333                 fpd_dma_chan4: dma-controller@fd530000 {
 334                         status = "disabled";
 335                         compatible = "xlnx,zynqmp-dma-1.0";
 336                         reg = <0x0 0xfd530000 0x0 0x1000>;
 337                         interrupt-parent = <&gic>;
 338                         interrupts = <0 127 4>;
 339                         clock-names = "clk_main", "clk_apb";
 340                         #dma-cells = <1>;
 341                         xlnx,bus-width = <128>;
 342                         iommus = <&smmu 0x14eb>;
 343                         power-domains = <&zynqmp_firmware PD_GDMA>;
 344                 };
 345
 346                 fpd_dma_chan5: dma-controller@fd540000 {
 347                         status = "disabled";
 348                         compatible = "xlnx,zynqmp-dma-1.0";
 349                         reg = <0x0 0xfd540000 0x0 0x1000>;
 350                         interrupt-parent = <&gic>;
 351                         interrupts = <0 128 4>;
 352                         clock-names = "clk_main", "clk_apb";
 353                         #dma-cells = <1>;
 354                         xlnx,bus-width = <128>;
 355                         iommus = <&smmu 0x14ec>;
 356                         power-domains = <&zynqmp_firmware PD_GDMA>;
 357                 };
 358
 359                 fpd_dma_chan6: dma-controller@fd550000 {
 360                         status = "disabled";
 361                         compatible = "xlnx,zynqmp-dma-1.0";
 362                         reg = <0x0 0xfd550000 0x0 0x1000>;
 363                         interrupt-parent = <&gic>;
 364                         interrupts = <0 129 4>;
 365                         clock-names = "clk_main", "clk_apb";
 366                         #dma-cells = <1>;
 367                         xlnx,bus-width = <128>;
 368                         iommus = <&smmu 0x14ed>;
 369                         power-domains = <&zynqmp_firmware PD_GDMA>;
 370                 };
 371
 372                 fpd_dma_chan7: dma-controller@fd560000 {
 373                         status = "disabled";
 374                         compatible = "xlnx,zynqmp-dma-1.0";
 375                         reg = <0x0 0xfd560000 0x0 0x1000>;
 376                         interrupt-parent = <&gic>;
 377                         interrupts = <0 130 4>;
 378                         clock-names = "clk_main", "clk_apb";
 379                         #dma-cells = <1>;
 380                         xlnx,bus-width = <128>;
 381                         iommus = <&smmu 0x14ee>;
 382                         power-domains = <&zynqmp_firmware PD_GDMA>;
 383                 };
 384
 385                 fpd_dma_chan8: dma-controller@fd570000 {
 386                         status = "disabled";
 387                         compatible = "xlnx,zynqmp-dma-1.0";
 388                         reg = <0x0 0xfd570000 0x0 0x1000>;
 389                         interrupt-parent = <&gic>;
 390                         interrupts = <0 131 4>;
 391                         clock-names = "clk_main", "clk_apb";
 392                         #dma-cells = <1>;
 393                         xlnx,bus-width = <128>;
 394                         iommus = <&smmu 0x14ef>;
 395                         power-domains = <&zynqmp_firmware PD_GDMA>;
 396                 };
 397
 398                 gic: interrupt-controller@f9010000 {
 399                         compatible = "arm,gic-400";
 400                         #interrupt-cells = <3>;
 401                         reg = <0x0 0xf9010000 0x0 0x10000>,
 402                               <0x0 0xf9020000 0x0 0x20000>,
 403                               <0x0 0xf9040000 0x0 0x20000>,
 404                               <0x0 0xf9060000 0x0 0x20000>;
 405                         interrupt-controller;
 406                         interrupt-parent = <&gic>;
 407                         interrupts = <1 9 0xf04>;
 408                 };
 409
 410                 gpu: gpu@fd4b0000 {
 411                         status = "disabled";
 412                         compatible = "xlnx,zynqmp-mali", "arm,mali-400";
 413                         reg = <0x0 0xfd4b0000 0x0 0x10000>;
 414                         interrupt-parent = <&gic>;
 415                         interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>;
 416                         interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1", "ppmmu1";
 417                         clock-names = "bus", "core";
 418                         power-domains = <&zynqmp_firmware PD_GPU>;
 419                 };
 420
 421                 /* LPDDMA default allows only secured access. inorder to enable
 422                  * These dma channels, Users should ensure that these dma
 423                  * Channels are allowed for non secure access.
 424                  */
 425                 lpd_dma_chan1: dma-controller@ffa80000 {
 426                         status = "disabled";
 427                         compatible = "xlnx,zynqmp-dma-1.0";
 428                         reg = <0x0 0xffa80000 0x0 0x1000>;
 429                         interrupt-parent = <&gic>;
 430                         interrupts = <0 77 4>;
 431                         clock-names = "clk_main", "clk_apb";
 432                         #dma-cells = <1>;
 433                         xlnx,bus-width = <64>;
 434                         iommus = <&smmu 0x868>;
 435                         power-domains = <&zynqmp_firmware PD_ADMA>;
 436                 };
 437
 438                 lpd_dma_chan2: dma-controller@ffa90000 {
 439                         status = "disabled";
 440                         compatible = "xlnx,zynqmp-dma-1.0";
 441                         reg = <0x0 0xffa90000 0x0 0x1000>;
 442                         interrupt-parent = <&gic>;
 443                         interrupts = <0 78 4>;
 444                         clock-names = "clk_main", "clk_apb";
 445                         #dma-cells = <1>;
 446                         xlnx,bus-width = <64>;
 447                         iommus = <&smmu 0x869>;
 448                         power-domains = <&zynqmp_firmware PD_ADMA>;
 449                 };
 450
 451                 lpd_dma_chan3: dma-controller@ffaa0000 {
 452                         status = "disabled";
 453                         compatible = "xlnx,zynqmp-dma-1.0";
 454                         reg = <0x0 0xffaa0000 0x0 0x1000>;
 455                         interrupt-parent = <&gic>;
 456                         interrupts = <0 79 4>;
 457                         clock-names = "clk_main", "clk_apb";
 458                         #dma-cells = <1>;
 459                         xlnx,bus-width = <64>;
 460                         iommus = <&smmu 0x86a>;
 461                         power-domains = <&zynqmp_firmware PD_ADMA>;
 462                 };
 463
 464                 lpd_dma_chan4: dma-controller@ffab0000 {
 465                         status = "disabled";
 466                         compatible = "xlnx,zynqmp-dma-1.0";
 467                         reg = <0x0 0xffab0000 0x0 0x1000>;
 468                         interrupt-parent = <&gic>;
 469                         interrupts = <0 80 4>;
 470                         clock-names = "clk_main", "clk_apb";
 471                         #dma-cells = <1>;
 472                         xlnx,bus-width = <64>;
 473                         iommus = <&smmu 0x86b>;
 474                         power-domains = <&zynqmp_firmware PD_ADMA>;
 475                 };
 476
 477                 lpd_dma_chan5: dma-controller@ffac0000 {
 478                         status = "disabled";
 479                         compatible = "xlnx,zynqmp-dma-1.0";
 480                         reg = <0x0 0xffac0000 0x0 0x1000>;
 481                         interrupt-parent = <&gic>;
 482                         interrupts = <0 81 4>;
 483                         clock-names = "clk_main", "clk_apb";
 484                         #dma-cells = <1>;
 485                         xlnx,bus-width = <64>;
 486                         iommus = <&smmu 0x86c>;
 487                         power-domains = <&zynqmp_firmware PD_ADMA>;
 488                 };
 489
 490                 lpd_dma_chan6: dma-controller@ffad0000 {
 491                         status = "disabled";
 492                         compatible = "xlnx,zynqmp-dma-1.0";
 493                         reg = <0x0 0xffad0000 0x0 0x1000>;
 494                         interrupt-parent = <&gic>;
 495                         interrupts = <0 82 4>;
 496                         clock-names = "clk_main", "clk_apb";
 497                         #dma-cells = <1>;
 498                         xlnx,bus-width = <64>;
 499                         iommus = <&smmu 0x86d>;
 500                         power-domains = <&zynqmp_firmware PD_ADMA>;
 501                 };
 502
 503                 lpd_dma_chan7: dma-controller@ffae0000 {
 504                         status = "disabled";
 505                         compatible = "xlnx,zynqmp-dma-1.0";
 506                         reg = <0x0 0xffae0000 0x0 0x1000>;
 507                         interrupt-parent = <&gic>;
 508                         interrupts = <0 83 4>;
 509                         clock-names = "clk_main", "clk_apb";
 510                         #dma-cells = <1>;
 511                         xlnx,bus-width = <64>;
 512                         iommus = <&smmu 0x86e>;
 513                         power-domains = <&zynqmp_firmware PD_ADMA>;
 514                 };
 515
 516                 lpd_dma_chan8: dma-controller@ffaf0000 {
 517                         status = "disabled";
 518                         compatible = "xlnx,zynqmp-dma-1.0";
 519                         reg = <0x0 0xffaf0000 0x0 0x1000>;
 520                         interrupt-parent = <&gic>;
 521                         interrupts = <0 84 4>;
 522                         clock-names = "clk_main", "clk_apb";
 523                         #dma-cells = <1>;
 524                         xlnx,bus-width = <64>;
 525                         iommus = <&smmu 0x86f>;
 526                         power-domains = <&zynqmp_firmware PD_ADMA>;
 527                 };
 528
 529                 mc: memory-controller@fd070000 {
 530                         compatible = "xlnx,zynqmp-ddrc-2.40a";
 531                         reg = <0x0 0xfd070000 0x0 0x30000>;
 532                         interrupt-parent = <&gic>;
 533                         interrupts = <0 112 4>;
 534                 };
 535
 536                 nand0: nand-controller@ff100000 {
 537                         compatible = "xlnx,zynqmp-nand-controller", "arasan,nfc-v3p10";
 538                         status = "disabled";
 539                         reg = <0x0 0xff100000 0x0 0x1000>;
 540                         clock-names = "controller", "bus";
 541                         interrupt-parent = <&gic>;
 542                         interrupts = <0 14 4>;
 543                         #address-cells = <1>;
 544                         #size-cells = <0>;
 545                         iommus = <&smmu 0x872>;
 546                         power-domains = <&zynqmp_firmware PD_NAND>;
 547                 };
 548
 549                 gem0: ethernet@ff0b0000 {
 550                         compatible = "xlnx,zynqmp-gem", "cdns,gem";
 551                         status = "disabled";
 552                         interrupt-parent = <&gic>;
 553                         interrupts = <0 57 4>, <0 57 4>;
 554                         reg = <0x0 0xff0b0000 0x0 0x1000>;
 555                         clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
 556                         #address-cells = <1>;
 557                         #size-cells = <0>;
 558                         iommus = <&smmu 0x874>;
 559                         power-domains = <&zynqmp_firmware PD_ETH_0>;
 560                         resets = <&zynqmp_reset ZYNQMP_RESET_GEM0>;
 561                         reset-names = "gem0_rst";
 562                 };
 563
 564                 gem1: ethernet@ff0c0000 {
 565                         compatible = "xlnx,zynqmp-gem", "cdns,gem";
 566                         status = "disabled";
 567                         interrupt-parent = <&gic>;
 568                         interrupts = <0 59 4>, <0 59 4>;
 569                         reg = <0x0 0xff0c0000 0x0 0x1000>;
 570                         clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
 571                         #address-cells = <1>;
 572                         #size-cells = <0>;
 573                         iommus = <&smmu 0x875>;
 574                         power-domains = <&zynqmp_firmware PD_ETH_1>;
 575                         resets = <&zynqmp_reset ZYNQMP_RESET_GEM1>;
 576                         reset-names = "gem1_rst";
 577                 };
 578
 579                 gem2: ethernet@ff0d0000 {
 580                         compatible = "xlnx,zynqmp-gem", "cdns,gem";
 581                         status = "disabled";
 582                         interrupt-parent = <&gic>;
 583                         interrupts = <0 61 4>, <0 61 4>;
 584                         reg = <0x0 0xff0d0000 0x0 0x1000>;
 585                         clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
 586                         #address-cells = <1>;
 587                         #size-cells = <0>;
 588                         iommus = <&smmu 0x876>;
 589                         power-domains = <&zynqmp_firmware PD_ETH_2>;
 590                         resets = <&zynqmp_reset ZYNQMP_RESET_GEM2>;
 591                         reset-names = "gem2_rst";
 592                 };
 593
 594                 gem3: ethernet@ff0e0000 {
 595                         compatible = "xlnx,zynqmp-gem", "cdns,gem";
 596                         status = "disabled";
 597                         interrupt-parent = <&gic>;
 598                         interrupts = <0 63 4>, <0 63 4>;
 599                         reg = <0x0 0xff0e0000 0x0 0x1000>;
 600                         clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
 601                         #address-cells = <1>;
 602                         #size-cells = <0>;
 603                         iommus = <&smmu 0x877>;
 604                         power-domains = <&zynqmp_firmware PD_ETH_3>;
 605                         resets = <&zynqmp_reset ZYNQMP_RESET_GEM3>;
 606                         reset-names = "gem3_rst";
 607                 };
 608
 609                 gpio: gpio@ff0a0000 {
 610                         compatible = "xlnx,zynqmp-gpio-1.0";
 611                         status = "disabled";
 612                         #gpio-cells = <0x2>;
 613                         gpio-controller;
 614                         interrupt-parent = <&gic>;
 615                         interrupts = <0 16 4>;
 616                         interrupt-controller;
 617                         #interrupt-cells = <2>;
 618                         reg = <0x0 0xff0a0000 0x0 0x1000>;
 619                         power-domains = <&zynqmp_firmware PD_GPIO>;
 620                 };
 621
 622                 i2c0: i2c@ff020000 {
 623                         compatible = "cdns,i2c-r1p14";
 624                         status = "disabled";
 625                         interrupt-parent = <&gic>;
 626                         interrupts = <0 17 4>;
 627                         clock-frequency = <400000>;
 628                         reg = <0x0 0xff020000 0x0 0x1000>;
 629                         #address-cells = <1>;
 630                         #size-cells = <0>;
 631                         power-domains = <&zynqmp_firmware PD_I2C_0>;
 632                 };
 633
 634                 i2c1: i2c@ff030000 {
 635                         compatible = "cdns,i2c-r1p14";
 636                         status = "disabled";
 637                         interrupt-parent = <&gic>;
 638                         interrupts = <0 18 4>;
 639                         clock-frequency = <400000>;
 640                         reg = <0x0 0xff030000 0x0 0x1000>;
 641                         #address-cells = <1>;
 642                         #size-cells = <0>;
 643                         power-domains = <&zynqmp_firmware PD_I2C_1>;
 644                 };
 645
 646                 ocm: memory-controller@ff960000 {
 647                         compatible = "xlnx,zynqmp-ocmc-1.0";
 648                         reg = <0x0 0xff960000 0x0 0x1000>;
 649                         interrupt-parent = <&gic>;
 650                         interrupts = <0 10 4>;
 651                 };
 652
 653                 pcie: pcie@fd0e0000 {
 654                         compatible = "xlnx,nwl-pcie-2.11";
 655                         status = "disabled";
 656                         #address-cells = <3>;
 657                         #size-cells = <2>;
 658                         #interrupt-cells = <1>;
 659                         msi-controller;
 660                         device_type = "pci";
 661                         interrupt-parent = <&gic>;
 662                         interrupts = <0 118 4>,
 663                                      <0 117 4>,
 664                                      <0 116 4>,
 665                                      <0 115 4>, /* MSI_1 [63...32] */
 666                                      <0 114 4>; /* MSI_0 [31...0] */
 667                         interrupt-names = "misc", "dummy", "intx",
 668                                           "msi1", "msi0";
 669                         msi-parent = <&pcie>;
 670                         reg = <0x0 0xfd0e0000 0x0 0x1000>,
 671                               <0x0 0xfd480000 0x0 0x1000>,
 672                               <0x80 0x00000000 0x0 0x1000000>;
 673                         reg-names = "breg", "pcireg", "cfg";
 674                         ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000>,/* non-prefetchable memory */
 675                                  <0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */
 676                         bus-range = <0x00 0xff>;
 677                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 678                         interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
 679                                         <0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
 680                                         <0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
 681                                         <0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
 682                         iommus = <&smmu 0x4d0>;
 683                         power-domains = <&zynqmp_firmware PD_PCIE>;
 684                         pcie_intc: legacy-interrupt-controller {
 685                                 interrupt-controller;
 686                                 #address-cells = <0>;
 687                                 #interrupt-cells = <1>;
 688                         };
 689                 };
 690
 691                 qspi: spi@ff0f0000 {
 692                         bootph-all;
 693                         compatible = "xlnx,zynqmp-qspi-1.0";
 694                         status = "disabled";
 695                         clock-names = "ref_clk", "pclk";
 696                         interrupts = <0 15 4>;
 697                         interrupt-parent = <&gic>;
 698                         num-cs = <1>;
 699                         reg = <0x0 0xff0f0000 0x0 0x1000>,
 700                               <0x0 0xc0000000 0x0 0x8000000>;
 701                         #address-cells = <1>;
 702                         #size-cells = <0>;
 703                         iommus = <&smmu 0x873>;
 704                         power-domains = <&zynqmp_firmware PD_QSPI>;
 705                 };
 706
 707                 psgtr: phy@fd400000 {
 708                         compatible = "xlnx,zynqmp-psgtr-v1.1";
 709                         status = "disabled";
 710                         reg = <0x0 0xfd400000 0x0 0x40000>,
 711                               <0x0 0xfd3d0000 0x0 0x1000>;
 712                         reg-names = "serdes", "siou";
 713                         #phy-cells = <4>;
 714                 };
 715
 716                 rtc: rtc@ffa60000 {
 717                         compatible = "xlnx,zynqmp-rtc";
 718                         status = "disabled";
 719                         reg = <0x0 0xffa60000 0x0 0x100>;
 720                         interrupt-parent = <&gic>;
 721                         interrupts = <0 26 4>, <0 27 4>;
 722                         interrupt-names = "alarm", "sec";
 723                         calibration = <0x7FFF>;
 724                 };
 725
 726                 sata: ahci@fd0c0000 {
 727                         compatible = "ceva,ahci-1v84";
 728                         status = "disabled";
 729                         reg = <0x0 0xfd0c0000 0x0 0x2000>;
 730                         interrupt-parent = <&gic>;
 731                         interrupts = <0 133 4>;
 732                         power-domains = <&zynqmp_firmware PD_SATA>;
 733                         resets = <&zynqmp_reset ZYNQMP_RESET_SATA>;
 734                         iommus = <&smmu 0x4c0>, <&smmu 0x4c1>,
 735                                  <&smmu 0x4c2>, <&smmu 0x4c3>;
 736                         /* dma-coherent; */
 737                 };
 738
 739                 sdhci0: mmc@ff160000 {
 740                         bootph-all;
 741                         compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
 742                         status = "disabled";
 743                         interrupt-parent = <&gic>;
 744                         interrupts = <0 48 4>;
 745                         reg = <0x0 0xff160000 0x0 0x1000>;
 746                         clock-names = "clk_xin", "clk_ahb";
 747                         iommus = <&smmu 0x870>;
 748                         #clock-cells = <1>;
 749                         clock-output-names = "clk_out_sd0", "clk_in_sd0";
 750                         power-domains = <&zynqmp_firmware PD_SD_0>;
 751                         resets = <&zynqmp_reset ZYNQMP_RESET_SDIO0>;
 752                 };
 753
 754                 sdhci1: mmc@ff170000 {
 755                         bootph-all;
 756                         compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
 757                         status = "disabled";
 758                         interrupt-parent = <&gic>;
 759                         interrupts = <0 49 4>;
 760                         reg = <0x0 0xff170000 0x0 0x1000>;
 761                         clock-names = "clk_xin", "clk_ahb";
 762                         iommus = <&smmu 0x871>;
 763                         #clock-cells = <1>;
 764                         clock-output-names = "clk_out_sd1", "clk_in_sd1";
 765                         power-domains = <&zynqmp_firmware PD_SD_1>;
 766                         resets = <&zynqmp_reset ZYNQMP_RESET_SDIO1>;
 767                 };
 768
 769                 smmu: iommu@fd800000 {
 770                         compatible = "arm,mmu-500";
 771                         reg = <0x0 0xfd800000 0x0 0x20000>;
 772                         #iommu-cells = <1>;
 773                         status = "disabled";
 774                         #global-interrupts = <1>;
 775                         interrupt-parent = <&gic>;
 776                         interrupts = <0 155 4>,
 777                                 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
 778                                 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
 779                                 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
 780                                 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;
 781                 };
 782
 783                 spi0: spi@ff040000 {
 784                         compatible = "cdns,spi-r1p6";
 785                         status = "disabled";
 786                         interrupt-parent = <&gic>;
 787                         interrupts = <0 19 4>;
 788                         reg = <0x0 0xff040000 0x0 0x1000>;
 789                         clock-names = "ref_clk", "pclk";
 790                         #address-cells = <1>;
 791                         #size-cells = <0>;
 792                         power-domains = <&zynqmp_firmware PD_SPI_0>;
 793                 };
 794
 795                 spi1: spi@ff050000 {
 796                         compatible = "cdns,spi-r1p6";
 797                         status = "disabled";
 798                         interrupt-parent = <&gic>;
 799                         interrupts = <0 20 4>;
 800                         reg = <0x0 0xff050000 0x0 0x1000>;
 801                         clock-names = "ref_clk", "pclk";
 802                         #address-cells = <1>;
 803                         #size-cells = <0>;
 804                         power-domains = <&zynqmp_firmware PD_SPI_1>;
 805                 };
 806
 807                 ttc0: timer@ff110000 {
 808                         compatible = "cdns,ttc";
 809                         status = "disabled";
 810                         interrupt-parent = <&gic>;
 811                         interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
 812                         reg = <0x0 0xff110000 0x0 0x1000>;
 813                         timer-width = <32>;
 814                         power-domains = <&zynqmp_firmware PD_TTC_0>;
 815                 };
 816
 817                 ttc1: timer@ff120000 {
 818                         compatible = "cdns,ttc";
 819                         status = "disabled";
 820                         interrupt-parent = <&gic>;
 821                         interrupts = <0 39 4>, <0 40 4>, <0 41 4>;
 822                         reg = <0x0 0xff120000 0x0 0x1000>;
 823                         timer-width = <32>;
 824                         power-domains = <&zynqmp_firmware PD_TTC_1>;
 825                 };
 826
 827                 ttc2: timer@ff130000 {
 828                         compatible = "cdns,ttc";
 829                         status = "disabled";
 830                         interrupt-parent = <&gic>;
 831                         interrupts = <0 42 4>, <0 43 4>, <0 44 4>;
 832                         reg = <0x0 0xff130000 0x0 0x1000>;
 833                         timer-width = <32>;
 834                         power-domains = <&zynqmp_firmware PD_TTC_2>;
 835                 };
 836
 837                 ttc3: timer@ff140000 {
 838                         compatible = "cdns,ttc";
 839                         status = "disabled";
 840                         interrupt-parent = <&gic>;
 841                         interrupts = <0 45 4>, <0 46 4>, <0 47 4>;
 842                         reg = <0x0 0xff140000 0x0 0x1000>;
 843                         timer-width = <32>;
 844                         power-domains = <&zynqmp_firmware PD_TTC_3>;
 845                 };
 846
 847                 uart0: serial@ff000000 {
 848                         bootph-all;
 849                         compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
 850                         status = "disabled";
 851                         interrupt-parent = <&gic>;
 852                         interrupts = <0 21 4>;
 853                         reg = <0x0 0xff000000 0x0 0x1000>;
 854                         clock-names = "uart_clk", "pclk";
 855                         power-domains = <&zynqmp_firmware PD_UART_0>;
 856                 };
 857
 858                 uart1: serial@ff010000 {
 859                         bootph-all;
 860                         compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
 861                         status = "disabled";
 862                         interrupt-parent = <&gic>;
 863                         interrupts = <0 22 4>;
 864                         reg = <0x0 0xff010000 0x0 0x1000>;
 865                         clock-names = "uart_clk", "pclk";
 866                         power-domains = <&zynqmp_firmware PD_UART_1>;
 867                 };
 868
 869                 usb0: usb@ff9d0000 {
 870                         #address-cells = <2>;
 871                         #size-cells = <2>;
 872                         status = "disabled";
 873                         compatible = "xlnx,zynqmp-dwc3";
 874                         reg = <0x0 0xff9d0000 0x0 0x100>;
 875                         clock-names = "bus_clk", "ref_clk";
 876                         power-domains = <&zynqmp_firmware PD_USB_0>;
 877                         resets = <&zynqmp_reset ZYNQMP_RESET_USB0_CORERESET>,
 878                                  <&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>,
 879                                  <&zynqmp_reset ZYNQMP_RESET_USB0_APB>;
 880                         reset-names = "usb_crst", "usb_hibrst", "usb_apbrst";
 881                         reset-gpios = <&modepin_gpio 1 GPIO_ACTIVE_LOW>;
 882                         ranges;
 883
 884                         dwc3_0: usb@fe200000 {
 885                                 compatible = "snps,dwc3";
 886                                 status = "disabled";
 887                                 reg = <0x0 0xfe200000 0x0 0x40000>;
 888                                 interrupt-parent = <&gic>;
 889                                 interrupt-names = "dwc_usb3", "otg", "hiber";
 890                                 interrupts = <0 65 4>, <0 69 4>, <0 75 4>;
 891                                 iommus = <&smmu 0x860>;
 892                                 snps,quirk-frame-length-adjustment = <0x20>;
 893                                 clock-names = "ref";
 894                                 snps,enable_guctl1_ipd_quirk;
 895                                 snps,xhci-stream-quirk;
 896                                 snps,resume-hs-terminations;
 897                                 /* dma-coherent; */
 898                         };
 899                 };
 900
 901                 usb1: usb@ff9e0000 {
 902                         #address-cells = <2>;
 903                         #size-cells = <2>;
 904                         status = "disabled";
 905                         compatible = "xlnx,zynqmp-dwc3";
 906                         reg = <0x0 0xff9e0000 0x0 0x100>;
 907                         clock-names = "bus_clk", "ref_clk";
 908                         power-domains = <&zynqmp_firmware PD_USB_1>;
 909                         resets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>,
 910                                  <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>,
 911                                  <&zynqmp_reset ZYNQMP_RESET_USB1_APB>;
 912                         reset-names = "usb_crst", "usb_hibrst", "usb_apbrst";
 913                         ranges;
 914
 915                         dwc3_1: usb@fe300000 {
 916                                 compatible = "snps,dwc3";
 917                                 status = "disabled";
 918                                 reg = <0x0 0xfe300000 0x0 0x40000>;
 919                                 interrupt-parent = <&gic>;
 920                                 interrupt-names = "dwc_usb3", "otg", "hiber";
 921                                 interrupts = <0 70 4>, <0 74 4>, <0 76 4>;
 922                                 iommus = <&smmu 0x861>;
 923                                 snps,quirk-frame-length-adjustment = <0x20>;
 924                                 clock-names = "ref";
 925                                 snps,enable_guctl1_ipd_quirk;
 926                                 snps,xhci-stream-quirk;
 927                                 snps,resume-hs-terminations;
 928                                 /* dma-coherent; */
 929                         };
 930                 };
 931
 932                 watchdog0: watchdog@fd4d0000 {
 933                         compatible = "cdns,wdt-r1p2";
 934                         status = "disabled";
 935                         interrupt-parent = <&gic>;
 936                         interrupts = <0 113 1>;
 937                         reg = <0x0 0xfd4d0000 0x0 0x1000>;
 938                         timeout-sec = <60>;
 939                         reset-on-timeout;
 940                 };
 941
 942                 lpd_watchdog: watchdog@ff150000 {
 943                         compatible = "cdns,wdt-r1p2";
 944                         status = "disabled";
 945                         interrupt-parent = <&gic>;
 946                         interrupts = <0 52 1>;
 947                         reg = <0x0 0xff150000 0x0 0x1000>;
 948                         timeout-sec = <10>;
 949                 };
 950
 951                 xilinx_ams: ams@ffa50000 {
 952                         compatible = "xlnx,zynqmp-ams";
 953                         status = "disabled";
 954                         interrupt-parent = <&gic>;
 955                         interrupts = <0 56 4>;
 956                         reg = <0x0 0xffa50000 0x0 0x800>;
 957                         #address-cells = <1>;
 958                         #size-cells = <1>;
 959                         #io-channel-cells = <1>;
 960                         ranges = <0 0 0xffa50800 0x800>;
 961
 962                         ams_ps: ams-ps@0 {
 963                                 compatible = "xlnx,zynqmp-ams-ps";
 964                                 status = "disabled";
 965                                 reg = <0x0 0x400>;
 966                         };
 967
 968                         ams_pl: ams-pl@400 {
 969                                 compatible = "xlnx,zynqmp-ams-pl";
 970                                 status = "disabled";
 971                                 reg = <0x400 0x400>;
 972                                 #address-cells = <1>;
 973                                 #size-cells = <0>;
 974                         };
 975                 };
 976
 977                 zynqmp_dpdma: dma-controller@fd4c0000 {
 978                         compatible = "xlnx,zynqmp-dpdma";
 979                         status = "disabled";
 980                         reg = <0x0 0xfd4c0000 0x0 0x1000>;
 981                         interrupts = <0 122 4>;
 982                         interrupt-parent = <&gic>;
 983                         clock-names = "axi_clk";
 984                         power-domains = <&zynqmp_firmware PD_DP>;
 985                         #dma-cells = <1>;
 986                 };
 987
 988                 zynqmp_dpsub: display@fd4a0000 {
 989                         bootph-all;
 990                         compatible = "xlnx,zynqmp-dpsub-1.7";
 991                         status = "disabled";
 992                         reg = <0x0 0xfd4a0000 0x0 0x1000>,
 993                               <0x0 0xfd4aa000 0x0 0x1000>,
 994                               <0x0 0xfd4ab000 0x0 0x1000>,
 995                               <0x0 0xfd4ac000 0x0 0x1000>;
 996                         reg-names = "dp", "blend", "av_buf", "aud";
 997                         interrupts = <0 119 4>;
 998                         interrupt-parent = <&gic>;
 999                         clock-names = "dp_apb_clk", "dp_aud_clk",
1000                                       "dp_vtc_pixel_clk_in";
1001                         power-domains = <&zynqmp_firmware PD_DP>;
1002                         resets = <&zynqmp_reset ZYNQMP_RESET_DP>;
1003                         dma-names = "vid0", "vid1", "vid2", "gfx0";
1004                         dmas = <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO0>,
1005                                <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO1>,
1006                                <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO2>,
1007                                <&zynqmp_dpdma ZYNQMP_DPDMA_GRAPHICS>;
1008                 };
1009         };
1010 };