2 * dts file for Xilinx ZynqMP
4 * (C) Copyright 2014 - 2015, Xilinx, Inc.
6 * Michal Simek <michal.simek@xilinx.com>
8 * SPDX-License-Identifier: GPL-2.0+
11 compatible = "xlnx,zynqmp";
20 compatible = "arm,cortex-a53", "arm,armv8";
22 enable-method = "psci";
27 compatible = "arm,cortex-a53", "arm,armv8";
29 enable-method = "psci";
34 compatible = "arm,cortex-a53", "arm,armv8";
36 enable-method = "psci";
41 compatible = "arm,cortex-a53", "arm,armv8";
43 enable-method = "psci";
49 compatible = "arm,dcc";
55 compatible = "xlnx,zynqmp-genpd";
58 #power-domain-cells = <0x0>;
63 #power-domain-cells = <0x0>;
68 #power-domain-cells = <0x0>;
73 #power-domain-cells = <0x0>;
78 #power-domain-cells = <0x0>;
83 #power-domain-cells = <0x0>;
88 #power-domain-cells = <0x0>;
93 #power-domain-cells = <0x0>;
98 #power-domain-cells = <0x0>;
103 #power-domain-cells = <0x0>;
108 #power-domain-cells = <0x0>;
113 #power-domain-cells = <0x0>;
118 #power-domain-cells = <0x0>;
123 /* fixme: what to attach to */
124 #power-domain-cells = <0x0>;
129 #power-domain-cells = <0x0>;
134 #power-domain-cells = <0x0>;
139 #power-domain-cells = <0x0>;
144 #power-domain-cells = <0x0>;
149 #power-domain-cells = <0x0>;
154 #power-domain-cells = <0x0>;
159 #power-domain-cells = <0x0>;
164 #power-domain-cells = <0x0>;
169 #power-domain-cells = <0x0>;
174 #power-domain-cells = <0x0>;
179 #power-domain-cells = <0x0>;
184 #power-domain-cells = <0x0>;
189 #power-domain-cells = <0x0>;
194 #power-domain-cells = <0x0>;
199 #power-domain-cells = <0x0>;
200 pd-id = <0x3a 0x14 0x15>;
205 compatible = "arm,armv8-pmuv3";
206 interrupt-parent = <&gic>;
207 interrupts = <0 143 4>,
214 compatible = "arm,psci-0.2";
219 compatible = "xlnx,zynqmp-pm";
224 compatible = "arm,armv8-timer";
225 interrupt-parent = <&gic>;
226 interrupts = <1 13 0xf01>,
233 compatible = "arm,cortex-a53-edac";
237 compatible = "xlnx,zynqmp-pcap-fpga";
240 amba_apu: amba_apu@0 {
241 compatible = "simple-bus";
242 #address-cells = <2>;
244 ranges = <0 0 0 0 0xffffffff>;
246 gic: interrupt-controller@f9010000 {
247 compatible = "arm,gic-400", "arm,cortex-a15-gic";
248 #interrupt-cells = <3>;
249 reg = <0x0 0xf9010000 0x10000>,
250 <0x0 0xf9020000 0x20000>,
251 <0x0 0xf9040000 0x20000>,
252 <0x0 0xf9060000 0x20000>;
253 interrupt-controller;
254 interrupt-parent = <&gic>;
255 interrupts = <1 9 0xf04>;
260 compatible = "simple-bus";
262 #address-cells = <2>;
264 ranges = <0 0 0 0 0xffffffff>;
267 compatible = "xlnx,zynq-can-1.0";
269 clock-names = "can_clk", "pclk";
270 reg = <0x0 0xff060000 0x1000>;
271 interrupts = <0 23 4>;
272 interrupt-parent = <&gic>;
273 tx-fifo-depth = <0x40>;
274 rx-fifo-depth = <0x40>;
275 power-domains = <&pd_can0>;
279 compatible = "xlnx,zynq-can-1.0";
281 clock-names = "can_clk", "pclk";
282 reg = <0x0 0xff070000 0x1000>;
283 interrupts = <0 24 4>;
284 interrupt-parent = <&gic>;
285 tx-fifo-depth = <0x40>;
286 rx-fifo-depth = <0x40>;
287 power-domains = <&pd_can1>;
291 compatible = "arm,cci-400";
292 reg = <0x0 0xfd6e0000 0x9000>;
293 ranges = <0x0 0x0 0xfd6e0000 0x10000>;
294 #address-cells = <1>;
298 compatible = "arm,cci-400-pmu,r1";
299 reg = <0x9000 0x5000>;
300 interrupt-parent = <&gic>;
301 interrupts = <0 123 4>,
310 fpd_dma_chan1: dma@fd500000 {
312 compatible = "xlnx,zynqmp-dma-1.0";
313 reg = <0x0 0xfd500000 0x1000>;
314 interrupt-parent = <&gic>;
315 interrupts = <0 124 4>;
316 clock-names = "clk_main", "clk_apb";
317 xlnx,bus-width = <128>;
318 #stream-id-cells = <1>;
319 iommus = <&smmu 0x14e8>;
320 power-domains = <&pd_gdma>;
323 fpd_dma_chan2: dma@fd510000 {
325 compatible = "xlnx,zynqmp-dma-1.0";
326 reg = <0x0 0xfd510000 0x1000>;
327 interrupt-parent = <&gic>;
328 interrupts = <0 125 4>;
329 clock-names = "clk_main", "clk_apb";
330 xlnx,bus-width = <128>;
331 #stream-id-cells = <1>;
332 iommus = <&smmu 0x14e9>;
333 power-domains = <&pd_gdma>;
336 fpd_dma_chan3: dma@fd520000 {
338 compatible = "xlnx,zynqmp-dma-1.0";
339 reg = <0x0 0xfd520000 0x1000>;
340 interrupt-parent = <&gic>;
341 interrupts = <0 126 4>;
342 clock-names = "clk_main", "clk_apb";
343 xlnx,bus-width = <128>;
344 #stream-id-cells = <1>;
345 iommus = <&smmu 0x14ea>;
346 power-domains = <&pd_gdma>;
349 fpd_dma_chan4: dma@fd530000 {
351 compatible = "xlnx,zynqmp-dma-1.0";
352 reg = <0x0 0xfd530000 0x1000>;
353 interrupt-parent = <&gic>;
354 interrupts = <0 127 4>;
355 clock-names = "clk_main", "clk_apb";
356 xlnx,bus-width = <128>;
357 #stream-id-cells = <1>;
358 iommus = <&smmu 0x14eb>;
359 power-domains = <&pd_gdma>;
362 fpd_dma_chan5: dma@fd540000 {
364 compatible = "xlnx,zynqmp-dma-1.0";
365 reg = <0x0 0xfd540000 0x1000>;
366 interrupt-parent = <&gic>;
367 interrupts = <0 128 4>;
368 clock-names = "clk_main", "clk_apb";
369 xlnx,bus-width = <128>;
370 #stream-id-cells = <1>;
371 iommus = <&smmu 0x14ec>;
372 power-domains = <&pd_gdma>;
375 fpd_dma_chan6: dma@fd550000 {
377 compatible = "xlnx,zynqmp-dma-1.0";
378 reg = <0x0 0xfd550000 0x1000>;
379 interrupt-parent = <&gic>;
380 interrupts = <0 129 4>;
381 clock-names = "clk_main", "clk_apb";
382 xlnx,bus-width = <128>;
383 #stream-id-cells = <1>;
384 iommus = <&smmu 0x14ed>;
385 power-domains = <&pd_gdma>;
388 fpd_dma_chan7: dma@fd560000 {
390 compatible = "xlnx,zynqmp-dma-1.0";
391 reg = <0x0 0xfd560000 0x1000>;
392 interrupt-parent = <&gic>;
393 interrupts = <0 130 4>;
394 clock-names = "clk_main", "clk_apb";
395 xlnx,bus-width = <128>;
396 #stream-id-cells = <1>;
397 iommus = <&smmu 0x14ee>;
398 power-domains = <&pd_gdma>;
401 fpd_dma_chan8: dma@fd570000 {
403 compatible = "xlnx,zynqmp-dma-1.0";
404 reg = <0x0 0xfd570000 0x1000>;
405 interrupt-parent = <&gic>;
406 interrupts = <0 131 4>;
407 clock-names = "clk_main", "clk_apb";
408 xlnx,bus-width = <128>;
409 #stream-id-cells = <1>;
410 iommus = <&smmu 0x14ef>;
411 power-domains = <&pd_gdma>;
416 compatible = "arm,mali-400", "arm,mali-utgard";
417 reg = <0x0 0xfd4b0000 0x30000>;
418 interrupt-parent = <&gic>;
419 interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>;
420 interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1";
421 power-domains = <&pd_gpu>;
425 lpd_dma_chan1: dma@ffa80000 {
427 compatible = "xlnx,zynqmp-dma-1.0";
428 reg = <0x0 0xffa80000 0x1000>;
429 interrupt-parent = <&gic>;
430 interrupts = <0 77 4>;
431 xlnx,bus-width = <64>;
432 #stream-id-cells = <1>;
433 iommus = <&smmu 0x868>;
434 power-domains = <&pd_adma>;
437 lpd_dma_chan2: dma@ffa90000 {
439 compatible = "xlnx,zynqmp-dma-1.0";
440 reg = <0x0 0xffa90000 0x1000>;
441 interrupt-parent = <&gic>;
442 interrupts = <0 78 4>;
443 xlnx,bus-width = <64>;
444 #stream-id-cells = <1>;
445 iommus = <&smmu 0x869>;
446 power-domains = <&pd_adma>;
449 lpd_dma_chan3: dma@ffaa0000 {
451 compatible = "xlnx,zynqmp-dma-1.0";
452 reg = <0x0 0xffaa0000 0x1000>;
453 interrupt-parent = <&gic>;
454 interrupts = <0 79 4>;
455 xlnx,bus-width = <64>;
456 #stream-id-cells = <1>;
457 iommus = <&smmu 0x86a>;
458 power-domains = <&pd_adma>;
461 lpd_dma_chan4: dma@ffab0000 {
463 compatible = "xlnx,zynqmp-dma-1.0";
464 reg = <0x0 0xffab0000 0x1000>;
465 interrupt-parent = <&gic>;
466 interrupts = <0 80 4>;
467 xlnx,bus-width = <64>;
468 #stream-id-cells = <1>;
469 iommus = <&smmu 0x86b>;
470 power-domains = <&pd_adma>;
473 lpd_dma_chan5: dma@ffac0000 {
475 compatible = "xlnx,zynqmp-dma-1.0";
476 reg = <0x0 0xffac0000 0x1000>;
477 interrupt-parent = <&gic>;
478 interrupts = <0 81 4>;
479 xlnx,bus-width = <64>;
480 #stream-id-cells = <1>;
481 iommus = <&smmu 0x86c>;
482 power-domains = <&pd_adma>;
485 lpd_dma_chan6: dma@ffad0000 {
487 compatible = "xlnx,zynqmp-dma-1.0";
488 reg = <0x0 0xffad0000 0x1000>;
489 interrupt-parent = <&gic>;
490 interrupts = <0 82 4>;
491 xlnx,bus-width = <64>;
492 #stream-id-cells = <1>;
493 iommus = <&smmu 0x86d>;
494 power-domains = <&pd_adma>;
497 lpd_dma_chan7: dma@ffae0000 {
499 compatible = "xlnx,zynqmp-dma-1.0";
500 reg = <0x0 0xffae0000 0x1000>;
501 interrupt-parent = <&gic>;
502 interrupts = <0 83 4>;
503 xlnx,bus-width = <64>;
504 #stream-id-cells = <1>;
505 iommus = <&smmu 0x86e>;
506 power-domains = <&pd_adma>;
509 lpd_dma_chan8: dma@ffaf0000 {
511 compatible = "xlnx,zynqmp-dma-1.0";
512 reg = <0x0 0xffaf0000 0x1000>;
513 interrupt-parent = <&gic>;
514 interrupts = <0 84 4>;
515 xlnx,bus-width = <64>;
516 #stream-id-cells = <1>;
517 iommus = <&smmu 0x86f>;
518 power-domains = <&pd_adma>;
521 mc: memory-controller@fd070000 {
522 compatible = "xlnx,zynqmp-ddrc-2.40a";
523 reg = <0x0 0xfd070000 0x30000>;
524 interrupt-parent = <&gic>;
525 interrupts = <0 112 4>;
528 nand0: nand@ff100000 {
529 compatible = "arasan,nfc-v3p10";
531 reg = <0x0 0xff100000 0x1000>;
532 clock-names = "clk_sys", "clk_flash";
533 interrupt-parent = <&gic>;
534 interrupts = <0 14 4>;
535 #address-cells = <2>;
537 #stream-id-cells = <1>;
538 iommus = <&smmu 0x872>;
539 power-domains = <&pd_nand>;
542 gem0: ethernet@ff0b0000 {
543 compatible = "cdns,zynqmp-gem";
545 interrupt-parent = <&gic>;
546 interrupts = <0 57 4>, <0 57 4>;
547 reg = <0x0 0xff0b0000 0x1000>;
548 clock-names = "pclk", "hclk", "tx_clk";
549 #address-cells = <1>;
551 #stream-id-cells = <1>;
552 iommus = <&smmu 0x874>;
553 power-domains = <&pd_eth0>;
556 gem1: ethernet@ff0c0000 {
557 compatible = "cdns,zynqmp-gem";
559 interrupt-parent = <&gic>;
560 interrupts = <0 59 4>, <0 59 4>;
561 reg = <0x0 0xff0c0000 0x1000>;
562 clock-names = "pclk", "hclk", "tx_clk";
563 #address-cells = <1>;
565 #stream-id-cells = <1>;
566 iommus = <&smmu 0x875>;
567 power-domains = <&pd_eth1>;
570 gem2: ethernet@ff0d0000 {
571 compatible = "cdns,zynqmp-gem";
573 interrupt-parent = <&gic>;
574 interrupts = <0 61 4>, <0 61 4>;
575 reg = <0x0 0xff0d0000 0x1000>;
576 clock-names = "pclk", "hclk", "tx_clk";
577 #address-cells = <1>;
579 #stream-id-cells = <1>;
580 iommus = <&smmu 0x876>;
581 power-domains = <&pd_eth2>;
584 gem3: ethernet@ff0e0000 {
585 compatible = "cdns,zynqmp-gem";
587 interrupt-parent = <&gic>;
588 interrupts = <0 63 4>, <0 63 4>;
589 reg = <0x0 0xff0e0000 0x1000>;
590 clock-names = "pclk", "hclk", "tx_clk";
591 #address-cells = <1>;
593 #stream-id-cells = <1>;
594 iommus = <&smmu 0x877>;
595 power-domains = <&pd_eth3>;
598 gpio: gpio@ff0a0000 {
599 compatible = "xlnx,zynqmp-gpio-1.0";
602 interrupt-parent = <&gic>;
603 interrupts = <0 16 4>;
604 interrupt-controller;
605 #interrupt-cells = <2>;
606 reg = <0x0 0xff0a0000 0x1000>;
607 power-domains = <&pd_gpio>;
611 compatible = "cdns,i2c-r1p10";
613 interrupt-parent = <&gic>;
614 interrupts = <0 17 4>;
615 reg = <0x0 0xff020000 0x1000>;
616 #address-cells = <1>;
618 power-domains = <&pd_i2c0>;
622 compatible = "cdns,i2c-r1p10";
624 interrupt-parent = <&gic>;
625 interrupts = <0 18 4>;
626 reg = <0x0 0xff030000 0x1000>;
627 #address-cells = <1>;
629 power-domains = <&pd_i2c1>;
632 pcie: pcie@fd0e0000 {
633 compatible = "xlnx,nwl-pcie-2.11";
635 #address-cells = <3>;
637 #interrupt-cells = <1>;
640 interrupt-parent = <&gic>;
641 interrupts = <0 118 4>,
644 <0 115 4>, /* MSI_1 [63...32] */
645 <0 114 4>; /* MSI_0 [31...0] */
646 interrupt-names = "misc","dummy","intx", "msi1", "msi0";
647 msi-parent = <&pcie>;
648 reg = <0x0 0xfd0e0000 0x1000>,
649 <0x0 0xfd480000 0x1000>,
650 <0x0 0xe0000000 0x1000000>;
651 reg-names = "breg", "pcireg", "cfg";
652 ranges = <0x02000000 0x00000000 0xe1000000 0x00000000 0xe1000000 0 0x0f000000>;
653 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
654 interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
655 <0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
656 <0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
657 <0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
658 power-domains = <&pd_pcie>;
659 pcie_intc: legacy-interrupt-controller {
660 interrupt-controller;
661 #address-cells = <0>;
662 #interrupt-cells = <1>;
667 compatible = "xlnx,zynqmp-qspi-1.0";
669 clock-names = "ref_clk", "pclk";
670 interrupts = <0 15 4>;
671 interrupt-parent = <&gic>;
673 reg = <0x0 0xff0f0000 0x1000>,
674 <0x0 0xc0000000 0x8000000>;
675 #address-cells = <1>;
677 #stream-id-cells = <1>;
678 iommus = <&smmu 0x873>;
679 power-domains = <&pd_qspi>;
683 compatible = "xlnx,zynqmp-rtc";
685 reg = <0x0 0xffa60000 0x100>;
686 interrupt-parent = <&gic>;
687 interrupts = <0 26 4>, <0 27 4>;
688 interrupt-names = "alarm", "sec";
691 sata: ahci@fd0c0000 {
692 compatible = "ceva,ahci-1v84";
694 reg = <0x0 0xfd0c0000 0x2000>;
695 interrupt-parent = <&gic>;
696 interrupts = <0 133 4>;
697 power-domains = <&pd_sata>;
700 sdhci0: sdhci@ff160000 {
702 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
704 interrupt-parent = <&gic>;
705 interrupts = <0 48 4>;
706 reg = <0x0 0xff160000 0x1000>;
707 clock-names = "clk_xin", "clk_ahb";
709 xlnx,device_id = <0>;
710 #stream-id-cells = <1>;
711 iommus = <&smmu 0x870>;
712 power-domains = <&pd_sd0>;
715 sdhci1: sdhci@ff170000 {
717 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
719 interrupt-parent = <&gic>;
720 interrupts = <0 49 4>;
721 reg = <0x0 0xff170000 0x1000>;
722 clock-names = "clk_xin", "clk_ahb";
724 xlnx,device_id = <1>;
725 #stream-id-cells = <1>;
726 iommus = <&smmu 0x871>;
727 power-domains = <&pd_sd1>;
730 smmu: smmu@fd800000 {
731 compatible = "arm,mmu-500";
732 reg = <0x0 0xfd800000 0x20000>;
734 #global-interrupts = <1>;
735 interrupt-parent = <&gic>;
736 interrupts = <0 155 4>,
737 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
738 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
739 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
740 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;
741 mmu-masters = < &gem0 0x874
756 &fpd_dma_chan1 0x14e8
757 &fpd_dma_chan2 0x14e9
758 &fpd_dma_chan3 0x14ea
759 &fpd_dma_chan4 0x14eb
760 &fpd_dma_chan5 0x14ec
761 &fpd_dma_chan6 0x14ed
762 &fpd_dma_chan7 0x14ee
763 &fpd_dma_chan8 0x14ef
770 compatible = "cdns,spi-r1p6";
772 interrupt-parent = <&gic>;
773 interrupts = <0 19 4>;
774 reg = <0x0 0xff040000 0x1000>;
775 clock-names = "ref_clk", "pclk";
776 #address-cells = <1>;
778 power-domains = <&pd_spi0>;
782 compatible = "cdns,spi-r1p6";
784 interrupt-parent = <&gic>;
785 interrupts = <0 20 4>;
786 reg = <0x0 0xff050000 0x1000>;
787 clock-names = "ref_clk", "pclk";
788 #address-cells = <1>;
790 power-domains = <&pd_spi1>;
793 ttc0: timer@ff110000 {
794 compatible = "cdns,ttc";
796 interrupt-parent = <&gic>;
797 interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
798 reg = <0x0 0xff110000 0x1000>;
800 power-domains = <&pd_ttc0>;
803 ttc1: timer@ff120000 {
804 compatible = "cdns,ttc";
806 interrupt-parent = <&gic>;
807 interrupts = <0 39 4>, <0 40 4>, <0 41 4>;
808 reg = <0x0 0xff120000 0x1000>;
810 power-domains = <&pd_ttc1>;
813 ttc2: timer@ff130000 {
814 compatible = "cdns,ttc";
816 interrupt-parent = <&gic>;
817 interrupts = <0 42 4>, <0 43 4>, <0 44 4>;
818 reg = <0x0 0xff130000 0x1000>;
820 power-domains = <&pd_ttc2>;
823 ttc3: timer@ff140000 {
824 compatible = "cdns,ttc";
826 interrupt-parent = <&gic>;
827 interrupts = <0 45 4>, <0 46 4>, <0 47 4>;
828 reg = <0x0 0xff140000 0x1000>;
830 power-domains = <&pd_ttc3>;
833 uart0: serial@ff000000 {
835 compatible = "cdns,uart-r1p12", "xlnx,xuartps";
837 interrupt-parent = <&gic>;
838 interrupts = <0 21 4>;
839 reg = <0x0 0xff000000 0x1000>;
840 clock-names = "uart_clk", "pclk";
841 power-domains = <&pd_uart0>;
844 uart1: serial@ff010000 {
846 compatible = "cdns,uart-r1p12", "xlnx,xuartps";
848 interrupt-parent = <&gic>;
849 interrupts = <0 22 4>;
850 reg = <0x0 0xff010000 0x1000>;
851 clock-names = "uart_clk", "pclk";
852 power-domains = <&pd_uart1>;
856 #address-cells = <2>;
859 compatible = "xlnx,zynqmp-dwc3";
860 clock-names = "bus_clk", "ref_clk";
861 clocks = <&clk125>, <&clk125>;
862 #stream-id-cells = <1>;
863 iommus = <&smmu 0x860>;
864 power-domains = <&pd_usb0>;
867 dwc3_0: dwc3@fe200000 {
868 compatible = "snps,dwc3";
870 reg = <0x0 0xfe200000 0x40000>;
871 interrupt-parent = <&gic>;
872 interrupts = <0 65 4>;
873 /* snps,quirk-frame-length-adjustment = <0x20>; */
879 #address-cells = <2>;
882 compatible = "xlnx,zynqmp-dwc3";
883 clock-names = "bus_clk", "ref_clk";
884 clocks = <&clk125>, <&clk125>;
885 #stream-id-cells = <1>;
886 iommus = <&smmu 0x861>;
887 power-domains = <&pd_usb1>;
890 dwc3_1: dwc3@fe300000 {
891 compatible = "snps,dwc3";
893 reg = <0x0 0xfe300000 0x40000>;
894 interrupt-parent = <&gic>;
895 interrupts = <0 70 4>;
896 /* snps,quirk-frame-length-adjustment = <0x20>; */
901 watchdog0: watchdog@fd4d0000 {
902 compatible = "cdns,wdt-r1p2";
904 interrupt-parent = <&gic>;
905 interrupts = <0 113 1>;
906 reg = <0x0 0xfd4d0000 0x1000>;
910 xilinx_drm: xilinx_drm {
911 compatible = "xlnx,drm";
913 xlnx,encoder-slave = <&xlnx_dp>;
914 xlnx,connector-type = "DisplayPort";
915 xlnx,dp-sub = <&xlnx_dp_sub>;
917 xlnx,pixel-format = "rgb565";
919 dmas = <&xlnx_dpdma 3>;
923 dmas = <&xlnx_dpdma 0>,
926 dma-names = "dma0", "dma1", "dma2";
931 xlnx_dp: dp@fd4a0000 {
932 compatible = "xlnx,v-dp";
934 reg = <0x0 0xfd4a0000 0x1000>;
935 interrupts = <0 119 4>;
936 interrupt-parent = <&gic>;
937 clock-names = "aclk", "aud_clk";
938 xlnx,dp-version = "v1.2";
939 xlnx,max-lanes = <2>;
940 xlnx,max-link-rate = <540000>;
943 xlnx,colormetry = "rgb";
945 xlnx,audio-chan = <2>;
946 xlnx,dp-sub = <&xlnx_dp_sub>;
947 xlnx,max-pclock-frequency = <300000>;
950 xlnx_dp_snd_card: dp_snd_card {
951 compatible = "xlnx,dp-snd-card";
953 xlnx,dp-snd-pcm = <&xlnx_dp_snd_pcm0>, <&xlnx_dp_snd_pcm1>;
954 xlnx,dp-snd-codec = <&xlnx_dp_snd_codec0>;
957 xlnx_dp_snd_codec0: dp_snd_codec0 {
958 compatible = "xlnx,dp-snd-codec";
960 clock-names = "aud_clk";
963 xlnx_dp_snd_pcm0: dp_snd_pcm0 {
964 compatible = "xlnx,dp-snd-pcm";
966 dmas = <&xlnx_dpdma 4>;
970 xlnx_dp_snd_pcm1: dp_snd_pcm1 {
971 compatible = "xlnx,dp-snd-pcm";
973 dmas = <&xlnx_dpdma 5>;
977 xlnx_dp_sub: dp_sub@fd4aa000 {
978 compatible = "xlnx,dp-sub";
980 reg = <0x0 0xfd4aa000 0x1000>,
981 <0x0 0xfd4ab000 0x1000>,
982 <0x0 0xfd4ac000 0x1000>;
983 reg-names = "blend", "av_buf", "aud";
984 xlnx,output-fmt = "rgb";
985 xlnx,vid-fmt = "yuyv";
986 xlnx,gfx-fmt = "rgb565";
989 xlnx_dpdma: dma@fd4c0000 {
990 compatible = "xlnx,dpdma";
992 reg = <0x0 0xfd4c0000 0x1000>;
993 interrupts = <0 122 4>;
994 interrupt-parent = <&gic>;
995 clock-names = "axi_clk";
999 compatible = "xlnx,video0";
1002 compatible = "xlnx,video1";
1005 compatible = "xlnx,video2";
1007 dma-graphicschannel {
1008 compatible = "xlnx,graphics";
1011 compatible = "xlnx,audio0";
1014 compatible = "xlnx,audio1";