2 * dts file for Xilinx ZynqMP
4 * (C) Copyright 2014 - 2015, Xilinx, Inc.
6 * Michal Simek <michal.simek@xilinx.com>
8 * SPDX-License-Identifier: GPL-2.0+
11 compatible = "xlnx,zynqmp";
20 compatible = "arm,cortex-a53", "arm,armv8";
22 enable-method = "psci";
27 compatible = "arm,cortex-a53", "arm,armv8";
29 enable-method = "psci";
34 compatible = "arm,cortex-a53", "arm,armv8";
36 enable-method = "psci";
41 compatible = "arm,cortex-a53", "arm,armv8";
43 enable-method = "psci";
49 compatible = "arm,dcc";
55 compatible = "xlnx,zynqmp-genpd";
58 #power-domain-cells = <0x0>;
63 #power-domain-cells = <0x0>;
68 #power-domain-cells = <0x0>;
73 #power-domain-cells = <0x0>;
78 #power-domain-cells = <0x0>;
83 #power-domain-cells = <0x0>;
88 #power-domain-cells = <0x0>;
93 #power-domain-cells = <0x0>;
98 #power-domain-cells = <0x0>;
103 #power-domain-cells = <0x0>;
108 #power-domain-cells = <0x0>;
113 #power-domain-cells = <0x0>;
118 #power-domain-cells = <0x0>;
123 /* fixme: what to attach to */
124 #power-domain-cells = <0x0>;
129 #power-domain-cells = <0x0>;
134 #power-domain-cells = <0x0>;
139 #power-domain-cells = <0x0>;
144 #power-domain-cells = <0x0>;
149 #power-domain-cells = <0x0>;
154 #power-domain-cells = <0x0>;
159 #power-domain-cells = <0x0>;
164 #power-domain-cells = <0x0>;
169 #power-domain-cells = <0x0>;
174 #power-domain-cells = <0x0>;
179 #power-domain-cells = <0x0>;
184 #power-domain-cells = <0x0>;
189 #power-domain-cells = <0x0>;
194 #power-domain-cells = <0x0>;
199 #power-domain-cells = <0x0>;
200 pd-id = <0x3a 0x14 0x15>;
205 compatible = "arm,armv8-pmuv3";
206 interrupt-parent = <&gic>;
207 interrupts = <0 143 4>,
214 compatible = "arm,psci-0.2";
219 compatible = "xlnx,zynqmp-pm";
224 compatible = "arm,armv8-timer";
225 interrupt-parent = <&gic>;
226 interrupts = <1 13 0xf01>,
233 compatible = "arm,cortex-a53-edac";
237 compatible = "xlnx,zynqmp-pcap-fpga";
240 amba_apu: amba_apu@0 {
241 compatible = "simple-bus";
242 #address-cells = <2>;
244 ranges = <0 0 0 0 0xffffffff>;
246 gic: interrupt-controller@f9010000 {
247 compatible = "arm,gic-400", "arm,cortex-a15-gic";
248 #interrupt-cells = <3>;
249 reg = <0x0 0xf9010000 0x10000>,
250 <0x0 0xf9020000 0x20000>,
251 <0x0 0xf9040000 0x20000>,
252 <0x0 0xf9060000 0x20000>;
253 interrupt-controller;
254 interrupt-parent = <&gic>;
255 interrupts = <1 9 0xf04>;
260 compatible = "simple-bus";
262 #address-cells = <2>;
267 compatible = "xlnx,zynq-can-1.0";
269 clock-names = "can_clk", "pclk";
270 reg = <0x0 0xff060000 0x0 0x1000>;
271 interrupts = <0 23 4>;
272 interrupt-parent = <&gic>;
273 tx-fifo-depth = <0x40>;
274 rx-fifo-depth = <0x40>;
275 power-domains = <&pd_can0>;
279 compatible = "xlnx,zynq-can-1.0";
281 clock-names = "can_clk", "pclk";
282 reg = <0x0 0xff070000 0x0 0x1000>;
283 interrupts = <0 24 4>;
284 interrupt-parent = <&gic>;
285 tx-fifo-depth = <0x40>;
286 rx-fifo-depth = <0x40>;
287 power-domains = <&pd_can1>;
291 compatible = "arm,cci-400";
292 reg = <0x0 0xfd6e0000 0x0 0x9000>;
293 ranges = <0x0 0x0 0xfd6e0000 0x10000>;
294 #address-cells = <1>;
298 compatible = "arm,cci-400-pmu,r1";
299 reg = <0x9000 0x5000>;
300 interrupt-parent = <&gic>;
301 interrupts = <0 123 4>,
310 fpd_dma_chan1: dma@fd500000 {
312 compatible = "xlnx,zynqmp-dma-1.0";
313 reg = <0x0 0xfd500000 0x0 0x1000>;
314 interrupt-parent = <&gic>;
315 interrupts = <0 124 4>;
316 clock-names = "clk_main", "clk_apb";
317 xlnx,bus-width = <128>;
318 #stream-id-cells = <1>;
319 iommus = <&smmu 0x14e8>;
320 power-domains = <&pd_gdma>;
323 fpd_dma_chan2: dma@fd510000 {
325 compatible = "xlnx,zynqmp-dma-1.0";
326 reg = <0x0 0xfd510000 0x0 0x1000>;
327 interrupt-parent = <&gic>;
328 interrupts = <0 125 4>;
329 clock-names = "clk_main", "clk_apb";
330 xlnx,bus-width = <128>;
331 #stream-id-cells = <1>;
332 iommus = <&smmu 0x14e9>;
333 power-domains = <&pd_gdma>;
336 fpd_dma_chan3: dma@fd520000 {
338 compatible = "xlnx,zynqmp-dma-1.0";
339 reg = <0x0 0xfd520000 0x0 0x1000>;
340 interrupt-parent = <&gic>;
341 interrupts = <0 126 4>;
342 clock-names = "clk_main", "clk_apb";
343 xlnx,bus-width = <128>;
344 #stream-id-cells = <1>;
345 iommus = <&smmu 0x14ea>;
346 power-domains = <&pd_gdma>;
349 fpd_dma_chan4: dma@fd530000 {
351 compatible = "xlnx,zynqmp-dma-1.0";
352 reg = <0x0 0xfd530000 0x0 0x1000>;
353 interrupt-parent = <&gic>;
354 interrupts = <0 127 4>;
355 clock-names = "clk_main", "clk_apb";
356 xlnx,bus-width = <128>;
357 #stream-id-cells = <1>;
358 iommus = <&smmu 0x14eb>;
359 power-domains = <&pd_gdma>;
362 fpd_dma_chan5: dma@fd540000 {
364 compatible = "xlnx,zynqmp-dma-1.0";
365 reg = <0x0 0xfd540000 0x0 0x1000>;
366 interrupt-parent = <&gic>;
367 interrupts = <0 128 4>;
368 clock-names = "clk_main", "clk_apb";
369 xlnx,bus-width = <128>;
370 #stream-id-cells = <1>;
371 iommus = <&smmu 0x14ec>;
372 power-domains = <&pd_gdma>;
375 fpd_dma_chan6: dma@fd550000 {
377 compatible = "xlnx,zynqmp-dma-1.0";
378 reg = <0x0 0xfd550000 0x0 0x1000>;
379 interrupt-parent = <&gic>;
380 interrupts = <0 129 4>;
381 clock-names = "clk_main", "clk_apb";
382 xlnx,bus-width = <128>;
383 #stream-id-cells = <1>;
384 iommus = <&smmu 0x14ed>;
385 power-domains = <&pd_gdma>;
388 fpd_dma_chan7: dma@fd560000 {
390 compatible = "xlnx,zynqmp-dma-1.0";
391 reg = <0x0 0xfd560000 0x0 0x1000>;
392 interrupt-parent = <&gic>;
393 interrupts = <0 130 4>;
394 clock-names = "clk_main", "clk_apb";
395 xlnx,bus-width = <128>;
396 #stream-id-cells = <1>;
397 iommus = <&smmu 0x14ee>;
398 power-domains = <&pd_gdma>;
401 fpd_dma_chan8: dma@fd570000 {
403 compatible = "xlnx,zynqmp-dma-1.0";
404 reg = <0x0 0xfd570000 0x0 0x1000>;
405 interrupt-parent = <&gic>;
406 interrupts = <0 131 4>;
407 clock-names = "clk_main", "clk_apb";
408 xlnx,bus-width = <128>;
409 #stream-id-cells = <1>;
410 iommus = <&smmu 0x14ef>;
411 power-domains = <&pd_gdma>;
416 compatible = "arm,mali-400", "arm,mali-utgard";
417 reg = <0x0 0xfd4b0000 0x0 0x30000>;
418 interrupt-parent = <&gic>;
419 interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>;
420 interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1";
421 power-domains = <&pd_gpu>;
424 /* LPDDMA default allows only secured access. inorder to enable
425 * These dma channels, Users should ensure that these dma
426 * Channels are allowed for non secure access.
428 lpd_dma_chan1: dma@ffa80000 {
430 compatible = "xlnx,zynqmp-dma-1.0";
431 reg = <0x0 0xffa80000 0x0 0x1000>;
432 interrupt-parent = <&gic>;
433 interrupts = <0 77 4>;
434 xlnx,bus-width = <64>;
435 #stream-id-cells = <1>;
436 iommus = <&smmu 0x868>;
437 power-domains = <&pd_adma>;
440 lpd_dma_chan2: dma@ffa90000 {
442 compatible = "xlnx,zynqmp-dma-1.0";
443 reg = <0x0 0xffa90000 0x0 0x1000>;
444 interrupt-parent = <&gic>;
445 interrupts = <0 78 4>;
446 xlnx,bus-width = <64>;
447 #stream-id-cells = <1>;
448 iommus = <&smmu 0x869>;
449 power-domains = <&pd_adma>;
452 lpd_dma_chan3: dma@ffaa0000 {
454 compatible = "xlnx,zynqmp-dma-1.0";
455 reg = <0x0 0xffaa0000 0x0 0x1000>;
456 interrupt-parent = <&gic>;
457 interrupts = <0 79 4>;
458 xlnx,bus-width = <64>;
459 #stream-id-cells = <1>;
460 iommus = <&smmu 0x86a>;
461 power-domains = <&pd_adma>;
464 lpd_dma_chan4: dma@ffab0000 {
466 compatible = "xlnx,zynqmp-dma-1.0";
467 reg = <0x0 0xffab0000 0x0 0x1000>;
468 interrupt-parent = <&gic>;
469 interrupts = <0 80 4>;
470 xlnx,bus-width = <64>;
471 #stream-id-cells = <1>;
472 iommus = <&smmu 0x86b>;
473 power-domains = <&pd_adma>;
476 lpd_dma_chan5: dma@ffac0000 {
478 compatible = "xlnx,zynqmp-dma-1.0";
479 reg = <0x0 0xffac0000 0x0 0x1000>;
480 interrupt-parent = <&gic>;
481 interrupts = <0 81 4>;
482 xlnx,bus-width = <64>;
483 #stream-id-cells = <1>;
484 iommus = <&smmu 0x86c>;
485 power-domains = <&pd_adma>;
488 lpd_dma_chan6: dma@ffad0000 {
490 compatible = "xlnx,zynqmp-dma-1.0";
491 reg = <0x0 0xffad0000 0x0 0x1000>;
492 interrupt-parent = <&gic>;
493 interrupts = <0 82 4>;
494 xlnx,bus-width = <64>;
495 #stream-id-cells = <1>;
496 iommus = <&smmu 0x86d>;
497 power-domains = <&pd_adma>;
500 lpd_dma_chan7: dma@ffae0000 {
502 compatible = "xlnx,zynqmp-dma-1.0";
503 reg = <0x0 0xffae0000 0x0 0x1000>;
504 interrupt-parent = <&gic>;
505 interrupts = <0 83 4>;
506 xlnx,bus-width = <64>;
507 #stream-id-cells = <1>;
508 iommus = <&smmu 0x86e>;
509 power-domains = <&pd_adma>;
512 lpd_dma_chan8: dma@ffaf0000 {
514 compatible = "xlnx,zynqmp-dma-1.0";
515 reg = <0x0 0xffaf0000 0x0 0x1000>;
516 interrupt-parent = <&gic>;
517 interrupts = <0 84 4>;
518 xlnx,bus-width = <64>;
519 #stream-id-cells = <1>;
520 iommus = <&smmu 0x86f>;
521 power-domains = <&pd_adma>;
524 mc: memory-controller@fd070000 {
525 compatible = "xlnx,zynqmp-ddrc-2.40a";
526 reg = <0x0 0xfd070000 0x0 0x30000>;
527 interrupt-parent = <&gic>;
528 interrupts = <0 112 4>;
531 nand0: nand@ff100000 {
532 compatible = "arasan,nfc-v3p10";
534 reg = <0x0 0xff100000 0x0 0x1000>;
535 clock-names = "clk_sys", "clk_flash";
536 interrupt-parent = <&gic>;
537 interrupts = <0 14 4>;
538 #address-cells = <2>;
540 #stream-id-cells = <1>;
541 iommus = <&smmu 0x872>;
542 power-domains = <&pd_nand>;
545 gem0: ethernet@ff0b0000 {
546 compatible = "cdns,zynqmp-gem";
548 interrupt-parent = <&gic>;
549 interrupts = <0 57 4>, <0 57 4>;
550 reg = <0x0 0xff0b0000 0x0 0x1000>;
551 clock-names = "pclk", "hclk", "tx_clk";
552 #address-cells = <1>;
554 #stream-id-cells = <1>;
555 iommus = <&smmu 0x874>;
556 power-domains = <&pd_eth0>;
559 gem1: ethernet@ff0c0000 {
560 compatible = "cdns,zynqmp-gem";
562 interrupt-parent = <&gic>;
563 interrupts = <0 59 4>, <0 59 4>;
564 reg = <0x0 0xff0c0000 0x0 0x1000>;
565 clock-names = "pclk", "hclk", "tx_clk";
566 #address-cells = <1>;
568 #stream-id-cells = <1>;
569 iommus = <&smmu 0x875>;
570 power-domains = <&pd_eth1>;
573 gem2: ethernet@ff0d0000 {
574 compatible = "cdns,zynqmp-gem";
576 interrupt-parent = <&gic>;
577 interrupts = <0 61 4>, <0 61 4>;
578 reg = <0x0 0xff0d0000 0x0 0x1000>;
579 clock-names = "pclk", "hclk", "tx_clk";
580 #address-cells = <1>;
582 #stream-id-cells = <1>;
583 iommus = <&smmu 0x876>;
584 power-domains = <&pd_eth2>;
587 gem3: ethernet@ff0e0000 {
588 compatible = "cdns,zynqmp-gem";
590 interrupt-parent = <&gic>;
591 interrupts = <0 63 4>, <0 63 4>;
592 reg = <0x0 0xff0e0000 0x0 0x1000>;
593 clock-names = "pclk", "hclk", "tx_clk";
594 #address-cells = <1>;
596 #stream-id-cells = <1>;
597 iommus = <&smmu 0x877>;
598 power-domains = <&pd_eth3>;
601 gpio: gpio@ff0a0000 {
602 compatible = "xlnx,zynqmp-gpio-1.0";
605 interrupt-parent = <&gic>;
606 interrupts = <0 16 4>;
607 interrupt-controller;
608 #interrupt-cells = <2>;
609 reg = <0x0 0xff0a0000 0x0 0x1000>;
610 power-domains = <&pd_gpio>;
614 compatible = "cdns,i2c-r1p10";
616 interrupt-parent = <&gic>;
617 interrupts = <0 17 4>;
618 reg = <0x0 0xff020000 0x0 0x1000>;
619 #address-cells = <1>;
621 power-domains = <&pd_i2c0>;
625 compatible = "cdns,i2c-r1p10";
627 interrupt-parent = <&gic>;
628 interrupts = <0 18 4>;
629 reg = <0x0 0xff030000 0x0 0x1000>;
630 #address-cells = <1>;
632 power-domains = <&pd_i2c1>;
635 ocm: memory-controller@ff960000 {
636 compatible = "xlnx,zynqmp-ocmc-1.0";
637 reg = <0x0 0xff960000 0x0 0x1000>;
638 interrupt-parent = <&gic>;
639 interrupts = <0 10 4>;
642 pcie: pcie@fd0e0000 {
643 compatible = "xlnx,nwl-pcie-2.11";
645 #address-cells = <3>;
647 #interrupt-cells = <1>;
650 interrupt-parent = <&gic>;
651 interrupts = <0 118 4>,
654 <0 115 4>, /* MSI_1 [63...32] */
655 <0 114 4>; /* MSI_0 [31...0] */
656 interrupt-names = "misc","dummy","intx", "msi1", "msi0";
657 msi-parent = <&pcie>;
658 reg = <0x0 0xfd0e0000 0x0 0x1000>,
659 <0x0 0xfd480000 0x0 0x1000>,
660 <0x0 0xe0000000 0x0 0x1000000>;
661 reg-names = "breg", "pcireg", "cfg";
662 ranges = <0x02000000 0x00000000 0xe1000000 0x00000000 0xe1000000 0 0x0f000000>;
663 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
664 interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
665 <0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
666 <0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
667 <0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
668 power-domains = <&pd_pcie>;
669 pcie_intc: legacy-interrupt-controller {
670 interrupt-controller;
671 #address-cells = <0>;
672 #interrupt-cells = <1>;
677 compatible = "xlnx,zynqmp-qspi-1.0";
679 clock-names = "ref_clk", "pclk";
680 interrupts = <0 15 4>;
681 interrupt-parent = <&gic>;
683 reg = <0x0 0xff0f0000 0x0 0x1000>,
684 <0x0 0xc0000000 0x0 0x8000000>;
685 #address-cells = <1>;
687 #stream-id-cells = <1>;
688 iommus = <&smmu 0x873>;
689 power-domains = <&pd_qspi>;
693 compatible = "xlnx,zynqmp-rtc";
695 reg = <0x0 0xffa60000 0x0 0x100>;
696 interrupt-parent = <&gic>;
697 interrupts = <0 26 4>, <0 27 4>;
698 interrupt-names = "alarm", "sec";
701 serdes: zynqmp_phy@fd400000 {
702 compatible = "xlnx,zynqmp-psgtr";
704 reg = <0x0 0xfd400000 0x0 0x40000>,
705 <0x0 0xfd3d0000 0x0 0x1000>,
706 <0x0 0xfd1a0000 0x0 0x1000>,
707 <0x0 0xff5e0000 0x0 0x1000>;
708 reg-names = "serdes", "siou", "fpd", "lpd";
709 xlnx,tx_termination_fix;
724 sata: ahci@fd0c0000 {
725 compatible = "ceva,ahci-1v84";
727 reg = <0x0 0xfd0c0000 0x0 0x2000>;
728 interrupt-parent = <&gic>;
729 interrupts = <0 133 4>;
730 power-domains = <&pd_sata>;
733 sdhci0: sdhci@ff160000 {
735 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
737 interrupt-parent = <&gic>;
738 interrupts = <0 48 4>;
739 reg = <0x0 0xff160000 0x0 0x1000>;
740 clock-names = "clk_xin", "clk_ahb";
741 xlnx,device_id = <0>;
742 #stream-id-cells = <1>;
743 iommus = <&smmu 0x870>;
744 power-domains = <&pd_sd0>;
747 sdhci1: sdhci@ff170000 {
749 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
751 interrupt-parent = <&gic>;
752 interrupts = <0 49 4>;
753 reg = <0x0 0xff170000 0x0 0x1000>;
754 clock-names = "clk_xin", "clk_ahb";
755 xlnx,device_id = <1>;
756 #stream-id-cells = <1>;
757 iommus = <&smmu 0x871>;
758 power-domains = <&pd_sd1>;
761 smmu: smmu@fd800000 {
762 compatible = "arm,mmu-500";
763 reg = <0x0 0xfd800000 0x0 0x20000>;
765 #global-interrupts = <1>;
766 interrupt-parent = <&gic>;
767 interrupts = <0 155 4>,
768 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
769 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
770 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
771 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;
772 mmu-masters = < &gem0 0x874
787 &fpd_dma_chan1 0x14e8
788 &fpd_dma_chan2 0x14e9
789 &fpd_dma_chan3 0x14ea
790 &fpd_dma_chan4 0x14eb
791 &fpd_dma_chan5 0x14ec
792 &fpd_dma_chan6 0x14ed
793 &fpd_dma_chan7 0x14ee
794 &fpd_dma_chan8 0x14ef
801 compatible = "cdns,spi-r1p6";
803 interrupt-parent = <&gic>;
804 interrupts = <0 19 4>;
805 reg = <0x0 0xff040000 0x0 0x1000>;
806 clock-names = "ref_clk", "pclk";
807 #address-cells = <1>;
809 power-domains = <&pd_spi0>;
813 compatible = "cdns,spi-r1p6";
815 interrupt-parent = <&gic>;
816 interrupts = <0 20 4>;
817 reg = <0x0 0xff050000 0x0 0x1000>;
818 clock-names = "ref_clk", "pclk";
819 #address-cells = <1>;
821 power-domains = <&pd_spi1>;
824 ttc0: timer@ff110000 {
825 compatible = "cdns,ttc";
827 interrupt-parent = <&gic>;
828 interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
829 reg = <0x0 0xff110000 0x0 0x1000>;
831 power-domains = <&pd_ttc0>;
834 ttc1: timer@ff120000 {
835 compatible = "cdns,ttc";
837 interrupt-parent = <&gic>;
838 interrupts = <0 39 4>, <0 40 4>, <0 41 4>;
839 reg = <0x0 0xff120000 0x0 0x1000>;
841 power-domains = <&pd_ttc1>;
844 ttc2: timer@ff130000 {
845 compatible = "cdns,ttc";
847 interrupt-parent = <&gic>;
848 interrupts = <0 42 4>, <0 43 4>, <0 44 4>;
849 reg = <0x0 0xff130000 0x0 0x1000>;
851 power-domains = <&pd_ttc2>;
854 ttc3: timer@ff140000 {
855 compatible = "cdns,ttc";
857 interrupt-parent = <&gic>;
858 interrupts = <0 45 4>, <0 46 4>, <0 47 4>;
859 reg = <0x0 0xff140000 0x0 0x1000>;
861 power-domains = <&pd_ttc3>;
864 uart0: serial@ff000000 {
866 compatible = "cdns,uart-r1p12", "xlnx,xuartps";
868 interrupt-parent = <&gic>;
869 interrupts = <0 21 4>;
870 reg = <0x0 0xff000000 0x0 0x1000>;
871 clock-names = "uart_clk", "pclk";
872 power-domains = <&pd_uart0>;
875 uart1: serial@ff010000 {
877 compatible = "cdns,uart-r1p12", "xlnx,xuartps";
879 interrupt-parent = <&gic>;
880 interrupts = <0 22 4>;
881 reg = <0x0 0xff010000 0x0 0x1000>;
882 clock-names = "uart_clk", "pclk";
883 power-domains = <&pd_uart1>;
887 #address-cells = <2>;
890 compatible = "xlnx,zynqmp-dwc3";
891 clock-names = "bus_clk", "ref_clk";
892 clocks = <&clk125>, <&clk125>;
893 #stream-id-cells = <1>;
894 iommus = <&smmu 0x860>;
895 power-domains = <&pd_usb0>;
898 dwc3_0: dwc3@fe200000 {
899 compatible = "snps,dwc3";
901 reg = <0x0 0xfe200000 0x0 0x40000>;
902 interrupt-parent = <&gic>;
903 interrupts = <0 65 4>;
904 /* snps,quirk-frame-length-adjustment = <0x20>; */
910 #address-cells = <2>;
913 compatible = "xlnx,zynqmp-dwc3";
914 clock-names = "bus_clk", "ref_clk";
915 clocks = <&clk125>, <&clk125>;
916 #stream-id-cells = <1>;
917 iommus = <&smmu 0x861>;
918 power-domains = <&pd_usb1>;
921 dwc3_1: dwc3@fe300000 {
922 compatible = "snps,dwc3";
924 reg = <0x0 0xfe300000 0x0 0x40000>;
925 interrupt-parent = <&gic>;
926 interrupts = <0 70 4>;
927 /* snps,quirk-frame-length-adjustment = <0x20>; */
932 watchdog0: watchdog@fd4d0000 {
933 compatible = "cdns,wdt-r1p2";
935 interrupt-parent = <&gic>;
936 interrupts = <0 113 1>;
937 reg = <0x0 0xfd4d0000 0x0 0x1000>;
941 xilinx_drm: xilinx_drm {
942 compatible = "xlnx,drm";
944 xlnx,encoder-slave = <&xlnx_dp>;
945 xlnx,connector-type = "DisplayPort";
946 xlnx,dp-sub = <&xlnx_dp_sub>;
948 xlnx,pixel-format = "rgb565";
950 dmas = <&xlnx_dpdma 3>;
954 dmas = <&xlnx_dpdma 0>,
957 dma-names = "dma0", "dma1", "dma2";
962 xlnx_dp: dp@fd4a0000 {
963 compatible = "xlnx,v-dp";
965 reg = <0x0 0xfd4a0000 0x0 0x1000>;
966 interrupts = <0 119 4>;
967 interrupt-parent = <&gic>;
968 clock-names = "aclk", "aud_clk";
969 xlnx,dp-version = "v1.2";
970 xlnx,max-lanes = <2>;
971 xlnx,max-link-rate = <540000>;
974 xlnx,colormetry = "rgb";
976 xlnx,audio-chan = <2>;
977 xlnx,dp-sub = <&xlnx_dp_sub>;
978 xlnx,max-pclock-frequency = <300000>;
981 xlnx_dp_snd_card: dp_snd_card {
982 compatible = "xlnx,dp-snd-card";
984 xlnx,dp-snd-pcm = <&xlnx_dp_snd_pcm0>, <&xlnx_dp_snd_pcm1>;
985 xlnx,dp-snd-codec = <&xlnx_dp_snd_codec0>;
988 xlnx_dp_snd_codec0: dp_snd_codec0 {
989 compatible = "xlnx,dp-snd-codec";
991 clock-names = "aud_clk";
994 xlnx_dp_snd_pcm0: dp_snd_pcm0 {
995 compatible = "xlnx,dp-snd-pcm";
997 dmas = <&xlnx_dpdma 4>;
1001 xlnx_dp_snd_pcm1: dp_snd_pcm1 {
1002 compatible = "xlnx,dp-snd-pcm";
1003 status = "disabled";
1004 dmas = <&xlnx_dpdma 5>;
1008 xlnx_dp_sub: dp_sub@fd4aa000 {
1009 compatible = "xlnx,dp-sub";
1010 status = "disabled";
1011 reg = <0x0 0xfd4aa000 0x0 0x1000>,
1012 <0x0 0xfd4ab000 0x0 0x1000>,
1013 <0x0 0xfd4ac000 0x0 0x1000>;
1014 reg-names = "blend", "av_buf", "aud";
1015 xlnx,output-fmt = "rgb";
1016 xlnx,vid-fmt = "yuyv";
1017 xlnx,gfx-fmt = "rgb565";
1020 xlnx_dpdma: dma@fd4c0000 {
1021 compatible = "xlnx,dpdma";
1022 status = "disabled";
1023 reg = <0x0 0xfd4c0000 0x0 0x1000>;
1024 interrupts = <0 122 4>;
1025 interrupt-parent = <&gic>;
1026 clock-names = "axi_clk";
1030 compatible = "xlnx,video0";
1033 compatible = "xlnx,video1";
1036 compatible = "xlnx,video2";
1038 dma-graphicschannel {
1039 compatible = "xlnx,graphics";
1042 compatible = "xlnx,audio0";
1045 compatible = "xlnx,audio1";