1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP
5 * (C) Copyright 2014 - 2015, Xilinx, Inc.
7 * Michal Simek <michal.simek@xilinx.com>
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
15 #include <dt-bindings/power/xlnx-zynqmp-power.h>
16 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
19 compatible = "xlnx,zynqmp";
28 compatible = "arm,cortex-a53";
30 enable-method = "psci";
31 operating-points-v2 = <&cpu_opp_table>;
33 cpu-idle-states = <&CPU_SLEEP_0>;
37 compatible = "arm,cortex-a53";
39 enable-method = "psci";
41 operating-points-v2 = <&cpu_opp_table>;
42 cpu-idle-states = <&CPU_SLEEP_0>;
46 compatible = "arm,cortex-a53";
48 enable-method = "psci";
50 operating-points-v2 = <&cpu_opp_table>;
51 cpu-idle-states = <&CPU_SLEEP_0>;
55 compatible = "arm,cortex-a53";
57 enable-method = "psci";
59 operating-points-v2 = <&cpu_opp_table>;
60 cpu-idle-states = <&CPU_SLEEP_0>;
64 entry-method = "psci";
66 CPU_SLEEP_0: cpu-sleep-0 {
67 compatible = "arm,idle-state";
68 arm,psci-suspend-param = <0x40000000>;
70 entry-latency-us = <300>;
71 exit-latency-us = <600>;
72 min-residency-us = <10000>;
77 cpu_opp_table: cpu-opp-table {
78 compatible = "operating-points-v2";
81 opp-hz = /bits/ 64 <1199999988>;
82 opp-microvolt = <1000000>;
83 clock-latency-ns = <500000>;
86 opp-hz = /bits/ 64 <599999994>;
87 opp-microvolt = <1000000>;
88 clock-latency-ns = <500000>;
91 opp-hz = /bits/ 64 <399999996>;
92 opp-microvolt = <1000000>;
93 clock-latency-ns = <500000>;
96 opp-hz = /bits/ 64 <299999997>;
97 opp-microvolt = <1000000>;
98 clock-latency-ns = <500000>;
104 compatible = "xlnx,zynqmp-ipi-mailbox";
105 interrupt-parent = <&gic>;
106 interrupts = <0 35 4>;
108 #address-cells = <2>;
112 ipi_mailbox_pmu1: mailbox@ff990400 {
114 reg = <0x0 0xff9905c0 0x0 0x20>,
115 <0x0 0xff9905e0 0x0 0x20>,
116 <0x0 0xff990e80 0x0 0x20>,
117 <0x0 0xff990ea0 0x0 0x20>;
118 reg-names = "local_request_region", "local_response_region",
119 "remote_request_region", "remote_response_region";
126 compatible = "arm,dcc";
132 compatible = "arm,armv8-pmuv3";
133 interrupt-parent = <&gic>;
134 interrupts = <0 143 4>,
141 compatible = "arm,psci-0.2";
146 zynqmp_firmware: zynqmp-firmware {
147 compatible = "xlnx,zynqmp-firmware";
149 #power-domain-cells = <0x1>;
152 zynqmp_power: zynqmp-power {
154 compatible = "xlnx,zynqmp-power";
155 interrupt-parent = <&gic>;
156 interrupts = <0 35 4>;
157 mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>;
158 mbox-names = "tx", "rx";
161 zynqmp_reset: reset-controller {
162 compatible = "xlnx,zynqmp-reset";
169 compatible = "arm,armv8-timer";
170 interrupt-parent = <&gic>;
171 interrupts = <1 13 0xf08>,
178 compatible = "arm,cortex-a53-edac";
181 fpga_full: fpga-full {
182 compatible = "fpga-region";
184 #address-cells = <2>;
189 compatible = "xlnx,zynqmp-nvmem-fw";
190 #address-cells = <1>;
193 soc_revision: soc_revision@0 {
199 compatible = "xlnx,zynqmp-pcap-fpga";
202 rst: reset-controller {
203 compatible = "xlnx,zynqmp-reset";
207 xlnx_dp_snd_card: dp_snd_card {
208 compatible = "xlnx,dp-snd-card";
210 xlnx,dp-snd-pcm = <&xlnx_dp_snd_pcm0>, <&xlnx_dp_snd_pcm1>;
211 xlnx,dp-snd-codec = <&xlnx_dp_snd_codec0>;
214 xlnx_dp_snd_codec0: dp_snd_codec0 {
215 compatible = "xlnx,dp-snd-codec";
217 clock-names = "aud_clk";
220 xlnx_dp_snd_pcm0: dp_snd_pcm0 {
221 compatible = "xlnx,dp-snd-pcm";
223 dmas = <&xlnx_dpdma 4>;
227 xlnx_dp_snd_pcm1: dp_snd_pcm1 {
228 compatible = "xlnx,dp-snd-pcm";
230 dmas = <&xlnx_dpdma 5>;
234 xilinx_drm: xilinx_drm {
235 compatible = "xlnx,drm";
237 xlnx,encoder-slave = <&xlnx_dp>;
238 xlnx,connector-type = "DisplayPort";
239 xlnx,dp-sub = <&xlnx_dp_sub>;
241 xlnx,pixel-format = "rgb565";
243 dmas = <&xlnx_dpdma 3>;
247 dmas = <&xlnx_dpdma 0>,
250 dma-names = "dma0", "dma1", "dma2";
255 amba_apu: amba-apu@0 {
256 compatible = "simple-bus";
257 #address-cells = <2>;
259 ranges = <0 0 0 0 0xffffffff>;
261 gic: interrupt-controller@f9010000 {
262 compatible = "arm,gic-400", "arm,cortex-a15-gic";
263 #interrupt-cells = <3>;
264 reg = <0x0 0xf9010000 0x10000>,
265 <0x0 0xf9020000 0x20000>,
266 <0x0 0xf9040000 0x20000>,
267 <0x0 0xf9060000 0x20000>;
268 interrupt-controller;
269 interrupt-parent = <&gic>;
270 interrupts = <1 9 0xf04>;
275 compatible = "simple-bus";
277 #address-cells = <2>;
282 compatible = "xlnx,zynq-can-1.0";
284 clock-names = "can_clk", "pclk";
285 reg = <0x0 0xff060000 0x0 0x1000>;
286 interrupts = <0 23 4>;
287 interrupt-parent = <&gic>;
288 tx-fifo-depth = <0x40>;
289 rx-fifo-depth = <0x40>;
290 power-domains = <&zynqmp_firmware PD_CAN_0>;
294 compatible = "xlnx,zynq-can-1.0";
296 clock-names = "can_clk", "pclk";
297 reg = <0x0 0xff070000 0x0 0x1000>;
298 interrupts = <0 24 4>;
299 interrupt-parent = <&gic>;
300 tx-fifo-depth = <0x40>;
301 rx-fifo-depth = <0x40>;
302 power-domains = <&zynqmp_firmware PD_CAN_1>;
306 compatible = "arm,cci-400";
307 reg = <0x0 0xfd6e0000 0x0 0x9000>;
308 ranges = <0x0 0x0 0xfd6e0000 0x10000>;
309 #address-cells = <1>;
313 compatible = "arm,cci-400-pmu,r1";
314 reg = <0x9000 0x5000>;
315 interrupt-parent = <&gic>;
316 interrupts = <0 123 4>,
325 fpd_dma_chan1: dma@fd500000 {
327 compatible = "xlnx,zynqmp-dma-1.0";
328 reg = <0x0 0xfd500000 0x0 0x1000>;
329 interrupt-parent = <&gic>;
330 interrupts = <0 124 4>;
331 clock-names = "clk_main", "clk_apb";
332 xlnx,bus-width = <128>;
333 #stream-id-cells = <1>;
334 iommus = <&smmu 0x14e8>;
335 power-domains = <&zynqmp_firmware PD_GDMA>;
338 fpd_dma_chan2: dma@fd510000 {
340 compatible = "xlnx,zynqmp-dma-1.0";
341 reg = <0x0 0xfd510000 0x0 0x1000>;
342 interrupt-parent = <&gic>;
343 interrupts = <0 125 4>;
344 clock-names = "clk_main", "clk_apb";
345 xlnx,bus-width = <128>;
346 #stream-id-cells = <1>;
347 iommus = <&smmu 0x14e9>;
348 power-domains = <&zynqmp_firmware PD_GDMA>;
351 fpd_dma_chan3: dma@fd520000 {
353 compatible = "xlnx,zynqmp-dma-1.0";
354 reg = <0x0 0xfd520000 0x0 0x1000>;
355 interrupt-parent = <&gic>;
356 interrupts = <0 126 4>;
357 clock-names = "clk_main", "clk_apb";
358 xlnx,bus-width = <128>;
359 #stream-id-cells = <1>;
360 iommus = <&smmu 0x14ea>;
361 power-domains = <&zynqmp_firmware PD_GDMA>;
364 fpd_dma_chan4: dma@fd530000 {
366 compatible = "xlnx,zynqmp-dma-1.0";
367 reg = <0x0 0xfd530000 0x0 0x1000>;
368 interrupt-parent = <&gic>;
369 interrupts = <0 127 4>;
370 clock-names = "clk_main", "clk_apb";
371 xlnx,bus-width = <128>;
372 #stream-id-cells = <1>;
373 iommus = <&smmu 0x14eb>;
374 power-domains = <&zynqmp_firmware PD_GDMA>;
377 fpd_dma_chan5: dma@fd540000 {
379 compatible = "xlnx,zynqmp-dma-1.0";
380 reg = <0x0 0xfd540000 0x0 0x1000>;
381 interrupt-parent = <&gic>;
382 interrupts = <0 128 4>;
383 clock-names = "clk_main", "clk_apb";
384 xlnx,bus-width = <128>;
385 #stream-id-cells = <1>;
386 iommus = <&smmu 0x14ec>;
387 power-domains = <&zynqmp_firmware PD_GDMA>;
390 fpd_dma_chan6: dma@fd550000 {
392 compatible = "xlnx,zynqmp-dma-1.0";
393 reg = <0x0 0xfd550000 0x0 0x1000>;
394 interrupt-parent = <&gic>;
395 interrupts = <0 129 4>;
396 clock-names = "clk_main", "clk_apb";
397 xlnx,bus-width = <128>;
398 #stream-id-cells = <1>;
399 iommus = <&smmu 0x14ed>;
400 power-domains = <&zynqmp_firmware PD_GDMA>;
403 fpd_dma_chan7: dma@fd560000 {
405 compatible = "xlnx,zynqmp-dma-1.0";
406 reg = <0x0 0xfd560000 0x0 0x1000>;
407 interrupt-parent = <&gic>;
408 interrupts = <0 130 4>;
409 clock-names = "clk_main", "clk_apb";
410 xlnx,bus-width = <128>;
411 #stream-id-cells = <1>;
412 iommus = <&smmu 0x14ee>;
413 power-domains = <&zynqmp_firmware PD_GDMA>;
416 fpd_dma_chan8: dma@fd570000 {
418 compatible = "xlnx,zynqmp-dma-1.0";
419 reg = <0x0 0xfd570000 0x0 0x1000>;
420 interrupt-parent = <&gic>;
421 interrupts = <0 131 4>;
422 clock-names = "clk_main", "clk_apb";
423 xlnx,bus-width = <128>;
424 #stream-id-cells = <1>;
425 iommus = <&smmu 0x14ef>;
426 power-domains = <&zynqmp_firmware PD_GDMA>;
431 compatible = "arm,mali-400", "arm,mali-utgard";
432 reg = <0x0 0xfd4b0000 0x0 0x10000>;
433 interrupt-parent = <&gic>;
434 interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>;
435 interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1";
436 clock-names = "gpu", "gpu_pp0", "gpu_pp1";
437 power-domains = <&zynqmp_firmware PD_GPU>;
440 /* LPDDMA default allows only secured access. inorder to enable
441 * These dma channels, Users should ensure that these dma
442 * Channels are allowed for non secure access.
444 lpd_dma_chan1: dma@ffa80000 {
446 compatible = "xlnx,zynqmp-dma-1.0";
447 reg = <0x0 0xffa80000 0x0 0x1000>;
448 interrupt-parent = <&gic>;
449 interrupts = <0 77 4>;
450 clock-names = "clk_main", "clk_apb";
451 xlnx,bus-width = <64>;
452 #stream-id-cells = <1>;
453 iommus = <&smmu 0x868>;
454 power-domains = <&zynqmp_firmware PD_ADMA>;
457 lpd_dma_chan2: dma@ffa90000 {
459 compatible = "xlnx,zynqmp-dma-1.0";
460 reg = <0x0 0xffa90000 0x0 0x1000>;
461 interrupt-parent = <&gic>;
462 interrupts = <0 78 4>;
463 clock-names = "clk_main", "clk_apb";
464 xlnx,bus-width = <64>;
465 #stream-id-cells = <1>;
466 iommus = <&smmu 0x869>;
467 power-domains = <&zynqmp_firmware PD_ADMA>;
470 lpd_dma_chan3: dma@ffaa0000 {
472 compatible = "xlnx,zynqmp-dma-1.0";
473 reg = <0x0 0xffaa0000 0x0 0x1000>;
474 interrupt-parent = <&gic>;
475 interrupts = <0 79 4>;
476 clock-names = "clk_main", "clk_apb";
477 xlnx,bus-width = <64>;
478 #stream-id-cells = <1>;
479 iommus = <&smmu 0x86a>;
480 power-domains = <&zynqmp_firmware PD_ADMA>;
483 lpd_dma_chan4: dma@ffab0000 {
485 compatible = "xlnx,zynqmp-dma-1.0";
486 reg = <0x0 0xffab0000 0x0 0x1000>;
487 interrupt-parent = <&gic>;
488 interrupts = <0 80 4>;
489 clock-names = "clk_main", "clk_apb";
490 xlnx,bus-width = <64>;
491 #stream-id-cells = <1>;
492 iommus = <&smmu 0x86b>;
493 power-domains = <&zynqmp_firmware PD_ADMA>;
496 lpd_dma_chan5: dma@ffac0000 {
498 compatible = "xlnx,zynqmp-dma-1.0";
499 reg = <0x0 0xffac0000 0x0 0x1000>;
500 interrupt-parent = <&gic>;
501 interrupts = <0 81 4>;
502 clock-names = "clk_main", "clk_apb";
503 xlnx,bus-width = <64>;
504 #stream-id-cells = <1>;
505 iommus = <&smmu 0x86c>;
506 power-domains = <&zynqmp_firmware PD_ADMA>;
509 lpd_dma_chan6: dma@ffad0000 {
511 compatible = "xlnx,zynqmp-dma-1.0";
512 reg = <0x0 0xffad0000 0x0 0x1000>;
513 interrupt-parent = <&gic>;
514 interrupts = <0 82 4>;
515 clock-names = "clk_main", "clk_apb";
516 xlnx,bus-width = <64>;
517 #stream-id-cells = <1>;
518 iommus = <&smmu 0x86d>;
519 power-domains = <&zynqmp_firmware PD_ADMA>;
522 lpd_dma_chan7: dma@ffae0000 {
524 compatible = "xlnx,zynqmp-dma-1.0";
525 reg = <0x0 0xffae0000 0x0 0x1000>;
526 interrupt-parent = <&gic>;
527 interrupts = <0 83 4>;
528 clock-names = "clk_main", "clk_apb";
529 xlnx,bus-width = <64>;
530 #stream-id-cells = <1>;
531 iommus = <&smmu 0x86e>;
532 power-domains = <&zynqmp_firmware PD_ADMA>;
535 lpd_dma_chan8: dma@ffaf0000 {
537 compatible = "xlnx,zynqmp-dma-1.0";
538 reg = <0x0 0xffaf0000 0x0 0x1000>;
539 interrupt-parent = <&gic>;
540 interrupts = <0 84 4>;
541 clock-names = "clk_main", "clk_apb";
542 xlnx,bus-width = <64>;
543 #stream-id-cells = <1>;
544 iommus = <&smmu 0x86f>;
545 power-domains = <&zynqmp_firmware PD_ADMA>;
548 mc: memory-controller@fd070000 {
549 compatible = "xlnx,zynqmp-ddrc-2.40a";
550 reg = <0x0 0xfd070000 0x0 0x30000>;
551 interrupt-parent = <&gic>;
552 interrupts = <0 112 4>;
555 nand0: nand@ff100000 {
556 compatible = "arasan,nfc-v3p10";
558 reg = <0x0 0xff100000 0x0 0x1000>;
559 clock-names = "clk_sys", "clk_flash";
560 interrupt-parent = <&gic>;
561 interrupts = <0 14 4>;
562 #address-cells = <1>;
564 #stream-id-cells = <1>;
565 iommus = <&smmu 0x872>;
566 power-domains = <&zynqmp_firmware PD_NAND>;
569 gem0: ethernet@ff0b0000 {
570 compatible = "cdns,zynqmp-gem", "cdns,gem";
572 interrupt-parent = <&gic>;
573 interrupts = <0 57 4>, <0 57 4>;
574 reg = <0x0 0xff0b0000 0x0 0x1000>;
575 clock-names = "pclk", "hclk", "tx_clk";
576 #address-cells = <1>;
578 #stream-id-cells = <1>;
579 iommus = <&smmu 0x874>;
580 power-domains = <&zynqmp_firmware PD_ETH_0>;
583 gem1: ethernet@ff0c0000 {
584 compatible = "cdns,zynqmp-gem", "cdns,gem";
586 interrupt-parent = <&gic>;
587 interrupts = <0 59 4>, <0 59 4>;
588 reg = <0x0 0xff0c0000 0x0 0x1000>;
589 clock-names = "pclk", "hclk", "tx_clk";
590 #address-cells = <1>;
592 #stream-id-cells = <1>;
593 iommus = <&smmu 0x875>;
594 power-domains = <&zynqmp_firmware PD_ETH_1>;
597 gem2: ethernet@ff0d0000 {
598 compatible = "cdns,zynqmp-gem", "cdns,gem";
600 interrupt-parent = <&gic>;
601 interrupts = <0 61 4>, <0 61 4>;
602 reg = <0x0 0xff0d0000 0x0 0x1000>;
603 clock-names = "pclk", "hclk", "tx_clk";
604 #address-cells = <1>;
606 #stream-id-cells = <1>;
607 iommus = <&smmu 0x876>;
608 power-domains = <&zynqmp_firmware PD_ETH_2>;
611 gem3: ethernet@ff0e0000 {
612 compatible = "cdns,zynqmp-gem", "cdns,gem";
614 interrupt-parent = <&gic>;
615 interrupts = <0 63 4>, <0 63 4>;
616 reg = <0x0 0xff0e0000 0x0 0x1000>;
617 clock-names = "pclk", "hclk", "tx_clk";
618 #address-cells = <1>;
620 #stream-id-cells = <1>;
621 iommus = <&smmu 0x877>;
622 power-domains = <&zynqmp_firmware PD_ETH_3>;
625 gpio: gpio@ff0a0000 {
626 compatible = "xlnx,zynqmp-gpio-1.0";
630 interrupt-parent = <&gic>;
631 interrupts = <0 16 4>;
632 interrupt-controller;
633 #interrupt-cells = <2>;
634 reg = <0x0 0xff0a0000 0x0 0x1000>;
635 power-domains = <&zynqmp_firmware PD_GPIO>;
639 compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
641 interrupt-parent = <&gic>;
642 interrupts = <0 17 4>;
643 reg = <0x0 0xff020000 0x0 0x1000>;
644 #address-cells = <1>;
646 power-domains = <&zynqmp_firmware PD_I2C_0>;
650 compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
652 interrupt-parent = <&gic>;
653 interrupts = <0 18 4>;
654 reg = <0x0 0xff030000 0x0 0x1000>;
655 #address-cells = <1>;
657 power-domains = <&zynqmp_firmware PD_I2C_1>;
660 ocm: memory-controller@ff960000 {
661 compatible = "xlnx,zynqmp-ocmc-1.0";
662 reg = <0x0 0xff960000 0x0 0x1000>;
663 interrupt-parent = <&gic>;
664 interrupts = <0 10 4>;
667 pcie: pcie@fd0e0000 {
668 compatible = "xlnx,nwl-pcie-2.11";
670 #address-cells = <3>;
672 #interrupt-cells = <1>;
675 interrupt-parent = <&gic>;
676 interrupts = <0 118 4>,
679 <0 115 4>, /* MSI_1 [63...32] */
680 <0 114 4>; /* MSI_0 [31...0] */
681 interrupt-names = "misc", "dummy", "intx",
683 msi-parent = <&pcie>;
684 reg = <0x0 0xfd0e0000 0x0 0x1000>,
685 <0x0 0xfd480000 0x0 0x1000>,
686 <0x80 0x00000000 0x0 0x1000000>;
687 reg-names = "breg", "pcireg", "cfg";
688 ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */
689 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */
690 bus-range = <0x00 0xff>;
691 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
692 interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
693 <0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
694 <0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
695 <0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
696 power-domains = <&zynqmp_firmware PD_PCIE>;
697 pcie_intc: legacy-interrupt-controller {
698 interrupt-controller;
699 #address-cells = <0>;
700 #interrupt-cells = <1>;
706 compatible = "xlnx,zynqmp-qspi-1.0";
708 clock-names = "ref_clk", "pclk";
709 interrupts = <0 15 4>;
710 interrupt-parent = <&gic>;
712 reg = <0x0 0xff0f0000 0x0 0x1000>,
713 <0x0 0xc0000000 0x0 0x8000000>;
714 #address-cells = <1>;
716 #stream-id-cells = <1>;
717 iommus = <&smmu 0x873>;
718 power-domains = <&zynqmp_firmware PD_QSPI>;
722 compatible = "xlnx,zynqmp-rtc";
724 reg = <0x0 0xffa60000 0x0 0x100>;
725 interrupt-parent = <&gic>;
726 interrupts = <0 26 4>, <0 27 4>;
727 interrupt-names = "alarm", "sec";
728 calibration = <0x8000>;
731 serdes: zynqmp_phy@fd400000 {
732 compatible = "xlnx,zynqmp-psgtr";
734 reg = <0x0 0xfd400000 0x0 0x40000>,
735 <0x0 0xfd3d0000 0x0 0x1000>,
736 <0x0 0xff5e0000 0x0 0x1000>;
737 reg-names = "serdes", "siou", "lpd";
738 nvmem-cells = <&soc_revision>;
739 nvmem-cell-names = "soc_revision";
740 resets = <&zynqmp_reset ZYNQMP_RESET_SATA>,
741 <&zynqmp_reset ZYNQMP_RESET_USB0_CORERESET>,
742 <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>,
743 <&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>,
744 <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>,
745 <&zynqmp_reset ZYNQMP_RESET_USB0_APB>,
746 <&zynqmp_reset ZYNQMP_RESET_USB1_APB>,
747 <&zynqmp_reset ZYNQMP_RESET_DP>,
748 <&zynqmp_reset ZYNQMP_RESET_GEM0>,
749 <&zynqmp_reset ZYNQMP_RESET_GEM1>,
750 <&zynqmp_reset ZYNQMP_RESET_GEM2>,
751 <&zynqmp_reset ZYNQMP_RESET_GEM3>;
752 reset-names = "sata_rst", "usb0_crst", "usb1_crst",
753 "usb0_hibrst", "usb1_hibrst", "usb0_apbrst",
754 "usb1_apbrst", "dp_rst", "gem0_rst",
755 "gem1_rst", "gem2_rst", "gem3_rst";
770 sata: ahci@fd0c0000 {
771 compatible = "ceva,ahci-1v84";
773 reg = <0x0 0xfd0c0000 0x0 0x2000>;
774 interrupt-parent = <&gic>;
775 interrupts = <0 133 4>;
776 power-domains = <&zynqmp_firmware PD_SATA>;
777 #stream-id-cells = <4>;
778 iommus = <&smmu 0x4c0>, <&smmu 0x4c1>,
779 <&smmu 0x4c2>, <&smmu 0x4c3>;
783 sdhci0: mmc@ff160000 {
785 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
787 interrupt-parent = <&gic>;
788 interrupts = <0 48 4>;
789 reg = <0x0 0xff160000 0x0 0x1000>;
790 clock-names = "clk_xin", "clk_ahb";
791 xlnx,device_id = <0>;
792 #stream-id-cells = <1>;
793 iommus = <&smmu 0x870>;
794 power-domains = <&zynqmp_firmware PD_SD_0>;
795 nvmem-cells = <&soc_revision>;
796 nvmem-cell-names = "soc_revision";
799 sdhci1: mmc@ff170000 {
801 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
803 interrupt-parent = <&gic>;
804 interrupts = <0 49 4>;
805 reg = <0x0 0xff170000 0x0 0x1000>;
806 clock-names = "clk_xin", "clk_ahb";
807 xlnx,device_id = <1>;
808 #stream-id-cells = <1>;
809 iommus = <&smmu 0x871>;
810 power-domains = <&zynqmp_firmware PD_SD_1>;
811 nvmem-cells = <&soc_revision>;
812 nvmem-cell-names = "soc_revision";
815 pinctrl0: pinctrl@ff180000 {
816 compatible = "xlnx,pinctrl-zynqmp";
818 reg = <0x0 0xff180000 0x0 0x1000>;
821 smmu: smmu@fd800000 {
822 compatible = "arm,mmu-500";
823 reg = <0x0 0xfd800000 0x0 0x20000>;
826 #global-interrupts = <1>;
827 interrupt-parent = <&gic>;
828 interrupts = <0 155 4>,
829 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
830 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
831 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
832 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;
836 compatible = "cdns,spi-r1p6";
838 interrupt-parent = <&gic>;
839 interrupts = <0 19 4>;
840 reg = <0x0 0xff040000 0x0 0x1000>;
841 clock-names = "ref_clk", "pclk";
842 #address-cells = <1>;
844 power-domains = <&zynqmp_firmware PD_SPI_0>;
848 compatible = "cdns,spi-r1p6";
850 interrupt-parent = <&gic>;
851 interrupts = <0 20 4>;
852 reg = <0x0 0xff050000 0x0 0x1000>;
853 clock-names = "ref_clk", "pclk";
854 #address-cells = <1>;
856 power-domains = <&zynqmp_firmware PD_SPI_1>;
859 ttc0: timer@ff110000 {
860 compatible = "cdns,ttc";
862 interrupt-parent = <&gic>;
863 interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
864 reg = <0x0 0xff110000 0x0 0x1000>;
866 power-domains = <&zynqmp_firmware PD_TTC_0>;
869 ttc1: timer@ff120000 {
870 compatible = "cdns,ttc";
872 interrupt-parent = <&gic>;
873 interrupts = <0 39 4>, <0 40 4>, <0 41 4>;
874 reg = <0x0 0xff120000 0x0 0x1000>;
876 power-domains = <&zynqmp_firmware PD_TTC_1>;
879 ttc2: timer@ff130000 {
880 compatible = "cdns,ttc";
882 interrupt-parent = <&gic>;
883 interrupts = <0 42 4>, <0 43 4>, <0 44 4>;
884 reg = <0x0 0xff130000 0x0 0x1000>;
886 power-domains = <&zynqmp_firmware PD_TTC_2>;
889 ttc3: timer@ff140000 {
890 compatible = "cdns,ttc";
892 interrupt-parent = <&gic>;
893 interrupts = <0 45 4>, <0 46 4>, <0 47 4>;
894 reg = <0x0 0xff140000 0x0 0x1000>;
896 power-domains = <&zynqmp_firmware PD_TTC_3>;
899 uart0: serial@ff000000 {
901 compatible = "cdns,uart-r1p12", "xlnx,xuartps";
903 interrupt-parent = <&gic>;
904 interrupts = <0 21 4>;
905 reg = <0x0 0xff000000 0x0 0x1000>;
906 clock-names = "uart_clk", "pclk";
907 power-domains = <&zynqmp_firmware PD_UART_0>;
910 uart1: serial@ff010000 {
912 compatible = "cdns,uart-r1p12", "xlnx,xuartps";
914 interrupt-parent = <&gic>;
915 interrupts = <0 22 4>;
916 reg = <0x0 0xff010000 0x0 0x1000>;
917 clock-names = "uart_clk", "pclk";
918 power-domains = <&zynqmp_firmware PD_UART_1>;
921 usb0: usb0@ff9d0000 {
922 #address-cells = <2>;
925 compatible = "xlnx,zynqmp-dwc3";
926 reg = <0x0 0xff9d0000 0x0 0x100>;
927 clock-names = "bus_clk", "ref_clk";
928 power-domains = <&zynqmp_firmware PD_USB_0>;
930 nvmem-cells = <&soc_revision>;
931 nvmem-cell-names = "soc_revision";
933 dwc3_0: dwc3@fe200000 {
934 compatible = "snps,dwc3";
936 reg = <0x0 0xfe200000 0x0 0x40000>;
937 interrupt-parent = <&gic>;
938 interrupts = <0 65 4>, <0 69 4>;
939 #stream-id-cells = <1>;
940 iommus = <&smmu 0x860>;
941 snps,quirk-frame-length-adjustment = <0x20>;
947 usb1: usb1@ff9e0000 {
948 #address-cells = <2>;
951 compatible = "xlnx,zynqmp-dwc3";
952 reg = <0x0 0xff9e0000 0x0 0x100>;
953 clock-names = "bus_clk", "ref_clk";
954 power-domains = <&zynqmp_firmware PD_USB_1>;
956 nvmem-cells = <&soc_revision>;
957 nvmem-cell-names = "soc_revision";
959 dwc3_1: dwc3@fe300000 {
960 compatible = "snps,dwc3";
962 reg = <0x0 0xfe300000 0x0 0x40000>;
963 interrupt-parent = <&gic>;
964 interrupts = <0 70 4>, <0 74 4>;
965 #stream-id-cells = <1>;
966 iommus = <&smmu 0x861>;
967 snps,quirk-frame-length-adjustment = <0x20>;
973 watchdog0: watchdog@fd4d0000 {
974 compatible = "cdns,wdt-r1p2";
976 interrupt-parent = <&gic>;
977 interrupts = <0 113 1>;
978 reg = <0x0 0xfd4d0000 0x0 0x1000>;
983 lpd_watchdog: watchdog@ff150000 {
984 compatible = "cdns,wdt-r1p2";
986 interrupt-parent = <&gic>;
987 interrupts = <0 52 1>;
988 reg = <0x0 0xff150000 0x0 0x1000>;
992 xilinx_ams: ams@ffa50000 {
993 compatible = "xlnx,zynqmp-ams";
995 interrupt-parent = <&gic>;
996 interrupts = <0 56 4>;
997 interrupt-names = "ams-irq";
998 reg = <0x0 0xffa50000 0x0 0x800>;
999 reg-names = "ams-base";
1000 #address-cells = <2>;
1002 #io-channel-cells = <1>;
1005 ams_ps: ams_ps@ffa50800 {
1006 compatible = "xlnx,zynqmp-ams-ps";
1007 status = "disabled";
1008 reg = <0x0 0xffa50800 0x0 0x400>;
1011 ams_pl: ams_pl@ffa50c00 {
1012 compatible = "xlnx,zynqmp-ams-pl";
1013 status = "disabled";
1014 reg = <0x0 0xffa50c00 0x0 0x400>;
1018 xlnx_dp: dp@fd4a0000 {
1019 compatible = "xlnx,v-dp";
1020 status = "disabled";
1021 reg = <0x0 0xfd4a0000 0x0 0x1000>;
1022 interrupts = <0 119 4>;
1023 interrupt-parent = <&gic>;
1024 clock-names = "aclk", "aud_clk";
1025 xlnx,dp-version = "v1.2";
1026 xlnx,max-lanes = <2>;
1027 xlnx,max-link-rate = <540000>;
1028 xlnx,max-bpc = <16>;
1030 xlnx,colormetry = "rgb";
1032 xlnx,audio-chan = <2>;
1033 xlnx,dp-sub = <&xlnx_dp_sub>;
1034 xlnx,max-pclock-frequency = <300000>;
1037 xlnx_dp_sub: dp_sub@fd4aa000 {
1038 compatible = "xlnx,dp-sub";
1039 status = "disabled";
1040 reg = <0x0 0xfd4aa000 0x0 0x1000>,
1041 <0x0 0xfd4ab000 0x0 0x1000>,
1042 <0x0 0xfd4ac000 0x0 0x1000>;
1043 reg-names = "blend", "av_buf", "aud";
1044 xlnx,output-fmt = "rgb";
1045 xlnx,vid-fmt = "yuyv";
1046 xlnx,gfx-fmt = "rgb565";
1049 xlnx_dpdma: dma@fd4c0000 {
1050 compatible = "xlnx,dpdma";
1051 status = "disabled";
1052 reg = <0x0 0xfd4c0000 0x0 0x1000>;
1053 interrupts = <0 122 4>;
1054 interrupt-parent = <&gic>;
1055 clock-names = "axi_clk";
1056 power-domains = <&zynqmp_firmware PD_DP>;
1060 compatible = "xlnx,video0";
1063 compatible = "xlnx,video1";
1066 compatible = "xlnx,video2";
1068 dma-graphicschannel {
1069 compatible = "xlnx,graphics";
1072 compatible = "xlnx,audio0";
1075 compatible = "xlnx,audio1";