arch/arm/dts/zynqmp.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * dts file for Xilinx ZynqMP
   4  *
   5  * (C) Copyright 2014 - 2020, Xilinx, Inc.
   6  *
   7  * Michal Simek <michal.simek@xilinx.com>
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  */
  14
  15 #include <dt-bindings/power/xlnx-zynqmp-power.h>
  16 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
  17
  18 / {
  19         compatible = "xlnx,zynqmp";
  20         #address-cells = <2>;
  21         #size-cells = <2>;
  22
  23         cpus {
  24                 #address-cells = <1>;
  25                 #size-cells = <0>;
  26
  27                 cpu0: cpu@0 {
  28                         compatible = "arm,cortex-a53";
  29                         device_type = "cpu";
  30                         enable-method = "psci";
  31                         operating-points-v2 = <&cpu_opp_table>;
  32                         reg = <0x0>;
  33                         cpu-idle-states = <&CPU_SLEEP_0>;
  34                 };
  35
  36                 cpu1: cpu@1 {
  37                         compatible = "arm,cortex-a53";
  38                         device_type = "cpu";
  39                         enable-method = "psci";
  40                         reg = <0x1>;
  41                         operating-points-v2 = <&cpu_opp_table>;
  42                         cpu-idle-states = <&CPU_SLEEP_0>;
  43                 };
  44
  45                 cpu2: cpu@2 {
  46                         compatible = "arm,cortex-a53";
  47                         device_type = "cpu";
  48                         enable-method = "psci";
  49                         reg = <0x2>;
  50                         operating-points-v2 = <&cpu_opp_table>;
  51                         cpu-idle-states = <&CPU_SLEEP_0>;
  52                 };
  53
  54                 cpu3: cpu@3 {
  55                         compatible = "arm,cortex-a53";
  56                         device_type = "cpu";
  57                         enable-method = "psci";
  58                         reg = <0x3>;
  59                         operating-points-v2 = <&cpu_opp_table>;
  60                         cpu-idle-states = <&CPU_SLEEP_0>;
  61                 };
  62
  63                 idle-states {
  64                         entry-method = "psci";
  65
  66                         CPU_SLEEP_0: cpu-sleep-0 {
  67                                 compatible = "arm,idle-state";
  68                                 arm,psci-suspend-param = <0x40000000>;
  69                                 local-timer-stop;
  70                                 entry-latency-us = <300>;
  71                                 exit-latency-us = <600>;
  72                                 min-residency-us = <10000>;
  73                         };
  74                 };
  75         };
  76
  77         cpu_opp_table: cpu-opp-table {
  78                 compatible = "operating-points-v2";
  79                 opp-shared;
  80                 opp00 {
  81                         opp-hz = /bits/ 64 <1199999988>;
  82                         opp-microvolt = <1000000>;
  83                         clock-latency-ns = <500000>;
  84                 };
  85                 opp01 {
  86                         opp-hz = /bits/ 64 <599999994>;
  87                         opp-microvolt = <1000000>;
  88                         clock-latency-ns = <500000>;
  89                 };
  90                 opp02 {
  91                         opp-hz = /bits/ 64 <399999996>;
  92                         opp-microvolt = <1000000>;
  93                         clock-latency-ns = <500000>;
  94                 };
  95                 opp03 {
  96                         opp-hz = /bits/ 64 <299999997>;
  97                         opp-microvolt = <1000000>;
  98                         clock-latency-ns = <500000>;
  99                 };
 100         };
 101
 102         zynqmp_ipi {
 103                 u-boot,dm-pre-reloc;
 104                 compatible = "xlnx,zynqmp-ipi-mailbox";
 105                 interrupt-parent = <&gic>;
 106                 interrupts = <0 35 4>;
 107                 xlnx,ipi-id = <0>;
 108                 #address-cells = <2>;
 109                 #size-cells = <2>;
 110                 ranges;
 111
 112                 ipi_mailbox_pmu1: mailbox@ff990400 {
 113                         u-boot,dm-pre-reloc;
 114                         reg = <0x0 0xff9905c0 0x0 0x20>,
 115                               <0x0 0xff9905e0 0x0 0x20>,
 116                               <0x0 0xff990e80 0x0 0x20>,
 117                               <0x0 0xff990ea0 0x0 0x20>;
 118                         reg-names = "local_request_region", "local_response_region",
 119                                     "remote_request_region", "remote_response_region";
 120                         #mbox-cells = <1>;
 121                         xlnx,ipi-id = <4>;
 122                 };
 123         };
 124
 125         dcc: dcc {
 126                 compatible = "arm,dcc";
 127                 status = "disabled";
 128                 u-boot,dm-pre-reloc;
 129         };
 130
 131         pmu {
 132                 compatible = "arm,armv8-pmuv3";
 133                 interrupt-parent = <&gic>;
 134                 interrupts = <0 143 4>,
 135                              <0 144 4>,
 136                              <0 145 4>,
 137                              <0 146 4>;
 138         };
 139
 140         psci {
 141                 compatible = "arm,psci-0.2";
 142                 method = "smc";
 143         };
 144
 145         firmware {
 146                 zynqmp_firmware: zynqmp-firmware {
 147                         compatible = "xlnx,zynqmp-firmware";
 148                         method = "smc";
 149                         #power-domain-cells = <0x1>;
 150                         u-boot,dm-pre-reloc;
 151
 152                         zynqmp_pcap: pcap {
 153                                 compatible = "xlnx,zynqmp-pcap-fpga";
 154                                 clock-names = "ref_clk";
 155                         };
 156
 157                         zynqmp_power: zynqmp-power {
 158                                 u-boot,dm-pre-reloc;
 159                                 compatible = "xlnx,zynqmp-power";
 160                                 interrupt-parent = <&gic>;
 161                                 interrupts = <0 35 4>;
 162                                 mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>;
 163                                 mbox-names = "tx", "rx";
 164                         };
 165
 166                         zynqmp_reset: reset-controller {
 167                                 compatible = "xlnx,zynqmp-reset";
 168                                 #reset-cells = <1>;
 169                         };
 170
 171                         pinctrl0: pinctrl {
 172                                 compatible = "xlnx,zynqmp-pinctrl";
 173                                 status = "disabled";
 174                         };
 175                 };
 176         };
 177
 178         timer {
 179                 compatible = "arm,armv8-timer";
 180                 interrupt-parent = <&gic>;
 181                 interrupts = <1 13 0xf08>,
 182                              <1 14 0xf08>,
 183                              <1 11 0xf08>,
 184                              <1 10 0xf08>;
 185         };
 186
 187         edac {
 188                 compatible = "arm,cortex-a53-edac";
 189         };
 190
 191         fpga_full: fpga-full {
 192                 compatible = "fpga-region";
 193                 fpga-mgr = <&zynqmp_pcap>;
 194                 #address-cells = <2>;
 195                 #size-cells = <2>;
 196                 ranges;
 197         };
 198
 199         nvmem_firmware {
 200                 compatible = "xlnx,zynqmp-nvmem-fw";
 201                 #address-cells = <1>;
 202                 #size-cells = <1>;
 203
 204                 soc_revision: soc_revision@0 {
 205                         reg = <0x0 0x4>;
 206                 };
 207         };
 208
 209         amba_apu: amba-apu@0 {
 210                 compatible = "simple-bus";
 211                 #address-cells = <2>;
 212                 #size-cells = <1>;
 213                 ranges = <0 0 0 0 0xffffffff>;
 214
 215                 gic: interrupt-controller@f9010000 {
 216                         compatible = "arm,gic-400";
 217                         #interrupt-cells = <3>;
 218                         reg = <0x0 0xf9010000 0x10000>,
 219                               <0x0 0xf9020000 0x20000>,
 220                               <0x0 0xf9040000 0x20000>,
 221                               <0x0 0xf9060000 0x20000>;
 222                         interrupt-controller;
 223                         interrupt-parent = <&gic>;
 224                         interrupts = <1 9 0xf04>;
 225                 };
 226         };
 227
 228         amba: amba {
 229                 compatible = "simple-bus";
 230                 u-boot,dm-pre-reloc;
 231                 #address-cells = <2>;
 232                 #size-cells = <2>;
 233                 ranges;
 234
 235                 can0: can@ff060000 {
 236                         compatible = "xlnx,zynq-can-1.0";
 237                         status = "disabled";
 238                         clock-names = "can_clk", "pclk";
 239                         reg = <0x0 0xff060000 0x0 0x1000>;
 240                         interrupts = <0 23 4>;
 241                         interrupt-parent = <&gic>;
 242                         tx-fifo-depth = <0x40>;
 243                         rx-fifo-depth = <0x40>;
 244                         power-domains = <&zynqmp_firmware PD_CAN_0>;
 245                 };
 246
 247                 can1: can@ff070000 {
 248                         compatible = "xlnx,zynq-can-1.0";
 249                         status = "disabled";
 250                         clock-names = "can_clk", "pclk";
 251                         reg = <0x0 0xff070000 0x0 0x1000>;
 252                         interrupts = <0 24 4>;
 253                         interrupt-parent = <&gic>;
 254                         tx-fifo-depth = <0x40>;
 255                         rx-fifo-depth = <0x40>;
 256                         power-domains = <&zynqmp_firmware PD_CAN_1>;
 257                 };
 258
 259                 cci: cci@fd6e0000 {
 260                         compatible = "arm,cci-400";
 261                         reg = <0x0 0xfd6e0000 0x0 0x9000>;
 262                         ranges = <0x0 0x0 0xfd6e0000 0x10000>;
 263                         #address-cells = <1>;
 264                         #size-cells = <1>;
 265
 266                         pmu@9000 {
 267                                 compatible = "arm,cci-400-pmu,r1";
 268                                 reg = <0x9000 0x5000>;
 269                                 interrupt-parent = <&gic>;
 270                                 interrupts = <0 123 4>,
 271                                              <0 123 4>,
 272                                              <0 123 4>,
 273                                              <0 123 4>,
 274                                              <0 123 4>;
 275                         };
 276                 };
 277
 278                 /* GDMA */
 279                 fpd_dma_chan1: dma@fd500000 {
 280                         status = "disabled";
 281                         compatible = "xlnx,zynqmp-dma-1.0";
 282                         reg = <0x0 0xfd500000 0x0 0x1000>;
 283                         interrupt-parent = <&gic>;
 284                         interrupts = <0 124 4>;
 285                         clock-names = "clk_main", "clk_apb";
 286                         xlnx,bus-width = <128>;
 287                         #stream-id-cells = <1>;
 288                         iommus = <&smmu 0x14e8>;
 289                         power-domains = <&zynqmp_firmware PD_GDMA>;
 290                 };
 291
 292                 fpd_dma_chan2: dma@fd510000 {
 293                         status = "disabled";
 294                         compatible = "xlnx,zynqmp-dma-1.0";
 295                         reg = <0x0 0xfd510000 0x0 0x1000>;
 296                         interrupt-parent = <&gic>;
 297                         interrupts = <0 125 4>;
 298                         clock-names = "clk_main", "clk_apb";
 299                         xlnx,bus-width = <128>;
 300                         #stream-id-cells = <1>;
 301                         iommus = <&smmu 0x14e9>;
 302                         power-domains = <&zynqmp_firmware PD_GDMA>;
 303                 };
 304
 305                 fpd_dma_chan3: dma@fd520000 {
 306                         status = "disabled";
 307                         compatible = "xlnx,zynqmp-dma-1.0";
 308                         reg = <0x0 0xfd520000 0x0 0x1000>;
 309                         interrupt-parent = <&gic>;
 310                         interrupts = <0 126 4>;
 311                         clock-names = "clk_main", "clk_apb";
 312                         xlnx,bus-width = <128>;
 313                         #stream-id-cells = <1>;
 314                         iommus = <&smmu 0x14ea>;
 315                         power-domains = <&zynqmp_firmware PD_GDMA>;
 316                 };
 317
 318                 fpd_dma_chan4: dma@fd530000 {
 319                         status = "disabled";
 320                         compatible = "xlnx,zynqmp-dma-1.0";
 321                         reg = <0x0 0xfd530000 0x0 0x1000>;
 322                         interrupt-parent = <&gic>;
 323                         interrupts = <0 127 4>;
 324                         clock-names = "clk_main", "clk_apb";
 325                         xlnx,bus-width = <128>;
 326                         #stream-id-cells = <1>;
 327                         iommus = <&smmu 0x14eb>;
 328                         power-domains = <&zynqmp_firmware PD_GDMA>;
 329                 };
 330
 331                 fpd_dma_chan5: dma@fd540000 {
 332                         status = "disabled";
 333                         compatible = "xlnx,zynqmp-dma-1.0";
 334                         reg = <0x0 0xfd540000 0x0 0x1000>;
 335                         interrupt-parent = <&gic>;
 336                         interrupts = <0 128 4>;
 337                         clock-names = "clk_main", "clk_apb";
 338                         xlnx,bus-width = <128>;
 339                         #stream-id-cells = <1>;
 340                         iommus = <&smmu 0x14ec>;
 341                         power-domains = <&zynqmp_firmware PD_GDMA>;
 342                 };
 343
 344                 fpd_dma_chan6: dma@fd550000 {
 345                         status = "disabled";
 346                         compatible = "xlnx,zynqmp-dma-1.0";
 347                         reg = <0x0 0xfd550000 0x0 0x1000>;
 348                         interrupt-parent = <&gic>;
 349                         interrupts = <0 129 4>;
 350                         clock-names = "clk_main", "clk_apb";
 351                         xlnx,bus-width = <128>;
 352                         #stream-id-cells = <1>;
 353                         iommus = <&smmu 0x14ed>;
 354                         power-domains = <&zynqmp_firmware PD_GDMA>;
 355                 };
 356
 357                 fpd_dma_chan7: dma@fd560000 {
 358                         status = "disabled";
 359                         compatible = "xlnx,zynqmp-dma-1.0";
 360                         reg = <0x0 0xfd560000 0x0 0x1000>;
 361                         interrupt-parent = <&gic>;
 362                         interrupts = <0 130 4>;
 363                         clock-names = "clk_main", "clk_apb";
 364                         xlnx,bus-width = <128>;
 365                         #stream-id-cells = <1>;
 366                         iommus = <&smmu 0x14ee>;
 367                         power-domains = <&zynqmp_firmware PD_GDMA>;
 368                 };
 369
 370                 fpd_dma_chan8: dma@fd570000 {
 371                         status = "disabled";
 372                         compatible = "xlnx,zynqmp-dma-1.0";
 373                         reg = <0x0 0xfd570000 0x0 0x1000>;
 374                         interrupt-parent = <&gic>;
 375                         interrupts = <0 131 4>;
 376                         clock-names = "clk_main", "clk_apb";
 377                         xlnx,bus-width = <128>;
 378                         #stream-id-cells = <1>;
 379                         iommus = <&smmu 0x14ef>;
 380                         power-domains = <&zynqmp_firmware PD_GDMA>;
 381                 };
 382
 383                 gpu: gpu@fd4b0000 {
 384                         status = "disabled";
 385                         compatible = "arm,mali-400", "arm,mali-utgard";
 386                         reg = <0x0 0xfd4b0000 0x0 0x10000>;
 387                         interrupt-parent = <&gic>;
 388                         interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>;
 389                         interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1";
 390                         clock-names = "gpu", "gpu_pp0", "gpu_pp1";
 391                         power-domains = <&zynqmp_firmware PD_GPU>;
 392                 };
 393
 394                 /* LPDDMA default allows only secured access. inorder to enable
 395                  * These dma channels, Users should ensure that these dma
 396                  * Channels are allowed for non secure access.
 397                  */
 398                 lpd_dma_chan1: dma@ffa80000 {
 399                         status = "disabled";
 400                         compatible = "xlnx,zynqmp-dma-1.0";
 401                         reg = <0x0 0xffa80000 0x0 0x1000>;
 402                         interrupt-parent = <&gic>;
 403                         interrupts = <0 77 4>;
 404                         clock-names = "clk_main", "clk_apb";
 405                         xlnx,bus-width = <64>;
 406                         #stream-id-cells = <1>;
 407                         iommus = <&smmu 0x868>;
 408                         power-domains = <&zynqmp_firmware PD_ADMA>;
 409                 };
 410
 411                 lpd_dma_chan2: dma@ffa90000 {
 412                         status = "disabled";
 413                         compatible = "xlnx,zynqmp-dma-1.0";
 414                         reg = <0x0 0xffa90000 0x0 0x1000>;
 415                         interrupt-parent = <&gic>;
 416                         interrupts = <0 78 4>;
 417                         clock-names = "clk_main", "clk_apb";
 418                         xlnx,bus-width = <64>;
 419                         #stream-id-cells = <1>;
 420                         iommus = <&smmu 0x869>;
 421                         power-domains = <&zynqmp_firmware PD_ADMA>;
 422                 };
 423
 424                 lpd_dma_chan3: dma@ffaa0000 {
 425                         status = "disabled";
 426                         compatible = "xlnx,zynqmp-dma-1.0";
 427                         reg = <0x0 0xffaa0000 0x0 0x1000>;
 428                         interrupt-parent = <&gic>;
 429                         interrupts = <0 79 4>;
 430                         clock-names = "clk_main", "clk_apb";
 431                         xlnx,bus-width = <64>;
 432                         #stream-id-cells = <1>;
 433                         iommus = <&smmu 0x86a>;
 434                         power-domains = <&zynqmp_firmware PD_ADMA>;
 435                 };
 436
 437                 lpd_dma_chan4: dma@ffab0000 {
 438                         status = "disabled";
 439                         compatible = "xlnx,zynqmp-dma-1.0";
 440                         reg = <0x0 0xffab0000 0x0 0x1000>;
 441                         interrupt-parent = <&gic>;
 442                         interrupts = <0 80 4>;
 443                         clock-names = "clk_main", "clk_apb";
 444                         xlnx,bus-width = <64>;
 445                         #stream-id-cells = <1>;
 446                         iommus = <&smmu 0x86b>;
 447                         power-domains = <&zynqmp_firmware PD_ADMA>;
 448                 };
 449
 450                 lpd_dma_chan5: dma@ffac0000 {
 451                         status = "disabled";
 452                         compatible = "xlnx,zynqmp-dma-1.0";
 453                         reg = <0x0 0xffac0000 0x0 0x1000>;
 454                         interrupt-parent = <&gic>;
 455                         interrupts = <0 81 4>;
 456                         clock-names = "clk_main", "clk_apb";
 457                         xlnx,bus-width = <64>;
 458                         #stream-id-cells = <1>;
 459                         iommus = <&smmu 0x86c>;
 460                         power-domains = <&zynqmp_firmware PD_ADMA>;
 461                 };
 462
 463                 lpd_dma_chan6: dma@ffad0000 {
 464                         status = "disabled";
 465                         compatible = "xlnx,zynqmp-dma-1.0";
 466                         reg = <0x0 0xffad0000 0x0 0x1000>;
 467                         interrupt-parent = <&gic>;
 468                         interrupts = <0 82 4>;
 469                         clock-names = "clk_main", "clk_apb";
 470                         xlnx,bus-width = <64>;
 471                         #stream-id-cells = <1>;
 472                         iommus = <&smmu 0x86d>;
 473                         power-domains = <&zynqmp_firmware PD_ADMA>;
 474                 };
 475
 476                 lpd_dma_chan7: dma@ffae0000 {
 477                         status = "disabled";
 478                         compatible = "xlnx,zynqmp-dma-1.0";
 479                         reg = <0x0 0xffae0000 0x0 0x1000>;
 480                         interrupt-parent = <&gic>;
 481                         interrupts = <0 83 4>;
 482                         clock-names = "clk_main", "clk_apb";
 483                         xlnx,bus-width = <64>;
 484                         #stream-id-cells = <1>;
 485                         iommus = <&smmu 0x86e>;
 486                         power-domains = <&zynqmp_firmware PD_ADMA>;
 487                 };
 488
 489                 lpd_dma_chan8: dma@ffaf0000 {
 490                         status = "disabled";
 491                         compatible = "xlnx,zynqmp-dma-1.0";
 492                         reg = <0x0 0xffaf0000 0x0 0x1000>;
 493                         interrupt-parent = <&gic>;
 494                         interrupts = <0 84 4>;
 495                         clock-names = "clk_main", "clk_apb";
 496                         xlnx,bus-width = <64>;
 497                         #stream-id-cells = <1>;
 498                         iommus = <&smmu 0x86f>;
 499                         power-domains = <&zynqmp_firmware PD_ADMA>;
 500                 };
 501
 502                 mc: memory-controller@fd070000 {
 503                         compatible = "xlnx,zynqmp-ddrc-2.40a";
 504                         reg = <0x0 0xfd070000 0x0 0x30000>;
 505                         interrupt-parent = <&gic>;
 506                         interrupts = <0 112 4>;
 507                 };
 508
 509                 nand0: nand@ff100000 {
 510                         compatible = "arasan,nfc-v3p10";
 511                         status = "disabled";
 512                         reg = <0x0 0xff100000 0x0 0x1000>;
 513                         clock-names = "clk_sys", "clk_flash";
 514                         interrupt-parent = <&gic>;
 515                         interrupts = <0 14 4>;
 516                         #address-cells = <1>;
 517                         #size-cells = <0>;
 518                         #stream-id-cells = <1>;
 519                         iommus = <&smmu 0x872>;
 520                         power-domains = <&zynqmp_firmware PD_NAND>;
 521                 };
 522
 523                 gem0: ethernet@ff0b0000 {
 524                         compatible = "cdns,zynqmp-gem", "cdns,gem";
 525                         status = "disabled";
 526                         interrupt-parent = <&gic>;
 527                         interrupts = <0 57 4>, <0 57 4>;
 528                         reg = <0x0 0xff0b0000 0x0 0x1000>;
 529                         clock-names = "pclk", "hclk", "tx_clk";
 530                         #address-cells = <1>;
 531                         #size-cells = <0>;
 532                         #stream-id-cells = <1>;
 533                         iommus = <&smmu 0x874>;
 534                         power-domains = <&zynqmp_firmware PD_ETH_0>;
 535                 };
 536
 537                 gem1: ethernet@ff0c0000 {
 538                         compatible = "cdns,zynqmp-gem", "cdns,gem";
 539                         status = "disabled";
 540                         interrupt-parent = <&gic>;
 541                         interrupts = <0 59 4>, <0 59 4>;
 542                         reg = <0x0 0xff0c0000 0x0 0x1000>;
 543                         clock-names = "pclk", "hclk", "tx_clk";
 544                         #address-cells = <1>;
 545                         #size-cells = <0>;
 546                         #stream-id-cells = <1>;
 547                         iommus = <&smmu 0x875>;
 548                         power-domains = <&zynqmp_firmware PD_ETH_1>;
 549                 };
 550
 551                 gem2: ethernet@ff0d0000 {
 552                         compatible = "cdns,zynqmp-gem", "cdns,gem";
 553                         status = "disabled";
 554                         interrupt-parent = <&gic>;
 555                         interrupts = <0 61 4>, <0 61 4>;
 556                         reg = <0x0 0xff0d0000 0x0 0x1000>;
 557                         clock-names = "pclk", "hclk", "tx_clk";
 558                         #address-cells = <1>;
 559                         #size-cells = <0>;
 560                         #stream-id-cells = <1>;
 561                         iommus = <&smmu 0x876>;
 562                         power-domains = <&zynqmp_firmware PD_ETH_2>;
 563                 };
 564
 565                 gem3: ethernet@ff0e0000 {
 566                         compatible = "cdns,zynqmp-gem", "cdns,gem";
 567                         status = "disabled";
 568                         interrupt-parent = <&gic>;
 569                         interrupts = <0 63 4>, <0 63 4>;
 570                         reg = <0x0 0xff0e0000 0x0 0x1000>;
 571                         clock-names = "pclk", "hclk", "tx_clk";
 572                         #address-cells = <1>;
 573                         #size-cells = <0>;
 574                         #stream-id-cells = <1>;
 575                         iommus = <&smmu 0x877>;
 576                         power-domains = <&zynqmp_firmware PD_ETH_3>;
 577                 };
 578
 579                 gpio: gpio@ff0a0000 {
 580                         compatible = "xlnx,zynqmp-gpio-1.0";
 581                         status = "disabled";
 582                         #gpio-cells = <0x2>;
 583                         gpio-controller;
 584                         interrupt-parent = <&gic>;
 585                         interrupts = <0 16 4>;
 586                         interrupt-controller;
 587                         #interrupt-cells = <2>;
 588                         reg = <0x0 0xff0a0000 0x0 0x1000>;
 589                         power-domains = <&zynqmp_firmware PD_GPIO>;
 590                 };
 591
 592                 i2c0: i2c@ff020000 {
 593                         compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
 594                         status = "disabled";
 595                         interrupt-parent = <&gic>;
 596                         interrupts = <0 17 4>;
 597                         reg = <0x0 0xff020000 0x0 0x1000>;
 598                         #address-cells = <1>;
 599                         #size-cells = <0>;
 600                         power-domains = <&zynqmp_firmware PD_I2C_0>;
 601                 };
 602
 603                 i2c1: i2c@ff030000 {
 604                         compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
 605                         status = "disabled";
 606                         interrupt-parent = <&gic>;
 607                         interrupts = <0 18 4>;
 608                         reg = <0x0 0xff030000 0x0 0x1000>;
 609                         #address-cells = <1>;
 610                         #size-cells = <0>;
 611                         power-domains = <&zynqmp_firmware PD_I2C_1>;
 612                 };
 613
 614                 ocm: memory-controller@ff960000 {
 615                         compatible = "xlnx,zynqmp-ocmc-1.0";
 616                         reg = <0x0 0xff960000 0x0 0x1000>;
 617                         interrupt-parent = <&gic>;
 618                         interrupts = <0 10 4>;
 619                 };
 620
 621                 pcie: pcie@fd0e0000 {
 622                         compatible = "xlnx,nwl-pcie-2.11";
 623                         status = "disabled";
 624                         #address-cells = <3>;
 625                         #size-cells = <2>;
 626                         #interrupt-cells = <1>;
 627                         msi-controller;
 628                         device_type = "pci";
 629                         interrupt-parent = <&gic>;
 630                         interrupts = <0 118 4>,
 631                                      <0 117 4>,
 632                                      <0 116 4>,
 633                                      <0 115 4>, /* MSI_1 [63...32] */
 634                                      <0 114 4>; /* MSI_0 [31...0] */
 635                         interrupt-names = "misc", "dummy", "intx",
 636                                           "msi1", "msi0";
 637                         msi-parent = <&pcie>;
 638                         reg = <0x0 0xfd0e0000 0x0 0x1000>,
 639                               <0x0 0xfd480000 0x0 0x1000>,
 640                               <0x80 0x00000000 0x0 0x1000000>;
 641                         reg-names = "breg", "pcireg", "cfg";
 642                         ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000  /* non-prefetchable memory */
 643                                   0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */
 644                         bus-range = <0x00 0xff>;
 645                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 646                         interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
 647                                         <0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
 648                                         <0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
 649                                         <0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
 650                         power-domains = <&zynqmp_firmware PD_PCIE>;
 651                         pcie_intc: legacy-interrupt-controller {
 652                                 interrupt-controller;
 653                                 #address-cells = <0>;
 654                                 #interrupt-cells = <1>;
 655                         };
 656                 };
 657
 658                 qspi: spi@ff0f0000 {
 659                         u-boot,dm-pre-reloc;
 660                         compatible = "xlnx,zynqmp-qspi-1.0";
 661                         status = "disabled";
 662                         clock-names = "ref_clk", "pclk";
 663                         interrupts = <0 15 4>;
 664                         interrupt-parent = <&gic>;
 665                         num-cs = <1>;
 666                         reg = <0x0 0xff0f0000 0x0 0x1000>,
 667                               <0x0 0xc0000000 0x0 0x8000000>;
 668                         #address-cells = <1>;
 669                         #size-cells = <0>;
 670                         #stream-id-cells = <1>;
 671                         iommus = <&smmu 0x873>;
 672                         power-domains = <&zynqmp_firmware PD_QSPI>;
 673                 };
 674
 675                 rtc: rtc@ffa60000 {
 676                         compatible = "xlnx,zynqmp-rtc";
 677                         status = "disabled";
 678                         reg = <0x0 0xffa60000 0x0 0x100>;
 679                         interrupt-parent = <&gic>;
 680                         interrupts = <0 26 4>, <0 27 4>;
 681                         interrupt-names = "alarm", "sec";
 682                         calibration = <0x8000>;
 683                 };
 684
 685                 serdes: zynqmp_phy@fd400000 {
 686                         compatible = "xlnx,zynqmp-psgtr";
 687                         status = "disabled";
 688                         reg = <0x0 0xfd400000 0x0 0x40000>,
 689                               <0x0 0xfd3d0000 0x0 0x1000>,
 690                               <0x0 0xff5e0000 0x0 0x1000>;
 691                         reg-names = "serdes", "siou", "lpd";
 692                         nvmem-cells = <&soc_revision>;
 693                         nvmem-cell-names = "soc_revision";
 694                         resets = <&zynqmp_reset ZYNQMP_RESET_SATA>,
 695                                  <&zynqmp_reset ZYNQMP_RESET_USB0_CORERESET>,
 696                                  <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>,
 697                                  <&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>,
 698                                  <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>,
 699                                  <&zynqmp_reset ZYNQMP_RESET_USB0_APB>,
 700                                  <&zynqmp_reset ZYNQMP_RESET_USB1_APB>,
 701                                  <&zynqmp_reset ZYNQMP_RESET_DP>,
 702                                  <&zynqmp_reset ZYNQMP_RESET_GEM0>,
 703                                  <&zynqmp_reset ZYNQMP_RESET_GEM1>,
 704                                  <&zynqmp_reset ZYNQMP_RESET_GEM2>,
 705                                  <&zynqmp_reset ZYNQMP_RESET_GEM3>;
 706                         reset-names = "sata_rst", "usb0_crst", "usb1_crst",
 707                                       "usb0_hibrst", "usb1_hibrst", "usb0_apbrst",
 708                                       "usb1_apbrst", "dp_rst", "gem0_rst",
 709                                       "gem1_rst", "gem2_rst", "gem3_rst";
 710                         lane0: lane0 {
 711                                 #phy-cells = <4>;
 712                         };
 713                         lane1: lane1 {
 714                                 #phy-cells = <4>;
 715                         };
 716                         lane2: lane2 {
 717                                 #phy-cells = <4>;
 718                         };
 719                         lane3: lane3 {
 720                                 #phy-cells = <4>;
 721                         };
 722                 };
 723
 724                 sata: ahci@fd0c0000 {
 725                         compatible = "ceva,ahci-1v84";
 726                         status = "disabled";
 727                         reg = <0x0 0xfd0c0000 0x0 0x2000>;
 728                         interrupt-parent = <&gic>;
 729                         interrupts = <0 133 4>;
 730                         power-domains = <&zynqmp_firmware PD_SATA>;
 731                         #stream-id-cells = <4>;
 732                         iommus = <&smmu 0x4c0>, <&smmu 0x4c1>,
 733                                  <&smmu 0x4c2>, <&smmu 0x4c3>;
 734                         /* dma-coherent; */
 735                 };
 736
 737                 sdhci0: mmc@ff160000 {
 738                         u-boot,dm-pre-reloc;
 739                         compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
 740                         status = "disabled";
 741                         interrupt-parent = <&gic>;
 742                         interrupts = <0 48 4>;
 743                         reg = <0x0 0xff160000 0x0 0x1000>;
 744                         clock-names = "clk_xin", "clk_ahb";
 745                         xlnx,device_id = <0>;
 746                         #stream-id-cells = <1>;
 747                         iommus = <&smmu 0x870>;
 748                         power-domains = <&zynqmp_firmware PD_SD_0>;
 749                         nvmem-cells = <&soc_revision>;
 750                         nvmem-cell-names = "soc_revision";
 751                         #clock-cells = <1>;
 752                         clock-output-names = "clk_out_sd0", "clk_in_sd0";
 753                 };
 754
 755                 sdhci1: mmc@ff170000 {
 756                         u-boot,dm-pre-reloc;
 757                         compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
 758                         status = "disabled";
 759                         interrupt-parent = <&gic>;
 760                         interrupts = <0 49 4>;
 761                         reg = <0x0 0xff170000 0x0 0x1000>;
 762                         clock-names = "clk_xin", "clk_ahb";
 763                         xlnx,device_id = <1>;
 764                         #stream-id-cells = <1>;
 765                         iommus = <&smmu 0x871>;
 766                         power-domains = <&zynqmp_firmware PD_SD_1>;
 767                         nvmem-cells = <&soc_revision>;
 768                         nvmem-cell-names = "soc_revision";
 769                         #clock-cells = <1>;
 770                         clock-output-names = "clk_out_sd1", "clk_in_sd1";
 771                 };
 772
 773                 smmu: smmu@fd800000 {
 774                         compatible = "arm,mmu-500";
 775                         reg = <0x0 0xfd800000 0x0 0x20000>;
 776                         #iommu-cells = <1>;
 777                         status = "disabled";
 778                         #global-interrupts = <1>;
 779                         interrupt-parent = <&gic>;
 780                         interrupts = <0 155 4>,
 781                                 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
 782                                 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
 783                                 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
 784                                 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;
 785                 };
 786
 787                 spi0: spi@ff040000 {
 788                         compatible = "cdns,spi-r1p6";
 789                         status = "disabled";
 790                         interrupt-parent = <&gic>;
 791                         interrupts = <0 19 4>;
 792                         reg = <0x0 0xff040000 0x0 0x1000>;
 793                         clock-names = "ref_clk", "pclk";
 794                         #address-cells = <1>;
 795                         #size-cells = <0>;
 796                         power-domains = <&zynqmp_firmware PD_SPI_0>;
 797                 };
 798
 799                 spi1: spi@ff050000 {
 800                         compatible = "cdns,spi-r1p6";
 801                         status = "disabled";
 802                         interrupt-parent = <&gic>;
 803                         interrupts = <0 20 4>;
 804                         reg = <0x0 0xff050000 0x0 0x1000>;
 805                         clock-names = "ref_clk", "pclk";
 806                         #address-cells = <1>;
 807                         #size-cells = <0>;
 808                         power-domains = <&zynqmp_firmware PD_SPI_1>;
 809                 };
 810
 811                 ttc0: timer@ff110000 {
 812                         compatible = "cdns,ttc";
 813                         status = "disabled";
 814                         interrupt-parent = <&gic>;
 815                         interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
 816                         reg = <0x0 0xff110000 0x0 0x1000>;
 817                         timer-width = <32>;
 818                         power-domains = <&zynqmp_firmware PD_TTC_0>;
 819                 };
 820
 821                 ttc1: timer@ff120000 {
 822                         compatible = "cdns,ttc";
 823                         status = "disabled";
 824                         interrupt-parent = <&gic>;
 825                         interrupts = <0 39 4>, <0 40 4>, <0 41 4>;
 826                         reg = <0x0 0xff120000 0x0 0x1000>;
 827                         timer-width = <32>;
 828                         power-domains = <&zynqmp_firmware PD_TTC_1>;
 829                 };
 830
 831                 ttc2: timer@ff130000 {
 832                         compatible = "cdns,ttc";
 833                         status = "disabled";
 834                         interrupt-parent = <&gic>;
 835                         interrupts = <0 42 4>, <0 43 4>, <0 44 4>;
 836                         reg = <0x0 0xff130000 0x0 0x1000>;
 837                         timer-width = <32>;
 838                         power-domains = <&zynqmp_firmware PD_TTC_2>;
 839                 };
 840
 841                 ttc3: timer@ff140000 {
 842                         compatible = "cdns,ttc";
 843                         status = "disabled";
 844                         interrupt-parent = <&gic>;
 845                         interrupts = <0 45 4>, <0 46 4>, <0 47 4>;
 846                         reg = <0x0 0xff140000 0x0 0x1000>;
 847                         timer-width = <32>;
 848                         power-domains = <&zynqmp_firmware PD_TTC_3>;
 849                 };
 850
 851                 uart0: serial@ff000000 {
 852                         u-boot,dm-pre-reloc;
 853                         compatible = "cdns,uart-r1p12", "xlnx,xuartps";
 854                         status = "disabled";
 855                         interrupt-parent = <&gic>;
 856                         interrupts = <0 21 4>;
 857                         reg = <0x0 0xff000000 0x0 0x1000>;
 858                         clock-names = "uart_clk", "pclk";
 859                         power-domains = <&zynqmp_firmware PD_UART_0>;
 860                 };
 861
 862                 uart1: serial@ff010000 {
 863                         u-boot,dm-pre-reloc;
 864                         compatible = "cdns,uart-r1p12", "xlnx,xuartps";
 865                         status = "disabled";
 866                         interrupt-parent = <&gic>;
 867                         interrupts = <0 22 4>;
 868                         reg = <0x0 0xff010000 0x0 0x1000>;
 869                         clock-names = "uart_clk", "pclk";
 870                         power-domains = <&zynqmp_firmware PD_UART_1>;
 871                 };
 872
 873                 usb0: usb0@ff9d0000 {
 874                         #address-cells = <2>;
 875                         #size-cells = <2>;
 876                         status = "disabled";
 877                         compatible = "xlnx,zynqmp-dwc3";
 878                         reg = <0x0 0xff9d0000 0x0 0x100>;
 879                         clock-names = "bus_clk", "ref_clk";
 880                         power-domains = <&zynqmp_firmware PD_USB_0>;
 881                         ranges;
 882                         nvmem-cells = <&soc_revision>;
 883                         nvmem-cell-names = "soc_revision";
 884
 885                         dwc3_0: dwc3@fe200000 {
 886                                 compatible = "snps,dwc3";
 887                                 status = "disabled";
 888                                 reg = <0x0 0xfe200000 0x0 0x40000>;
 889                                 interrupt-parent = <&gic>;
 890                                 interrupts = <0 65 4>, <0 69 4>;
 891                                 #stream-id-cells = <1>;
 892                                 iommus = <&smmu 0x860>;
 893                                 snps,quirk-frame-length-adjustment = <0x20>;
 894                                 snps,refclk_fladj;
 895                                 /* dma-coherent; */
 896                         };
 897                 };
 898
 899                 usb1: usb1@ff9e0000 {
 900                         #address-cells = <2>;
 901                         #size-cells = <2>;
 902                         status = "disabled";
 903                         compatible = "xlnx,zynqmp-dwc3";
 904                         reg = <0x0 0xff9e0000 0x0 0x100>;
 905                         clock-names = "bus_clk", "ref_clk";
 906                         power-domains = <&zynqmp_firmware PD_USB_1>;
 907                         ranges;
 908                         nvmem-cells = <&soc_revision>;
 909                         nvmem-cell-names = "soc_revision";
 910
 911                         dwc3_1: dwc3@fe300000 {
 912                                 compatible = "snps,dwc3";
 913                                 status = "disabled";
 914                                 reg = <0x0 0xfe300000 0x0 0x40000>;
 915                                 interrupt-parent = <&gic>;
 916                                 interrupts = <0 70 4>, <0 74 4>;
 917                                 #stream-id-cells = <1>;
 918                                 iommus = <&smmu 0x861>;
 919                                 snps,quirk-frame-length-adjustment = <0x20>;
 920                                 snps,refclk_fladj;
 921                                 /* dma-coherent; */
 922                         };
 923                 };
 924
 925                 watchdog0: watchdog@fd4d0000 {
 926                         compatible = "cdns,wdt-r1p2";
 927                         status = "disabled";
 928                         interrupt-parent = <&gic>;
 929                         interrupts = <0 113 1>;
 930                         reg = <0x0 0xfd4d0000 0x0 0x1000>;
 931                         timeout-sec = <60>;
 932                         reset-on-timeout;
 933                 };
 934
 935                 lpd_watchdog: watchdog@ff150000 {
 936                         compatible = "cdns,wdt-r1p2";
 937                         status = "disabled";
 938                         interrupt-parent = <&gic>;
 939                         interrupts = <0 52 1>;
 940                         reg = <0x0 0xff150000 0x0 0x1000>;
 941                         timeout-sec = <10>;
 942                 };
 943
 944                 xilinx_ams: ams@ffa50000 {
 945                         compatible = "xlnx,zynqmp-ams";
 946                         status = "disabled";
 947                         interrupt-parent = <&gic>;
 948                         interrupts = <0 56 4>;
 949                         interrupt-names = "ams-irq";
 950                         reg = <0x0 0xffa50000 0x0 0x800>;
 951                         reg-names = "ams-base";
 952                         #address-cells = <2>;
 953                         #size-cells = <2>;
 954                         #io-channel-cells = <1>;
 955                         ranges;
 956
 957                         ams_ps: ams_ps@ffa50800 {
 958                                 compatible = "xlnx,zynqmp-ams-ps";
 959                                 status = "disabled";
 960                                 reg = <0x0 0xffa50800 0x0 0x400>;
 961                         };
 962
 963                         ams_pl: ams_pl@ffa50c00 {
 964                                 compatible = "xlnx,zynqmp-ams-pl";
 965                                 status = "disabled";
 966                                 reg = <0x0 0xffa50c00 0x0 0x400>;
 967                         };
 968                 };
 969
 970                 xlnx_dpdma: dma@fd4c0000 {
 971                         compatible = "xlnx,dpdma";
 972                         status = "disabled";
 973                         reg = <0x0 0xfd4c0000 0x0 0x1000>;
 974                         interrupts = <0 122 4>;
 975                         interrupt-parent = <&gic>;
 976                         clock-names = "axi_clk";
 977                         power-domains = <&zynqmp_firmware PD_DP>;
 978                         dma-channels = <6>;
 979                         #dma-cells = <1>;
 980                         dma-video0channel {
 981                                 compatible = "xlnx,video0";
 982                         };
 983                         dma-video1channel {
 984                                 compatible = "xlnx,video1";
 985                         };
 986                         dma-video2channel {
 987                                 compatible = "xlnx,video2";
 988                         };
 989                         dma-graphicschannel {
 990                                 compatible = "xlnx,graphics";
 991                         };
 992                         dma-audio0channel {
 993                                 compatible = "xlnx,audio0";
 994                         };
 995                         dma-audio1channel {
 996                                 compatible = "xlnx,audio1";
 997                         };
 998                 };
 999
1000                 zynqmp_dpsub: zynqmp-display@fd4a0000 {
1001                         compatible = "xlnx,zynqmp-dpsub-1.7";
1002                         status = "disabled";
1003                         reg = <0x0 0xfd4a0000 0x0 0x1000>,
1004                               <0x0 0xfd4aa000 0x0 0x1000>,
1005                               <0x0 0xfd4ab000 0x0 0x1000>,
1006                               <0x0 0xfd4ac000 0x0 0x1000>;
1007                         reg-names = "dp", "blend", "av_buf", "aud";
1008                         interrupts = <0 119 4>;
1009                         interrupt-parent = <&gic>;
1010
1011                         clock-names = "dp_apb_clk", "dp_aud_clk",
1012                                       "dp_vtc_pixel_clk_in";
1013
1014                         power-domains = <&zynqmp_firmware PD_DP>;
1015
1016                         vid-layer {
1017                                 dma-names = "vid0", "vid1", "vid2";
1018                                 dmas = <&xlnx_dpdma 0>,
1019                                        <&xlnx_dpdma 1>,
1020                                        <&xlnx_dpdma 2>;
1021                         };
1022
1023                         gfx-layer {
1024                                 dma-names = "gfx0";
1025                                 dmas = <&xlnx_dpdma 3>;
1026                         };
1027
1028                         /* dummy node to indicate there's no child i2c device */
1029                         i2c-bus {
1030                         };
1031
1032                         zynqmp_dp_snd_codec0: zynqmp_dp_snd_codec0 {
1033                                 compatible = "xlnx,dp-snd-codec";
1034                                 clock-names = "aud_clk";
1035                         };
1036
1037                         zynqmp_dp_snd_pcm0: zynqmp_dp_snd_pcm0 {
1038                                 compatible = "xlnx,dp-snd-pcm";
1039                                 dmas = <&xlnx_dpdma 4>;
1040                                 dma-names = "tx";
1041                         };
1042
1043                         zynqmp_dp_snd_pcm1: zynqmp_dp_snd_pcm1 {
1044                                 compatible = "xlnx,dp-snd-pcm";
1045                                 dmas = <&xlnx_dpdma 5>;
1046                                 dma-names = "tx";
1047                         };
1048
1049                         zynqmp_dp_snd_card0: zynqmp_dp_snd_card {
1050                                 compatible = "xlnx,dp-snd-card";
1051                                 xlnx,dp-snd-pcm = <&zynqmp_dp_snd_pcm0>,
1052                                                   <&zynqmp_dp_snd_pcm1>;
1053                                 xlnx,dp-snd-codec = <&zynqmp_dp_snd_codec0>;
1054                         };
1055                 };
1056         };
1057 };