arch/arm/dts/zynqmp-zcu216-revA.dts

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * dts file for Xilinx ZynqMP ZCU216
   4  *
   5  * (C) Copyright 2017 - 2021, Xilinx, Inc.
   6  *
   7  * Michal Simek <michal.simek@amd.com>
   8  */
   9
  10 /dts-v1/;
  11
  12 #include "zynqmp.dtsi"
  13 #include "zynqmp-clk-ccf.dtsi"
  14 #include <dt-bindings/input/input.h>
  15 #include <dt-bindings/gpio/gpio.h>
  16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
  17 #include <dt-bindings/phy/phy.h>
  18
  19 / {
  20         model = "ZynqMP ZCU216 RevA";
  21         compatible = "xlnx,zynqmp-zcu216-revA", "xlnx,zynqmp-zcu216", "xlnx,zynqmp";
  22
  23         aliases {
  24                 ethernet0 = &gem3;
  25                 i2c0 = &i2c0;
  26                 i2c1 = &i2c1;
  27                 mmc0 = &sdhci1;
  28                 nvmem0 = &eeprom;
  29                 rtc0 = &rtc;
  30                 serial0 = &uart0;
  31                 serial1 = &dcc;
  32                 spi0 = &qspi;
  33                 usb0 = &usb0;
  34         };
  35
  36         chosen {
  37                 bootargs = "earlycon";
  38                 stdout-path = "serial0:115200n8";
  39         };
  40
  41         memory@0 {
  42                 device_type = "memory";
  43                 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
  44         };
  45
  46         gpio-keys {
  47                 compatible = "gpio-keys";
  48                 autorepeat;
  49                 sw19 {
  50                         label = "sw19";
  51                         gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
  52                         linux,code = <KEY_DOWN>;
  53                         wakeup-source;
  54                         autorepeat;
  55                 };
  56         };
  57
  58         leds {
  59                 compatible = "gpio-leds";
  60                 heartbeat_led {
  61                         label = "heartbeat";
  62                         gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
  63                         linux,default-trigger = "heartbeat";
  64                 };
  65         };
  66
  67         ina226-vccint {
  68                 compatible = "iio-hwmon";
  69                 io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;
  70         };
  71         ina226-vccint-io-bram-ps {
  72                 compatible = "iio-hwmon";
  73                 io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>;
  74         };
  75         ina226-vcc1v8 {
  76                 compatible = "iio-hwmon";
  77                 io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>;
  78         };
  79         ina226-vcc1v2 {
  80                 compatible = "iio-hwmon";
  81                 io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>;
  82         };
  83         ina226-vadj-fmc {
  84                 compatible = "iio-hwmon";
  85                 io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;
  86         };
  87         ina226-mgtavcc {
  88                 compatible = "iio-hwmon";
  89                 io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>;
  90         };
  91         ina226-mgt1v2 {
  92                 compatible = "iio-hwmon";
  93                 io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>;
  94         };
  95         ina226-mgt1v8 {
  96                 compatible = "iio-hwmon";
  97                 io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>;
  98         };
  99         ina226-vccint-ams {
 100                 compatible = "iio-hwmon";
 101                 io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>;
 102         };
 103         ina226-dac-avtt {
 104                 compatible = "iio-hwmon";
 105                 io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>;
 106         };
 107         ina226-dac-avccaux {
 108                 compatible = "iio-hwmon";
 109                 io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>;
 110         };
 111         ina226-adc-avcc {
 112                 compatible = "iio-hwmon";
 113                 io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>;
 114         };
 115         ina226-adc-avccaux {
 116                 compatible = "iio-hwmon";
 117                 io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>;
 118         };
 119         ina226-dac-avcc {
 120                 compatible = "iio-hwmon";
 121                 io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>;
 122         };
 123
 124         /* 48MHz reference crystal */
 125         ref48: ref48M {
 126                 compatible = "fixed-clock";
 127                 #clock-cells = <0>;
 128                 clock-frequency = <48000000>;
 129         };
 130 };
 131
 132 &psgtr {
 133         status = "okay";
 134         /* nc, nc, usb3, sata */
 135         clocks = <&si5341 0 2>, <&si5341 0 3>;
 136         clock-names = "ref2", "ref3";
 137 };
 138
 139 &dcc {
 140         status = "okay";
 141 };
 142
 143 &fpd_dma_chan1 {
 144         status = "okay";
 145 };
 146
 147 &fpd_dma_chan2 {
 148         status = "okay";
 149 };
 150
 151 &fpd_dma_chan3 {
 152         status = "okay";
 153 };
 154
 155 &fpd_dma_chan4 {
 156         status = "okay";
 157 };
 158
 159 &fpd_dma_chan5 {
 160         status = "okay";
 161 };
 162
 163 &fpd_dma_chan6 {
 164         status = "okay";
 165 };
 166
 167 &fpd_dma_chan7 {
 168         status = "okay";
 169 };
 170
 171 &fpd_dma_chan8 {
 172         status = "okay";
 173 };
 174
 175 &gem3 {
 176         status = "okay";
 177         phy-handle = <&phy0>;
 178         phy-mode = "rgmii-id";
 179         mdio: mdio {
 180                 #address-cells = <1>;
 181                 #size-cells = <0>;
 182                 phy0: ethernet-phy@c {
 183                         #phy-cells = <1>;
 184                         compatible = "ethernet-phy-id2000.a231";
 185                         reg = <0xc>;
 186                         ti,rx-internal-delay = <0x8>;
 187                         ti,tx-internal-delay = <0xa>;
 188                         ti,fifo-depth = <0x1>;
 189                         ti,dp83867-rxctrl-strap-quirk;
 190                         reset-gpios = <&tca6416_u15 6 GPIO_ACTIVE_LOW>;
 191                 };
 192         };
 193 };
 194 &gpio {
 195         status = "okay";
 196         gpio-line-names = "QSPI_LWR_CLK", "QSPI_LWR_DQ1", "QSPI_LWR_DQ2", "QSPI_LWR_DQ3", "QSPI_LWR_DQ0", /* 0 - 4 */
 197                   "QSPI_LWR_CS_B", "", "QSPI_UPR_CS_B", "QSPI_UPR_DQ0", "QSPI_UPR_DQ1", /* 5 - 9 */
 198                   "QSPI_UPR_DQ2", "QSPI_UPR_DQ3", "QSPI_UPR_CLK", "PS_GPIO2", "I2C0_SCL", /* 10 - 14 */
 199                   "I2C0_SDA", "I2C1_SCL", "I2C1_SDA", "UART0_TXD", "UART0_RXD", /* 15 - 19 */
 200                   "", "", "BUTTON", "LED", "", /* 20 - 24 */
 201                   "", "PMU_INPUT", "", "", "", /* 25 - 29 */
 202                   "", "", "PMU_GPO0", "PMU_GPO1", "PMU_GPO2", /* 30 - 34 */
 203                   "PMU_GPO3", "PMU_GPO4", "PMU_GPO5", "PS_GPIO1", "SDIO_SEL", /* 35 - 39 */
 204                   "SDIO_DIR_CMD", "SDIO_DIR_DAT0", "SDIO_DIR_DAT1", "", "", /* 40 - 44 */
 205                   "SDIO_DETECT", "SDIO_DAT0", "SDIO_DAT1", "SDIO_DAT2", "SDIO_DAT3", /* 45 - 49 */
 206                   "SDIO_CMD", "SDIO_CLK", "USB_CLK", "USB_DIR", "USB_DATA2", /* 50 - 54 */
 207                   "USB_NXT", "USB_DATA0", "USB_DATA1", "USB_STP", "USB_DATA3", /* 55 - 59 */
 208                   "USB_DATA4", "USB_DATA5", "USB_DATA6", "USB_DATA7", "ENET_TX_CLK", /* 60 - 64 */
 209                   "ENET_TX_D0", "ENET_TX_D1", "ENET_TX_D2", "ENET_TX_D3", "ENET_TX_CTRL", /* 65 - 69 */
 210                   "ENET_RX_CLK", "ENET_RX_D0", "ENET_RX_D1", "ENET_RX_D2", "ENET_RX_D3", /* 70 - 74 */
 211                   "ENET_RX_CTRL", "ENET_MDC", "ENET_MDIO", /* 75 - 77, MIO end and EMIO start */
 212                   "", "", /* 78 - 79 */
 213                   "", "", "", "", "", /* 80 - 84 */
 214                   "", "", "", "", "", /* 85 -89 */
 215                   "", "", "", "", "", /* 90 - 94 */
 216                   "", "", "", "", "", /* 95 - 99 */
 217                   "", "", "", "", "", /* 100 - 104 */
 218                   "", "", "", "", "", /* 105 - 109 */
 219                   "", "", "", "", "", /* 110 - 114 */
 220                   "", "", "", "", "", /* 115 - 119 */
 221                   "", "", "", "", "", /* 120 - 124 */
 222                   "", "", "", "", "", /* 125 - 129 */
 223                   "", "", "", "", "", /* 130 - 134 */
 224                   "", "", "", "", "", /* 135 - 139 */
 225                   "", "", "", "", "", /* 140 - 144 */
 226                   "", "", "", "", "", /* 145 - 149 */
 227                   "", "", "", "", "", /* 150 - 154 */
 228                   "", "", "", "", "", /* 155 - 159 */
 229                   "", "", "", "", "", /* 160 - 164 */
 230                   "", "", "", "", "", /* 165 - 169 */
 231                   "", "", "", ""; /* 170 - 173 */
 232 };
 233
 234 &gpu {
 235         status = "okay";
 236 };
 237
 238 &i2c0 {
 239         status = "okay";
 240         clock-frequency = <400000>;
 241         pinctrl-names = "default", "gpio";
 242         pinctrl-0 = <&pinctrl_i2c0_default>;
 243         pinctrl-1 = <&pinctrl_i2c0_gpio>;
 244         scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 245         sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 246
 247         tca6416_u15: gpio@20 { /* u15 */
 248                 compatible = "ti,tca6416";
 249                 reg = <0x20>;
 250                 gpio-controller; /* interrupt not connected */
 251                 #gpio-cells = <2>;
 252                 gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "MIO26_PMU_INPUT_LS", "", /* 0 - 3 */
 253                                   "", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "MAX6643_FULL_SPEED", /* 4 - 7 */
 254                                   "FMCP_HSPC_PRSNT_M2C_B", "", "", "VCCINT_VRHOT_B", /* 10 - 13 */
 255                                   "", "8A34001_EXP_RST_B", "IRPS5401_ALERT_B", "INA226_PMBUS_ALERT"; /* 14 - 17 */
 256         };
 257
 258         i2c-mux@75 { /* u17 */
 259                 compatible = "nxp,pca9544";
 260                 #address-cells = <1>;
 261                 #size-cells = <0>;
 262                 reg = <0x75>;
 263                 i2c@0 {
 264                         #address-cells = <1>;
 265                         #size-cells = <0>;
 266                         reg = <0>;
 267                         /* PS_PMBUS */
 268                         /* PMBUS_ALERT done via pca9544 */
 269                         vccint: ina226@40 { /* u65 */
 270                                 compatible = "ti,ina226";
 271                                 #io-channel-cells = <1>;
 272                                 label = "ina226-vccint";
 273                                 reg = <0x40>;
 274                                 shunt-resistor = <5000>;
 275                         };
 276                         vccint_io_bram_ps: ina226@41 { /* u57 */
 277                                 compatible = "ti,ina226";
 278                                 #io-channel-cells = <1>;
 279                                 label = "ina226-vccint-io-bram-ps";
 280                                 reg = <0x41>;
 281                                 shunt-resistor = <5000>;
 282                         };
 283                         vcc1v8: ina226@42 { /* u60 */
 284                                 compatible = "ti,ina226";
 285                                 #io-channel-cells = <1>;
 286                                 label = "ina226-vcc1v8";
 287                                 reg = <0x42>;
 288                                 shunt-resistor = <2000>;
 289                         };
 290                         vcc1v2: ina226@43 { /* u58 */
 291                                 compatible = "ti,ina226";
 292                                 #io-channel-cells = <1>;
 293                                 label = "ina226-vcc1v2";
 294                                 reg = <0x43>;
 295                                 shunt-resistor = <5000>;
 296                         };
 297                         vadj_fmc: ina226@45 { /* u62 */
 298                                 compatible = "ti,ina226";
 299                                 #io-channel-cells = <1>;
 300                                 label = "ina226-vadj-fmc";
 301                                 reg = <0x45>;
 302                                 shunt-resistor = <5000>;
 303                         };
 304                         mgtavcc: ina226@46 { /* u67 */
 305                                 compatible = "ti,ina226";
 306                                 #io-channel-cells = <1>;
 307                                 label = "ina226-mgtavcc";
 308                                 reg = <0x46>;
 309                                 shunt-resistor = <2000>;
 310                         };
 311                         mgt1v2: ina226@47 { /* u63 */
 312                                 compatible = "ti,ina226";
 313                                 #io-channel-cells = <1>;
 314                                 label = "ina226-mgt1v2";
 315                                 reg = <0x47>;
 316                                 shunt-resistor = <5000>;
 317                         };
 318                         mgt1v8: ina226@48 { /* u64 */
 319                                 compatible = "ti,ina226";
 320                                 #io-channel-cells = <1>;
 321                                 label = "ina226-mgt1v8";
 322                                 reg = <0x48>;
 323                                 shunt-resistor = <5000>;
 324                         };
 325                         vccint_ams: ina226@49 { /* u61 */
 326                                 compatible = "ti,ina226";
 327                                 #io-channel-cells = <1>;
 328                                 label = "ina226-vccint-ams";
 329                                 reg = <0x49>;
 330                                 shunt-resistor = <5000>;
 331                         };
 332                         dac_avtt: ina226@4a { /* u59 */
 333                                 compatible = "ti,ina226";
 334                                 #io-channel-cells = <1>;
 335                                 label = "ina226-dac-avtt";
 336                                 reg = <0x4a>;
 337                                 shunt-resistor = <5000>;
 338                         };
 339                         dac_avccaux: ina226@4b { /* u124 */
 340                                 compatible = "ti,ina226";
 341                                 #io-channel-cells = <1>;
 342                                 label = "ina226-dac-avccaux";
 343                                 reg = <0x4b>;
 344                                 shunt-resistor = <5000>;
 345                         };
 346                         adc_avcc: ina226@4c { /* u75 */
 347                                 compatible = "ti,ina226";
 348                                 #io-channel-cells = <1>;
 349                                 label = "ina226-adc-avcc";
 350                                 reg = <0x4c>;
 351                                 shunt-resistor = <5000>;
 352                         };
 353                         adc_avccaux: ina226@4d { /* u71 */
 354                                 compatible = "ti,ina226";
 355                                 #io-channel-cells = <1>;
 356                                 label = "ina226-adc-avccaux";
 357                                 reg = <0x4d>;
 358                                 shunt-resistor = <5000>;
 359                         };
 360                         dac_avcc: ina226@4e { /* u77 */
 361                                 compatible = "ti,ina226";
 362                                 #io-channel-cells = <1>;
 363                                 label = "ina226-dac-avcc";
 364                                 reg = <0x4e>;
 365                                 shunt-resistor = <5000>;
 366                         };
 367                 };
 368                 i2c@1 {
 369                         #address-cells = <1>;
 370                         #size-cells = <0>;
 371                         reg = <1>;
 372                         /* NC */
 373                 };
 374                 i2c@2 {
 375                         #address-cells = <1>;
 376                         #size-cells = <0>;
 377                         reg = <2>;
 378                         /* u104 - ir35215 0x10/0x40 */
 379                         /* u127 - ir38164 0x1b/0x4b */
 380                         /* u112 - ir38164 0x13/0x43 */
 381                         /* u123 - ir38164 0x1c/0x4c */
 382
 383                         irps5401_44: irps5401@44 { /* IRPS5401 - u53 */
 384                                 compatible = "infineon,irps5401";
 385                                 reg = <0x44>; /* i2c addr 0x14 */
 386                         };
 387                         irps5401_45: irps5401@45 { /* IRPS5401 - u55 */
 388                                 compatible = "infineon,irps5401";
 389                                 reg = <0x45>; /* i2c addr 0x15 */
 390                         };
 391                         /* J21 header too */
 392
 393                 };
 394                 i2c@3 {
 395                         #address-cells = <1>;
 396                         #size-cells = <0>;
 397                         reg = <3>;
 398                         /* SYSMON */
 399                 };
 400         };
 401         /* u38 MPS430 */
 402 };
 403
 404 &i2c1 {
 405         status = "okay";
 406         clock-frequency = <400000>;
 407         pinctrl-names = "default", "gpio";
 408         pinctrl-0 = <&pinctrl_i2c1_default>;
 409         pinctrl-1 = <&pinctrl_i2c1_gpio>;
 410         scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 411         sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 412
 413         i2c-mux@74 {
 414                 compatible = "nxp,pca9548"; /* u20 */
 415                 #address-cells = <1>;
 416                 #size-cells = <0>;
 417                 reg = <0x74>;
 418                 i2c-mux-idle-disconnect;
 419                 /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
 420                 i2c_eeprom: i2c@0 {
 421                         #address-cells = <1>;
 422                         #size-cells = <0>;
 423                         reg = <0>;
 424                         /*
 425                          * IIC_EEPROM 1kB memory which uses 256B blocks
 426                          * where every block has different address.
 427                          *    0 - 256B address 0x54
 428                          * 256B - 512B address 0x55
 429                          * 512B - 768B address 0x56
 430                          * 768B - 1024B address 0x57
 431                          */
 432                         eeprom: eeprom@54 { /* u21 */
 433                                 compatible = "atmel,24c128";
 434                                 reg = <0x54>;
 435                         };
 436                 };
 437                 i2c_si5341: i2c@1 {
 438                         #address-cells = <1>;
 439                         #size-cells = <0>;
 440                         reg = <1>;
 441                         si5341: clock-generator@36 { /* SI5341 - u43 */
 442                                 compatible = "silabs,si5341";
 443                                 reg = <0x36>;
 444                                 #clock-cells = <2>;
 445                                 #address-cells = <1>;
 446                                 #size-cells = <0>;
 447                                 clocks = <&ref48>;
 448                                 clock-names = "xtal";
 449                                 clock-output-names = "si5341";
 450
 451                                 si5341_2: out@2 {
 452                                         /* refclk2 for PS-GT, used for USB3 */
 453                                         reg = <2>;
 454                                         always-on;
 455                                 };
 456                                 si5341_3: out@3 {
 457                                         /* refclk3 for PS-GT, used for SATA */
 458                                         reg = <3>;
 459                                         always-on;
 460                                 };
 461                                 si5341_5: out@5 {
 462                                         /* refclk5 PL CLK100 */
 463                                         reg = <5>;
 464                                         always-on;
 465                                 };
 466                                 si5341_6: out@6 {
 467                                         /* refclk6 PL CLK125 */
 468                                         reg = <6>;
 469                                         always-on;
 470                                 };
 471                                 si5341_9: out@9 {
 472                                         /* refclk9 used for PS_REF_CLK 33.3 MHz */
 473                                         reg = <9>;
 474                                         always-on;
 475                                 };
 476                         };
 477                 };
 478                 i2c_si570_user_c0: i2c@2 {
 479                         #address-cells = <1>;
 480                         #size-cells = <0>;
 481                         reg = <2>;
 482                         si570_1: clock-generator@5d { /* USER C0 SI570 - u47 */
 483                                 #clock-cells = <0>;
 484                                 compatible = "silabs,si570";
 485                                 reg = <0x5d>;
 486                                 temperature-stability = <50>;
 487                                 factory-fout = <300000000>;
 488                                 clock-frequency = <300000000>;
 489                                 clock-output-names = "si570_user_c0";
 490                         };
 491                 };
 492                 i2c_si570_mgt: i2c@3 {
 493                         #address-cells = <1>;
 494                         #size-cells = <0>;
 495                         reg = <3>;
 496                         si570_2: clock-generator@5d { /* USER MGT SI570 - u48 */
 497                                 #clock-cells = <0>;
 498                                 compatible = "silabs,si570";
 499                                 reg = <0x5d>;
 500                                 temperature-stability = <50>;
 501                                 factory-fout = <156250000>;
 502                                 clock-frequency = <148500000>;
 503                                 clock-output-names = "si570_mgt";
 504                         };
 505                 };
 506                 i2c_8a34001: i2c@4 {
 507                         #address-cells = <1>;
 508                         #size-cells = <0>;
 509                         reg = <4>;
 510                         idt_8a34001: phc@5b {
 511                                 compatible = "idt,8a34001"; /* u409B */
 512                                 reg = <0x5b>;
 513                         };
 514                 };
 515                 i2c_clk104: i2c@5 {
 516                         #address-cells = <1>;
 517                         #size-cells = <0>;
 518                         reg = <5>;
 519                         /* CLK104_SDA */
 520                 };
 521                 i2c@6 {
 522                         #address-cells = <1>;
 523                         #size-cells = <0>;
 524                         reg = <6>;
 525                         /* RFMCP connector */
 526                 };
 527                 /* 7 NC */
 528         };
 529
 530         i2c-mux@75 {
 531                 compatible = "nxp,pca9548"; /* u22 */
 532                 #address-cells = <1>;
 533                 #size-cells = <0>;
 534                 reg = <0x75>;
 535                 i2c-mux-idle-disconnect;
 536                 /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
 537                 i2c@0 {
 538                         #address-cells = <1>;
 539                         #size-cells = <0>;
 540                         reg = <0>;
 541                         /* FMCP_HSPC_IIC */
 542                 };
 543                 i2c_si570_user_c1: i2c@1 {
 544                         #address-cells = <1>;
 545                         #size-cells = <0>;
 546                         reg = <1>;
 547                         si570_3: clock-generator@5d { /* USER C1 SI570 - u130 */
 548                                 #clock-cells = <0>;
 549                                 compatible = "silabs,si570";
 550                                 reg = <0x5d>;
 551                                 temperature-stability = <50>;
 552                                 factory-fout = <300000000>;
 553                                 clock-frequency = <300000000>;
 554                                 clock-output-names = "si570_user_c1";
 555                         };
 556                 };
 557                 i2c@2 {
 558                         #address-cells = <1>;
 559                         #size-cells = <0>;
 560                         reg = <2>;
 561                         /* SYSMON */
 562                 };
 563                 i2c@3 {
 564                         #address-cells = <1>;
 565                         #size-cells = <0>;
 566                         reg = <3>;
 567                         /* DDR4 SODIMM */
 568                 };
 569                 i2c@4 {
 570                         #address-cells = <1>;
 571                         #size-cells = <0>;
 572                         reg = <4>;
 573                         /* SFP3 */
 574                 };
 575                 i2c@5 {
 576                         #address-cells = <1>;
 577                         #size-cells = <0>;
 578                         reg = <5>;
 579                         /* SFP2 */
 580                 };
 581                 i2c@6 {
 582                         #address-cells = <1>;
 583                         #size-cells = <0>;
 584                         reg = <6>;
 585                         /* SFP1 */
 586                 };
 587                 i2c@7 {
 588                         #address-cells = <1>;
 589                         #size-cells = <0>;
 590                         reg = <7>;
 591                         /* SFP0 */
 592                 };
 593         };
 594         /* MSP430 */
 595 };
 596
 597 &pinctrl0 {
 598         status = "okay";
 599         pinctrl_i2c0_default: i2c0-default {
 600                 mux {
 601                         groups = "i2c0_3_grp";
 602                         function = "i2c0";
 603                 };
 604
 605                 conf {
 606                         groups = "i2c0_3_grp";
 607                         bias-pull-up;
 608                         slew-rate = <SLEW_RATE_SLOW>;
 609                         power-source = <IO_STANDARD_LVCMOS18>;
 610                 };
 611         };
 612
 613         pinctrl_i2c0_gpio: i2c0-gpio {
 614                 mux {
 615                         groups = "gpio0_14_grp", "gpio0_15_grp";
 616                         function = "gpio0";
 617                 };
 618
 619                 conf {
 620                         groups = "gpio0_14_grp", "gpio0_15_grp";
 621                         slew-rate = <SLEW_RATE_SLOW>;
 622                         power-source = <IO_STANDARD_LVCMOS18>;
 623                 };
 624         };
 625
 626         pinctrl_i2c1_default: i2c1-default {
 627                 mux {
 628                         groups = "i2c1_4_grp";
 629                         function = "i2c1";
 630                 };
 631
 632                 conf {
 633                         groups = "i2c1_4_grp";
 634                         bias-pull-up;
 635                         slew-rate = <SLEW_RATE_SLOW>;
 636                         power-source = <IO_STANDARD_LVCMOS18>;
 637                 };
 638         };
 639
 640         pinctrl_i2c1_gpio: i2c1-gpio {
 641                 mux {
 642                         groups = "gpio0_16_grp", "gpio0_17_grp";
 643                         function = "gpio0";
 644                 };
 645
 646                 conf {
 647                         groups = "gpio0_16_grp", "gpio0_17_grp";
 648                         slew-rate = <SLEW_RATE_SLOW>;
 649                         power-source = <IO_STANDARD_LVCMOS18>;
 650                 };
 651         };
 652 };
 653
 654 &qspi {
 655         status = "okay";
 656         is-dual = <1>;
 657         flash@0 {
 658                 compatible = "m25p80", "jedec,spi-nor"; /* U11 and U12 MT25QU02GCBBE12 1Gb */
 659                 #address-cells = <1>;
 660                 #size-cells = <1>;
 661                 reg = <0x0>;
 662                 spi-tx-bus-width = <4>;
 663                 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
 664                 spi-max-frequency = <108000000>; /* Based on DC1 spec */
 665         };
 666 };
 667
 668 &rtc {
 669         status = "okay";
 670 };
 671
 672 &sata {
 673         status = "okay";
 674         /* SATA OOB timing settings */
 675         ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
 676         ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
 677         ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 678         ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 679         ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
 680         ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
 681         ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 682         ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 683         phy-names = "sata-phy";
 684         phys = <&psgtr 3 PHY_TYPE_SATA 1 3>;
 685 };
 686
 687 /* SD1 with level shifter */
 688 &sdhci1 {
 689         status = "okay";
 690         disable-wp;
 691         /*
 692          * This property should be removed for supporting UHS mode
 693          */
 694         no-1-8-v;
 695         xlnx,mio-bank = <1>;
 696 };
 697
 698 &uart0 {
 699         status = "okay";
 700 };
 701
 702 /* ULPI SMSC USB3320 */
 703 &usb0 {
 704         status = "okay";
 705         phy-names = "usb3-phy";
 706         phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
 707 };
 708
 709 &dwc3_0 {
 710         status = "okay";
 711         dr_mode = "host";
 712         snps,usb3_lpm_capable;
 713         maximum-speed = "super-speed";
 714 };