arch/arm/dts/zynqmp-zcu104-revC.dts

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * dts file for Xilinx ZynqMP ZCU104
   4  *
   5  * (C) Copyright 2017 - 2021, Xilinx, Inc.
   6  *
   7  * Michal Simek <michal.simek@amd.com>
   8  */
   9
  10 /dts-v1/;
  11
  12 #include "zynqmp.dtsi"
  13 #include "zynqmp-clk-ccf.dtsi"
  14 #include <dt-bindings/gpio/gpio.h>
  15 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
  16 #include <dt-bindings/phy/phy.h>
  17
  18 / {
  19         model = "ZynqMP ZCU104 RevC";
  20         compatible = "xlnx,zynqmp-zcu104-revC", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
  21
  22         aliases {
  23                 ethernet0 = &gem3;
  24                 i2c0 = &i2c1;
  25                 mmc0 = &sdhci1;
  26                 nvmem0 = &eeprom;
  27                 rtc0 = &rtc;
  28                 serial0 = &uart0;
  29                 serial1 = &uart1;
  30                 serial2 = &dcc;
  31                 spi0 = &qspi;
  32                 usb0 = &usb0;
  33         };
  34
  35         chosen {
  36                 bootargs = "earlycon";
  37                 stdout-path = "serial0:115200n8";
  38         };
  39
  40         memory@0 {
  41                 device_type = "memory";
  42                 reg = <0x0 0x0 0x0 0x80000000>;
  43         };
  44
  45         ina226 {
  46                 compatible = "iio-hwmon";
  47                 io-channels = <&u183 0>, <&u183 1>, <&u183 2>, <&u183 3>;
  48         };
  49
  50         clock_8t49n287_5: clk125 {
  51                 compatible = "fixed-clock";
  52                 #clock-cells = <0>;
  53                 clock-frequency = <125000000>;
  54         };
  55
  56         clock_8t49n287_2: clk26 {
  57                 compatible = "fixed-clock";
  58                 #clock-cells = <0>;
  59                 clock-frequency = <26000000>;
  60         };
  61
  62         clock_8t49n287_3: clk27 {
  63                 compatible = "fixed-clock";
  64                 #clock-cells = <0>;
  65                 clock-frequency = <27000000>;
  66         };
  67 };
  68
  69 &can1 {
  70         status = "okay";
  71         pinctrl-names = "default";
  72         pinctrl-0 = <&pinctrl_can1_default>;
  73 };
  74
  75 &dcc {
  76         status = "okay";
  77 };
  78
  79 &fpd_dma_chan1 {
  80         status = "okay";
  81 };
  82
  83 &fpd_dma_chan2 {
  84         status = "okay";
  85 };
  86
  87 &fpd_dma_chan3 {
  88         status = "okay";
  89 };
  90
  91 &fpd_dma_chan4 {
  92         status = "okay";
  93 };
  94
  95 &fpd_dma_chan5 {
  96         status = "okay";
  97 };
  98
  99 &fpd_dma_chan6 {
 100         status = "okay";
 101 };
 102
 103 &fpd_dma_chan7 {
 104         status = "okay";
 105 };
 106
 107 &fpd_dma_chan8 {
 108         status = "okay";
 109 };
 110
 111 &gem3 {
 112         status = "okay";
 113         phy-handle = <&phy0>;
 114         phy-mode = "rgmii-id";
 115         pinctrl-names = "default";
 116         pinctrl-0 = <&pinctrl_gem3_default>;
 117         mdio: mdio {
 118                 #address-cells = <1>;
 119                 #size-cells = <0>;
 120                 phy0: ethernet-phy@c {
 121                         #phy-cells = <1>;
 122                         compatible = "ethernet-phy-id2000.a231";
 123                         reg = <0xc>;
 124                         ti,rx-internal-delay = <0x8>;
 125                         ti,tx-internal-delay = <0xa>;
 126                         ti,fifo-depth = <0x1>;
 127                         ti,dp83867-rxctrl-strap-quirk;
 128                         reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;
 129                 };
 130         };
 131 };
 132
 133 &gpio {
 134         status = "okay";
 135 };
 136
 137 &gpu {
 138         status = "okay";
 139 };
 140
 141 &i2c1 {
 142         status = "okay";
 143         clock-frequency = <400000>;
 144         pinctrl-names = "default", "gpio";
 145         pinctrl-0 = <&pinctrl_i2c1_default>;
 146         pinctrl-1 = <&pinctrl_i2c1_gpio>;
 147         scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 148         sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 149
 150         tca6416_u97: gpio@20 {
 151                 compatible = "ti,tca6416";
 152                 reg = <0x20>;
 153                 gpio-controller;
 154                 #gpio-cells = <2>;
 155                 /*
 156                  * IRQ not connected
 157                  * Lines:
 158                  * 0 - IRPS5401_ALERT_B
 159                  * 1 - HDMI_8T49N241_INT_ALM
 160                  * 2 - MAX6643_OT_B
 161                  * 3 - MAX6643_FANFAIL_B
 162                  * 5 - IIC_MUX_RESET_B
 163                  * 6 - GEM3_EXP_RESET_B
 164                  * 7 - FMC_LPC_PRSNT_M2C_B
 165                  * 4, 10 - 17 - not connected
 166                  */
 167         };
 168
 169         /* Another connection to this bus via PL i2c via PCA9306 - u45 */
 170         i2c-mux@74 { /* u34 */
 171                 compatible = "nxp,pca9548";
 172                 #address-cells = <1>;
 173                 #size-cells = <0>;
 174                 reg = <0x74>;
 175                 i2c@0 {
 176                         #address-cells = <1>;
 177                         #size-cells = <0>;
 178                         reg = <0>;
 179                         /*
 180                          * IIC_EEPROM 1kB memory which uses 256B blocks
 181                          * where every block has different address.
 182                          *    0 - 256B address 0x54
 183                          * 256B - 512B address 0x55
 184                          * 512B - 768B address 0x56
 185                          * 768B - 1024B address 0x57
 186                          */
 187                         eeprom: eeprom@54 { /* u23 */
 188                                 compatible = "atmel,24c08";
 189                                 reg = <0x54>;
 190                                 #address-cells = <1>;
 191                                 #size-cells = <1>;
 192                         };
 193                 };
 194
 195                 i2c@1 {
 196                         #address-cells = <1>;
 197                         #size-cells = <0>;
 198                         reg = <1>;
 199                         /* 8T49N287 - u182 */
 200                 };
 201
 202                 i2c@2 {
 203                         #address-cells = <1>;
 204                         #size-cells = <0>;
 205                         reg = <2>;
 206                         irps5401_43: irps5401@43 { /* IRPS5401 - u175 */
 207                                 compatible = "infineon,irps5401";
 208                                 reg = <0x43>; /* pmbus / i2c 0x13 */
 209                         };
 210                         irps5401_44: irps5401@44 { /* IRPS5401 - u180 */
 211                                 compatible = "infineon,irps5401";
 212                                 reg = <0x44>; /* pmbus / i2c 0x14 */
 213                         };
 214                 };
 215
 216                 i2c@3 {
 217                         #address-cells = <1>;
 218                         #size-cells = <0>;
 219                         reg = <3>;
 220                         u183: ina226@40 { /* u183 */
 221                                 compatible = "ti,ina226";
 222                                 #io-channel-cells = <1>;
 223                                 reg = <0x40>;
 224                                 shunt-resistor = <5000>;
 225                         };
 226                 };
 227
 228                 i2c@5 {
 229                         #address-cells = <1>;
 230                         #size-cells = <0>;
 231                         reg = <5>;
 232                 };
 233
 234                 i2c@7 {
 235                         #address-cells = <1>;
 236                         #size-cells = <0>;
 237                         reg = <7>;
 238                 };
 239
 240                 /* 4, 6 not connected */
 241         };
 242 };
 243
 244 &pinctrl0 {
 245         status = "okay";
 246
 247         pinctrl_can1_default: can1-default {
 248                 mux {
 249                         function = "can1";
 250                         groups = "can1_6_grp";
 251                 };
 252
 253                 conf {
 254                         groups = "can1_6_grp";
 255                         slew-rate = <SLEW_RATE_SLOW>;
 256                         power-source = <IO_STANDARD_LVCMOS18>;
 257                         drive-strength = <12>;
 258                 };
 259
 260                 conf-rx {
 261                         pins = "MIO25";
 262                         bias-high-impedance;
 263                 };
 264
 265                 conf-tx {
 266                         pins = "MIO24";
 267                         bias-disable;
 268                 };
 269         };
 270
 271         pinctrl_i2c1_default: i2c1-default {
 272                 mux {
 273                         groups = "i2c1_4_grp";
 274                         function = "i2c1";
 275                 };
 276
 277                 conf {
 278                         groups = "i2c1_4_grp";
 279                         bias-pull-up;
 280                         slew-rate = <SLEW_RATE_SLOW>;
 281                         power-source = <IO_STANDARD_LVCMOS18>;
 282                         drive-strength = <12>;
 283                 };
 284         };
 285
 286         pinctrl_i2c1_gpio: i2c1-gpio {
 287                 mux {
 288                         groups = "gpio0_16_grp", "gpio0_17_grp";
 289                         function = "gpio0";
 290                 };
 291
 292                 conf {
 293                         groups = "gpio0_16_grp", "gpio0_17_grp";
 294                         slew-rate = <SLEW_RATE_SLOW>;
 295                         power-source = <IO_STANDARD_LVCMOS18>;
 296                         drive-strength = <12>;
 297                 };
 298         };
 299
 300         pinctrl_gem3_default: gem3-default {
 301                 mux {
 302                         function = "ethernet3";
 303                         groups = "ethernet3_0_grp";
 304                 };
 305
 306                 conf {
 307                         groups = "ethernet3_0_grp";
 308                         slew-rate = <SLEW_RATE_SLOW>;
 309                         power-source = <IO_STANDARD_LVCMOS18>;
 310                         drive-strength = <12>;
 311                 };
 312
 313                 conf-rx {
 314                         pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
 315                                                                         "MIO75";
 316                         bias-high-impedance;
 317                         low-power-disable;
 318                 };
 319
 320                 conf-tx {
 321                         pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
 322                                                                         "MIO69";
 323                         bias-disable;
 324                         low-power-enable;
 325                 };
 326
 327                 mux-mdio {
 328                         function = "mdio3";
 329                         groups = "mdio3_0_grp";
 330                 };
 331
 332                 conf-mdio {
 333                         groups = "mdio3_0_grp";
 334                         slew-rate = <SLEW_RATE_SLOW>;
 335                         power-source = <IO_STANDARD_LVCMOS18>;
 336                         bias-disable;
 337                 };
 338         };
 339
 340         pinctrl_sdhci1_default: sdhci1-default {
 341                 mux {
 342                         groups = "sdio1_0_grp";
 343                         function = "sdio1";
 344                 };
 345
 346                 conf {
 347                         groups = "sdio1_0_grp";
 348                         slew-rate = <SLEW_RATE_SLOW>;
 349                         power-source = <IO_STANDARD_LVCMOS18>;
 350                         bias-disable;
 351                         drive-strength = <12>;
 352                 };
 353
 354                 mux-cd {
 355                         groups = "sdio1_cd_0_grp";
 356                         function = "sdio1_cd";
 357                 };
 358
 359                 conf-cd {
 360                         groups = "sdio1_cd_0_grp";
 361                         bias-high-impedance;
 362                         bias-pull-up;
 363                         slew-rate = <SLEW_RATE_SLOW>;
 364                         power-source = <IO_STANDARD_LVCMOS18>;
 365                 };
 366         };
 367
 368         pinctrl_uart0_default: uart0-default {
 369                 mux {
 370                         groups = "uart0_4_grp";
 371                         function = "uart0";
 372                 };
 373
 374                 conf {
 375                         groups = "uart0_4_grp";
 376                         slew-rate = <SLEW_RATE_SLOW>;
 377                         power-source = <IO_STANDARD_LVCMOS18>;
 378                         drive-strength = <12>;
 379                 };
 380
 381                 conf-rx {
 382                         pins = "MIO18";
 383                         bias-high-impedance;
 384                 };
 385
 386                 conf-tx {
 387                         pins = "MIO19";
 388                         bias-disable;
 389                 };
 390         };
 391
 392         pinctrl_uart1_default: uart1-default {
 393                 mux {
 394                         groups = "uart1_5_grp";
 395                         function = "uart1";
 396                 };
 397
 398                 conf {
 399                         groups = "uart1_5_grp";
 400                         slew-rate = <SLEW_RATE_SLOW>;
 401                         power-source = <IO_STANDARD_LVCMOS18>;
 402                         drive-strength = <12>;
 403                 };
 404
 405                 conf-rx {
 406                         pins = "MIO21";
 407                         bias-high-impedance;
 408                 };
 409
 410                 conf-tx {
 411                         pins = "MIO20";
 412                         bias-disable;
 413                 };
 414         };
 415
 416         pinctrl_usb0_default: usb0-default {
 417                 mux {
 418                         groups = "usb0_0_grp";
 419                         function = "usb0";
 420                 };
 421
 422                 conf {
 423                         groups = "usb0_0_grp";
 424                         power-source = <IO_STANDARD_LVCMOS18>;
 425                 };
 426
 427                 conf-rx {
 428                         pins = "MIO52", "MIO53", "MIO55";
 429                         bias-high-impedance;
 430                         drive-strength = <12>;
 431                         slew-rate = <SLEW_RATE_FAST>;
 432                 };
 433
 434                 conf-tx {
 435                         pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
 436                                "MIO60", "MIO61", "MIO62", "MIO63";
 437                         bias-disable;
 438                         drive-strength = <4>;
 439                         slew-rate = <SLEW_RATE_SLOW>;
 440                 };
 441         };
 442 };
 443
 444 &psgtr {
 445         status = "okay";
 446         /* nc, sata, usb3, dp */
 447         clocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>;
 448         clock-names = "ref1", "ref2", "ref3";
 449 };
 450
 451 &qspi {
 452         status = "okay";
 453         flash@0 {
 454                 compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */
 455                 #address-cells = <1>;
 456                 #size-cells = <1>;
 457                 reg = <0x0>;
 458                 spi-tx-bus-width = <4>;
 459                 spi-rx-bus-width = <4>;
 460                 spi-max-frequency = <108000000>; /* Based on DC1 spec */
 461                 partition@0 { /* for testing purpose */
 462                         label = "qspi-fsbl-uboot";
 463                         reg = <0x0 0x100000>;
 464                 };
 465                 partition@100000 { /* for testing purpose */
 466                         label = "qspi-linux";
 467                         reg = <0x100000 0x500000>;
 468                 };
 469                 partition@600000 { /* for testing purpose */
 470                         label = "qspi-device-tree";
 471                         reg = <0x600000 0x20000>;
 472                 };
 473                 partition@620000 { /* for testing purpose */
 474                         label = "qspi-rootfs";
 475                         reg = <0x620000 0x5E0000>;
 476                 };
 477         };
 478 };
 479
 480 &rtc {
 481         status = "okay";
 482 };
 483
 484 &sata {
 485         status = "okay";
 486         /* SATA OOB timing settings */
 487         ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
 488         ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
 489         ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 490         ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 491         ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
 492         ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
 493         ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 494         ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 495         phy-names = "sata-phy";
 496         phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
 497 };
 498
 499 /* SD1 with level shifter */
 500 &sdhci1 {
 501         status = "okay";
 502         no-1-8-v;
 503         pinctrl-names = "default";
 504         pinctrl-0 = <&pinctrl_sdhci1_default>;
 505         xlnx,mio-bank = <1>;
 506         disable-wp;
 507 };
 508
 509 &uart0 {
 510         status = "okay";
 511         pinctrl-names = "default";
 512         pinctrl-0 = <&pinctrl_uart0_default>;
 513 };
 514
 515 &uart1 {
 516         status = "okay";
 517         pinctrl-names = "default";
 518         pinctrl-0 = <&pinctrl_uart1_default>;
 519 };
 520
 521 /* ULPI SMSC USB3320 */
 522 &usb0 {
 523         status = "okay";
 524         pinctrl-names = "default";
 525         pinctrl-0 = <&pinctrl_usb0_default>;
 526         phy-names = "usb3-phy";
 527         phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
 528 };
 529
 530 &dwc3_0 {
 531         status = "okay";
 532         dr_mode = "host";
 533         snps,usb3_lpm_capable;
 534         maximum-speed = "super-speed";
 535 };
 536
 537 &watchdog0 {
 538         status = "okay";
 539 };
 540
 541 &xilinx_ams {
 542         status = "okay";
 543 };
 544
 545 &ams_ps {
 546         status = "okay";
 547 };
 548
 549 &ams_pl {
 550         status = "okay";
 551 };
 552
 553 &zynqmp_dpdma {
 554         status = "okay";
 555 };
 556
 557 &zynqmp_dpsub {
 558         status = "okay";
 559         phy-names = "dp-phy0", "dp-phy1";
 560         phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
 561                <&psgtr 0 PHY_TYPE_DP 1 3>;
 562 };