1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP ZCU104
5 * (C) Copyright 2017 - 2020, Xilinx, Inc.
7 * Michal Simek <michal.simek@xilinx.com>
12 #include "zynqmp.dtsi"
13 #include "zynqmp-clk-ccf.dtsi"
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/phy/phy.h>
18 model = "ZynqMP ZCU104 RevC";
19 compatible = "xlnx,zynqmp-zcu104-revC", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
35 bootargs = "earlycon";
36 stdout-path = "serial0:115200n8";
37 xlnx,eeprom = &eeprom;
41 device_type = "memory";
42 reg = <0x0 0x0 0x0 0x80000000>;
46 compatible = "iio-hwmon";
47 io-channels = <&u183 0>, <&u183 1>, <&u183 2>, <&u183 3>;
94 phy-mode = "rgmii-id";
95 phy0: ethernet-phy@c {
97 ti,rx-internal-delay = <0x8>;
98 ti,tx-internal-delay = <0xa>;
99 ti,fifo-depth = <0x1>;
100 ti,dp83867-rxctrl-strap-quirk;
114 clock-frequency = <400000>;
116 tca6416_u97: gpio@20 {
117 compatible = "ti,tca6416";
124 * 0 - IRPS5401_ALERT_B
125 * 1 - HDMI_8T49N241_INT_ALM
127 * 3 - MAX6643_FANFAIL_B
128 * 5 - IIC_MUX_RESET_B
129 * 6 - GEM3_EXP_RESET_B
130 * 7 - FMC_LPC_PRSNT_M2C_B
131 * 4, 10 - 17 - not connected
135 /* Another connection to this bus via PL i2c via PCA9306 - u45 */
136 i2c-mux@74 { /* u34 */
137 compatible = "nxp,pca9548";
138 #address-cells = <1>;
142 #address-cells = <1>;
146 * IIC_EEPROM 1kB memory which uses 256B blocks
147 * where every block has different address.
148 * 0 - 256B address 0x54
149 * 256B - 512B address 0x55
150 * 512B - 768B address 0x56
151 * 768B - 1024B address 0x57
153 eeprom: eeprom@54 { /* u23 */
154 compatible = "atmel,24c08";
156 #address-cells = <1>;
162 #address-cells = <1>;
165 clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */
166 compatible = "idt,8t49n287";
172 #address-cells = <1>;
175 irps5401_43: irps54012@43 { /* IRPS5401 - u175 */
177 compatible = "infineon,irps5401";
180 irps5401_4d: irps54012@4d { /* IRPS5401 - u180 */
182 compatible = "infineon,irps5401";
188 #address-cells = <1>;
191 u183: ina226@40 { /* u183 */
192 compatible = "ti,ina226";
193 #io-channel-cells = <1>;
195 shunt-resistor = <5000>;
200 #address-cells = <1>;
206 #address-cells = <1>;
211 /* 4, 6 not connected */
218 compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */
219 #address-cells = <1>;
222 spi-tx-bus-width = <1>;
223 spi-rx-bus-width = <4>;
224 spi-max-frequency = <108000000>; /* Based on DC1 spec */
225 partition@0 { /* for testing purpose */
226 label = "qspi-fsbl-uboot";
227 reg = <0x0 0x100000>;
229 partition@100000 { /* for testing purpose */
230 label = "qspi-linux";
231 reg = <0x100000 0x500000>;
233 partition@600000 { /* for testing purpose */
234 label = "qspi-device-tree";
235 reg = <0x600000 0x20000>;
237 partition@620000 { /* for testing purpose */
238 label = "qspi-rootfs";
239 reg = <0x620000 0x5E0000>;
250 /* SATA OOB timing settings */
251 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
252 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
253 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
254 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
255 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
256 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
257 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
258 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
259 phy-names = "sata-phy";
260 phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;
263 /* SD1 with level shifter */
283 /* ULPI SMSC USB3320 */
291 snps,usb3_lpm_capable;
292 phy-names = "usb3-phy";
293 phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
294 maximum-speed = "super-speed";