arch/arm/dts/zynqmp-zcu104-revC.dts

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * dts file for Xilinx ZynqMP ZCU104
   4  *
   5  * (C) Copyright 2017 - 2018, Xilinx, Inc.
   6  *
   7  * Michal Simek <michal.simek@xilinx.com>
   8  */
   9
  10 /dts-v1/;
  11
  12 #include "zynqmp.dtsi"
  13 #include "zynqmp-clk-ccf.dtsi"
  14 #include <dt-bindings/gpio/gpio.h>
  15 #include <dt-bindings/phy/phy.h>
  16
  17 / {
  18         model = "ZynqMP ZCU104 RevC";
  19         compatible = "xlnx,zynqmp-zcu104-revC", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
  20
  21         aliases {
  22                 ethernet0 = &gem3;
  23                 gpio0 = &gpio;
  24                 i2c0 = &i2c1;
  25                 mmc0 = &sdhci1;
  26                 rtc0 = &rtc;
  27                 serial0 = &uart0;
  28                 serial1 = &uart1;
  29                 serial2 = &dcc;
  30                 spi0 = &qspi;
  31                 usb0 = &usb0;
  32         };
  33
  34         chosen {
  35                 bootargs = "earlycon";
  36                 stdout-path = "serial0:115200n8";
  37                 xlnx,eeprom = &eeprom;
  38         };
  39
  40         memory@0 {
  41                 device_type = "memory";
  42                 reg = <0x0 0x0 0x0 0x80000000>;
  43         };
  44
  45         ina226 {
  46                 compatible = "iio-hwmon";
  47                 io-channels = <&u183 0>, <&u183 1>, <&u183 2>, <&u183 3>;
  48         };
  49 };
  50
  51 &can1 {
  52         status = "okay";
  53 };
  54
  55 &dcc {
  56         status = "okay";
  57 };
  58
  59 &gem3 {
  60         status = "okay";
  61         phy-handle = <&phy0>;
  62         phy-mode = "rgmii-id";
  63         phy0: ethernet-phy@c {
  64                 reg = <0xc>;
  65                 ti,rx-internal-delay = <0x8>;
  66                 ti,tx-internal-delay = <0xa>;
  67                 ti,fifo-depth = <0x1>;
  68         };
  69 };
  70
  71 &gpio {
  72         status = "okay";
  73 };
  74
  75 &gpu {
  76         status = "okay";
  77 };
  78
  79 &i2c1 {
  80         status = "okay";
  81         clock-frequency = <400000>;
  82
  83         tca6416_u97: gpio@20 {
  84                 compatible = "ti,tca6416";
  85                 reg = <0x20>;
  86                 gpio-controller;
  87                 #gpio-cells = <2>;
  88                 /*
  89                  * IRQ not connected
  90                  * Lines:
  91                  * 0 - IRPS5401_ALERT_B
  92                  * 1 - HDMI_8T49N241_INT_ALM
  93                  * 2 - MAX6643_OT_B
  94                  * 3 - MAX6643_FANFAIL_B
  95                  * 5 - IIC_MUX_RESET_B
  96                  * 6 - GEM3_EXP_RESET_B
  97                  * 7 - FMC_LPC_PRSNT_M2C_B
  98                  * 4, 10 - 17 - not connected
  99                  */
 100         };
 101
 102         /* Another connection to this bus via PL i2c via PCA9306 - u45 */
 103         i2c-mux@74 { /* u34 */
 104                 compatible = "nxp,pca9548";
 105                 #address-cells = <1>;
 106                 #size-cells = <0>;
 107                 reg = <0x74>;
 108                 i2c@0 {
 109                         #address-cells = <1>;
 110                         #size-cells = <0>;
 111                         reg = <0>;
 112                         /*
 113                          * IIC_EEPROM 1kB memory which uses 256B blocks
 114                          * where every block has different address.
 115                          *    0 - 256B address 0x54
 116                          * 256B - 512B address 0x55
 117                          * 512B - 768B address 0x56
 118                          * 768B - 1024B address 0x57
 119                          */
 120                         eeprom: eeprom@54 { /* u23 */
 121                                 compatible = "atmel,24c08";
 122                                 reg = <0x54>;
 123                                 #address-cells = <1>;
 124                                 #size-cells = <1>;
 125                         };
 126                 };
 127
 128                 i2c@1 {
 129                         #address-cells = <1>;
 130                         #size-cells = <0>;
 131                         reg = <1>;
 132                         clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */
 133                                 compatible = "idt,8t49n287";
 134                                 reg = <0x6c>;
 135                         };
 136                 };
 137
 138                 i2c@2 {
 139                         #address-cells = <1>;
 140                         #size-cells = <0>;
 141                         reg = <2>;
 142                         irps5401_43: irps54012@43 { /* IRPS5401 - u175 */
 143                                 #clock-cells = <0>;
 144                                 compatible = "infineon,irps5401";
 145                                 reg = <0x43>;
 146                         };
 147                         irps5401_4d: irps54012@4d { /* IRPS5401 - u180 */
 148                                 #clock-cells = <0>;
 149                                 compatible = "infineon,irps5401";
 150                                 reg = <0x4d>;
 151                         };
 152                 };
 153
 154                 i2c@3 {
 155                         #address-cells = <1>;
 156                         #size-cells = <0>;
 157                         reg = <3>;
 158                         u183: ina226@40 { /* u183 */
 159                                 compatible = "ti,ina226";
 160                                 #io-channel-cells = <1>;
 161                                 reg = <0x40>;
 162                                 shunt-resistor = <5000>;
 163                         };
 164                 };
 165
 166                 i2c@5 {
 167                         #address-cells = <1>;
 168                         #size-cells = <0>;
 169                         reg = <5>;
 170                 };
 171
 172                 i2c@7 {
 173                         #address-cells = <1>;
 174                         #size-cells = <0>;
 175                         reg = <7>;
 176                 };
 177
 178                 /* 4, 6 not connected */
 179         };
 180 };
 181
 182 &qspi {
 183         status = "okay";
 184         flash@0 {
 185                 compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */
 186                 #address-cells = <1>;
 187                 #size-cells = <1>;
 188                 reg = <0x0>;
 189                 spi-tx-bus-width = <1>;
 190                 spi-rx-bus-width = <4>;
 191                 spi-max-frequency = <108000000>; /* Based on DC1 spec */
 192                 partition@qspi-fsbl-uboot { /* for testing purpose */
 193                         label = "qspi-fsbl-uboot";
 194                         reg = <0x0 0x100000>;
 195                 };
 196                 partition@qspi-linux { /* for testing purpose */
 197                         label = "qspi-linux";
 198                         reg = <0x100000 0x500000>;
 199                 };
 200                 partition@qspi-device-tree { /* for testing purpose */
 201                         label = "qspi-device-tree";
 202                         reg = <0x600000 0x20000>;
 203                 };
 204                 partition@qspi-rootfs { /* for testing purpose */
 205                         label = "qspi-rootfs";
 206                         reg = <0x620000 0x5E0000>;
 207                 };
 208         };
 209 };
 210
 211 &rtc {
 212         status = "okay";
 213 };
 214
 215 &sata {
 216         status = "okay";
 217         /* SATA OOB timing settings */
 218         ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
 219         ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
 220         ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 221         ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 222         ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
 223         ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
 224         ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 225         ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 226         phy-names = "sata-phy";
 227         phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;
 228 };
 229
 230 /* SD1 with level shifter */
 231 &sdhci1 {
 232         status = "okay";
 233         no-1-8-v;
 234         xlnx,mio_bank = <1>;
 235         disable-wp;
 236 };
 237
 238 &serdes {
 239         status = "okay";
 240 };
 241
 242 &uart0 {
 243         status = "okay";
 244 };
 245
 246 &uart1 {
 247         status = "okay";
 248 };
 249
 250 /* ULPI SMSC USB3320 */
 251 &usb0 {
 252         status = "okay";
 253 };
 254
 255 &dwc3_0 {
 256         status = "okay";
 257         dr_mode = "host";
 258         snps,usb3_lpm_capable;
 259         phy-names = "usb3-phy";
 260         phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
 261         maximum-speed = "super-speed";
 262 };
 263
 264 &watchdog0 {
 265         status = "okay";
 266 };
 267
 268 &xilinx_ams {
 269         status = "okay";
 270 };
 271
 272 &ams_ps {
 273         status = "okay";
 274 };
 275
 276 &ams_pl {
 277         status = "okay";
 278 };