arch/arm/dts/zynqmp-zcu104-revC.dts

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * dts file for Xilinx ZynqMP ZCU104
   4  *
   5  * (C) Copyright 2017 - 2020, Xilinx, Inc.
   6  *
   7  * Michal Simek <michal.simek@xilinx.com>
   8  */
   9
  10 /dts-v1/;
  11
  12 #include "zynqmp.dtsi"
  13 #include "zynqmp-clk-ccf.dtsi"
  14 #include <dt-bindings/gpio/gpio.h>
  15 #include <dt-bindings/phy/phy.h>
  16
  17 / {
  18         model = "ZynqMP ZCU104 RevC";
  19         compatible = "xlnx,zynqmp-zcu104-revC", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
  20
  21         aliases {
  22                 ethernet0 = &gem3;
  23                 gpio0 = &gpio;
  24                 i2c0 = &i2c1;
  25                 mmc0 = &sdhci1;
  26                 rtc0 = &rtc;
  27                 serial0 = &uart0;
  28                 serial1 = &uart1;
  29                 serial2 = &dcc;
  30                 spi0 = &qspi;
  31                 usb0 = &usb0;
  32         };
  33
  34         chosen {
  35                 bootargs = "earlycon";
  36                 stdout-path = "serial0:115200n8";
  37                 xlnx,eeprom = &eeprom;
  38         };
  39
  40         memory@0 {
  41                 device_type = "memory";
  42                 reg = <0x0 0x0 0x0 0x80000000>;
  43         };
  44
  45         ina226 {
  46                 compatible = "iio-hwmon";
  47                 io-channels = <&u183 0>, <&u183 1>, <&u183 2>, <&u183 3>;
  48         };
  49 };
  50
  51 &can1 {
  52         status = "okay";
  53 };
  54
  55 &dcc {
  56         status = "okay";
  57 };
  58
  59 &fpd_dma_chan1 {
  60         status = "okay";
  61 };
  62
  63 &fpd_dma_chan2 {
  64         status = "okay";
  65 };
  66
  67 &fpd_dma_chan3 {
  68         status = "okay";
  69 };
  70
  71 &fpd_dma_chan4 {
  72         status = "okay";
  73 };
  74
  75 &fpd_dma_chan5 {
  76         status = "okay";
  77 };
  78
  79 &fpd_dma_chan6 {
  80         status = "okay";
  81 };
  82
  83 &fpd_dma_chan7 {
  84         status = "okay";
  85 };
  86
  87 &fpd_dma_chan8 {
  88         status = "okay";
  89 };
  90
  91 &gem3 {
  92         status = "okay";
  93         phy-handle = <&phy0>;
  94         phy-mode = "rgmii-id";
  95         phy0: ethernet-phy@c {
  96                 reg = <0xc>;
  97                 ti,rx-internal-delay = <0x8>;
  98                 ti,tx-internal-delay = <0xa>;
  99                 ti,fifo-depth = <0x1>;
 100                 ti,dp83867-rxctrl-strap-quirk;
 101         };
 102 };
 103
 104 &gpio {
 105         status = "okay";
 106 };
 107
 108 &gpu {
 109         status = "okay";
 110 };
 111
 112 &i2c1 {
 113         status = "okay";
 114         clock-frequency = <400000>;
 115
 116         tca6416_u97: gpio@20 {
 117                 compatible = "ti,tca6416";
 118                 reg = <0x20>;
 119                 gpio-controller;
 120                 #gpio-cells = <2>;
 121                 /*
 122                  * IRQ not connected
 123                  * Lines:
 124                  * 0 - IRPS5401_ALERT_B
 125                  * 1 - HDMI_8T49N241_INT_ALM
 126                  * 2 - MAX6643_OT_B
 127                  * 3 - MAX6643_FANFAIL_B
 128                  * 5 - IIC_MUX_RESET_B
 129                  * 6 - GEM3_EXP_RESET_B
 130                  * 7 - FMC_LPC_PRSNT_M2C_B
 131                  * 4, 10 - 17 - not connected
 132                  */
 133         };
 134
 135         /* Another connection to this bus via PL i2c via PCA9306 - u45 */
 136         i2c-mux@74 { /* u34 */
 137                 compatible = "nxp,pca9548";
 138                 #address-cells = <1>;
 139                 #size-cells = <0>;
 140                 reg = <0x74>;
 141                 i2c@0 {
 142                         #address-cells = <1>;
 143                         #size-cells = <0>;
 144                         reg = <0>;
 145                         /*
 146                          * IIC_EEPROM 1kB memory which uses 256B blocks
 147                          * where every block has different address.
 148                          *    0 - 256B address 0x54
 149                          * 256B - 512B address 0x55
 150                          * 512B - 768B address 0x56
 151                          * 768B - 1024B address 0x57
 152                          */
 153                         eeprom: eeprom@54 { /* u23 */
 154                                 compatible = "atmel,24c08";
 155                                 reg = <0x54>;
 156                                 #address-cells = <1>;
 157                                 #size-cells = <1>;
 158                         };
 159                 };
 160
 161                 i2c@1 {
 162                         #address-cells = <1>;
 163                         #size-cells = <0>;
 164                         reg = <1>;
 165                         clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */
 166                                 compatible = "idt,8t49n287";
 167                                 reg = <0x6c>;
 168                         };
 169                 };
 170
 171                 i2c@2 {
 172                         #address-cells = <1>;
 173                         #size-cells = <0>;
 174                         reg = <2>;
 175                         irps5401_43: irps54012@43 { /* IRPS5401 - u175 */
 176                                 #clock-cells = <0>;
 177                                 compatible = "infineon,irps5401";
 178                                 reg = <0x43>;
 179                         };
 180                         irps5401_4d: irps54012@4d { /* IRPS5401 - u180 */
 181                                 #clock-cells = <0>;
 182                                 compatible = "infineon,irps5401";
 183                                 reg = <0x4d>;
 184                         };
 185                 };
 186
 187                 i2c@3 {
 188                         #address-cells = <1>;
 189                         #size-cells = <0>;
 190                         reg = <3>;
 191                         u183: ina226@40 { /* u183 */
 192                                 compatible = "ti,ina226";
 193                                 #io-channel-cells = <1>;
 194                                 reg = <0x40>;
 195                                 shunt-resistor = <5000>;
 196                         };
 197                 };
 198
 199                 i2c@5 {
 200                         #address-cells = <1>;
 201                         #size-cells = <0>;
 202                         reg = <5>;
 203                 };
 204
 205                 i2c@7 {
 206                         #address-cells = <1>;
 207                         #size-cells = <0>;
 208                         reg = <7>;
 209                 };
 210
 211                 /* 4, 6 not connected */
 212         };
 213 };
 214
 215 &qspi {
 216         status = "okay";
 217         flash@0 {
 218                 compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */
 219                 #address-cells = <1>;
 220                 #size-cells = <1>;
 221                 reg = <0x0>;
 222                 spi-tx-bus-width = <1>;
 223                 spi-rx-bus-width = <4>;
 224                 spi-max-frequency = <108000000>; /* Based on DC1 spec */
 225                 partition@0 { /* for testing purpose */
 226                         label = "qspi-fsbl-uboot";
 227                         reg = <0x0 0x100000>;
 228                 };
 229                 partition@100000 { /* for testing purpose */
 230                         label = "qspi-linux";
 231                         reg = <0x100000 0x500000>;
 232                 };
 233                 partition@600000 { /* for testing purpose */
 234                         label = "qspi-device-tree";
 235                         reg = <0x600000 0x20000>;
 236                 };
 237                 partition@620000 { /* for testing purpose */
 238                         label = "qspi-rootfs";
 239                         reg = <0x620000 0x5E0000>;
 240                 };
 241         };
 242 };
 243
 244 &rtc {
 245         status = "okay";
 246 };
 247
 248 &sata {
 249         status = "okay";
 250         /* SATA OOB timing settings */
 251         ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
 252         ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
 253         ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 254         ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 255         ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
 256         ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
 257         ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 258         ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 259         phy-names = "sata-phy";
 260         phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;
 261 };
 262
 263 /* SD1 with level shifter */
 264 &sdhci1 {
 265         status = "okay";
 266         no-1-8-v;
 267         xlnx,mio_bank = <1>;
 268         disable-wp;
 269 };
 270
 271 &serdes {
 272         status = "okay";
 273 };
 274
 275 &uart0 {
 276         status = "okay";
 277 };
 278
 279 &uart1 {
 280         status = "okay";
 281 };
 282
 283 /* ULPI SMSC USB3320 */
 284 &usb0 {
 285         status = "okay";
 286 };
 287
 288 &dwc3_0 {
 289         status = "okay";
 290         dr_mode = "host";
 291         snps,usb3_lpm_capable;
 292         phy-names = "usb3-phy";
 293         phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
 294         maximum-speed = "super-speed";
 295 };
 296
 297 &watchdog0 {
 298         status = "okay";
 299 };
 300
 301 &xilinx_ams {
 302         status = "okay";
 303 };
 304
 305 &ams_ps {
 306         status = "okay";
 307 };
 308
 309 &ams_pl {
 310         status = "okay";
 311 };