arch/arm/dts/zynqmp-zcu104-revA.dts

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * dts file for Xilinx ZynqMP ZCU104
   4  *
   5  * (C) Copyright 2017 - 2021, Xilinx, Inc.
   6  *
   7  * Michal Simek <michal.simek@xilinx.com>
   8  */
   9
  10 /dts-v1/;
  11
  12 #include "zynqmp.dtsi"
  13 #include "zynqmp-clk-ccf.dtsi"
  14 #include <dt-bindings/gpio/gpio.h>
  15 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
  16 #include <dt-bindings/phy/phy.h>
  17
  18 / {
  19         model = "ZynqMP ZCU104 RevA";
  20         compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
  21
  22         aliases {
  23                 ethernet0 = &gem3;
  24                 i2c0 = &i2c1;
  25                 mmc0 = &sdhci1;
  26                 nvmem0 = &eeprom;
  27                 rtc0 = &rtc;
  28                 serial0 = &uart0;
  29                 serial1 = &uart1;
  30                 serial2 = &dcc;
  31                 spi0 = &qspi;
  32                 usb0 = &usb0;
  33         };
  34
  35         chosen {
  36                 bootargs = "earlycon";
  37                 stdout-path = "serial0:115200n8";
  38         };
  39
  40         memory@0 {
  41                 device_type = "memory";
  42                 reg = <0x0 0x0 0x0 0x80000000>;
  43         };
  44
  45         clock_8t49n287_5: clk125 {
  46                 compatible = "fixed-clock";
  47                 #clock-cells = <0>;
  48                 clock-frequency = <125000000>;
  49         };
  50
  51         clock_8t49n287_2: clk26 {
  52                 compatible = "fixed-clock";
  53                 #clock-cells = <0>;
  54                 clock-frequency = <26000000>;
  55         };
  56
  57         clock_8t49n287_3: clk27 {
  58                 compatible = "fixed-clock";
  59                 #clock-cells = <0>;
  60                 clock-frequency = <27000000>;
  61         };
  62 };
  63
  64 &can1 {
  65         status = "okay";
  66         pinctrl-names = "default";
  67         pinctrl-0 = <&pinctrl_can1_default>;
  68 };
  69
  70 &dcc {
  71         status = "okay";
  72 };
  73
  74 &fpd_dma_chan1 {
  75         status = "okay";
  76 };
  77
  78 &fpd_dma_chan2 {
  79         status = "okay";
  80 };
  81
  82 &fpd_dma_chan3 {
  83         status = "okay";
  84 };
  85
  86 &fpd_dma_chan4 {
  87         status = "okay";
  88 };
  89
  90 &fpd_dma_chan5 {
  91         status = "okay";
  92 };
  93
  94 &fpd_dma_chan6 {
  95         status = "okay";
  96 };
  97
  98 &fpd_dma_chan7 {
  99         status = "okay";
 100 };
 101
 102 &fpd_dma_chan8 {
 103         status = "okay";
 104 };
 105
 106 &gem3 {
 107         status = "okay";
 108         phy-handle = <&phy0>;
 109         phy-mode = "rgmii-id";
 110         pinctrl-names = "default";
 111         pinctrl-0 = <&pinctrl_gem3_default>;
 112         phy0: ethernet-phy@c {
 113                 reg = <0xc>;
 114                 ti,rx-internal-delay = <0x8>;
 115                 ti,tx-internal-delay = <0xa>;
 116                 ti,fifo-depth = <0x1>;
 117                 ti,dp83867-rxctrl-strap-quirk;
 118         };
 119 };
 120
 121 &gpio {
 122         status = "okay";
 123 };
 124
 125 &gpu {
 126         status = "okay";
 127 };
 128
 129 &i2c1 {
 130         status = "okay";
 131         clock-frequency = <400000>;
 132         pinctrl-names = "default", "gpio";
 133         pinctrl-0 = <&pinctrl_i2c1_default>;
 134         pinctrl-1 = <&pinctrl_i2c1_gpio>;
 135         scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
 136         sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
 137
 138         /* Another connection to this bus via PL i2c via PCA9306 - u45 */
 139         i2c-mux@74 { /* u34 */
 140                 compatible = "nxp,pca9548";
 141                 #address-cells = <1>;
 142                 #size-cells = <0>;
 143                 reg = <0x74>;
 144                 i2c@0 {
 145                         #address-cells = <1>;
 146                         #size-cells = <0>;
 147                         reg = <0>;
 148                         /*
 149                          * IIC_EEPROM 1kB memory which uses 256B blocks
 150                          * where every block has different address.
 151                          *    0 - 256B address 0x54
 152                          * 256B - 512B address 0x55
 153                          * 512B - 768B address 0x56
 154                          * 768B - 1024B address 0x57
 155                          */
 156                         eeprom: eeprom@54 { /* u23 */
 157                                 compatible = "atmel,24c08";
 158                                 reg = <0x54>;
 159                                 #address-cells = <1>;
 160                                 #size-cells = <1>;
 161                         };
 162                 };
 163
 164                 i2c@1 {
 165                         #address-cells = <1>;
 166                         #size-cells = <0>;
 167                         reg = <1>;
 168                         /* 8T49N287 - u182 */
 169                 };
 170
 171                 i2c@2 {
 172                         #address-cells = <1>;
 173                         #size-cells = <0>;
 174                         reg = <2>;
 175                         irps5401_43: irps5401@43 { /* IRPS5401 - u175 */
 176                                 compatible = "infineon,irps5401";
 177                                 reg = <0x43>; /* pmbus / i2c 0x13 */
 178                         };
 179                         irps5401_44: irps5401@44 { /* IRPS5401 - u180 */
 180                                 compatible = "infineon,irps5401";
 181                                 reg = <0x44>; /* pmbus / i2c 0x14 */
 182                         };
 183                 };
 184
 185                 i2c@4 {
 186                         #address-cells = <1>;
 187                         #size-cells = <0>;
 188                         reg = <4>;
 189                         tca6416_u97: gpio@20 {
 190                                 compatible = "ti,tca6416";
 191                                 reg = <0x20>;
 192                                 gpio-controller;
 193                                 #gpio-cells = <2>;
 194                                 /*
 195                                  * IRQ not connected
 196                                  * Lines:
 197                                  * 0 - IRPS5401_ALERT_B
 198                                  * 1 - HDMI_8T49N241_INT_ALM
 199                                  * 2 - MAX6643_OT_B
 200                                  * 3 - MAX6643_FANFAIL_B
 201                                  * 5 - IIC_MUX_RESET_B
 202                                  * 6 - GEM3_EXP_RESET_B
 203                                  * 7 - FMC_LPC_PRSNT_M2C_B
 204                                  * 4, 10 - 17 - not connected
 205                                  */
 206                         };
 207                 };
 208
 209                 i2c@5 {
 210                         #address-cells = <1>;
 211                         #size-cells = <0>;
 212                         reg = <5>;
 213                 };
 214
 215                 i2c@7 {
 216                         #address-cells = <1>;
 217                         #size-cells = <0>;
 218                         reg = <7>;
 219                 };
 220
 221                 /* 3, 6 not connected */
 222         };
 223 };
 224
 225 &pinctrl0 {
 226         status = "okay";
 227
 228         pinctrl_can1_default: can1-default {
 229                 mux {
 230                         function = "can1";
 231                         groups = "can1_6_grp";
 232                 };
 233
 234                 conf {
 235                         groups = "can1_6_grp";
 236                         slew-rate = <SLEW_RATE_SLOW>;
 237                         power-source = <IO_STANDARD_LVCMOS18>;
 238                         drive-strength = <12>;
 239                 };
 240
 241                 conf-rx {
 242                         pins = "MIO25";
 243                         bias-high-impedance;
 244                 };
 245
 246                 conf-tx {
 247                         pins = "MIO24";
 248                         bias-disable;
 249                 };
 250         };
 251
 252         pinctrl_i2c1_default: i2c1-default {
 253                 mux {
 254                         groups = "i2c1_4_grp";
 255                         function = "i2c1";
 256                 };
 257
 258                 conf {
 259                         groups = "i2c1_4_grp";
 260                         bias-pull-up;
 261                         slew-rate = <SLEW_RATE_SLOW>;
 262                         power-source = <IO_STANDARD_LVCMOS18>;
 263                         drive-strength = <12>;
 264                 };
 265         };
 266
 267         pinctrl_i2c1_gpio: i2c1-gpio {
 268                 mux {
 269                         groups = "gpio0_16_grp", "gpio0_17_grp";
 270                         function = "gpio0";
 271                 };
 272
 273                 conf {
 274                         groups = "gpio0_16_grp", "gpio0_17_grp";
 275                         slew-rate = <SLEW_RATE_SLOW>;
 276                         power-source = <IO_STANDARD_LVCMOS18>;
 277                         drive-strength = <12>;
 278                 };
 279         };
 280
 281         pinctrl_gem3_default: gem3-default {
 282                 mux {
 283                         function = "ethernet3";
 284                         groups = "ethernet3_0_grp";
 285                 };
 286
 287                 conf {
 288                         groups = "ethernet3_0_grp";
 289                         slew-rate = <SLEW_RATE_SLOW>;
 290                         power-source = <IO_STANDARD_LVCMOS18>;
 291                         drive-strength = <12>;
 292                 };
 293
 294                 conf-rx {
 295                         pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
 296                                                                         "MIO75";
 297                         bias-high-impedance;
 298                         low-power-disable;
 299                 };
 300
 301                 conf-tx {
 302                         pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
 303                                                                         "MIO69";
 304                         bias-disable;
 305                         low-power-enable;
 306                 };
 307
 308                 mux-mdio {
 309                         function = "mdio3";
 310                         groups = "mdio3_0_grp";
 311                 };
 312
 313                 conf-mdio {
 314                         groups = "mdio3_0_grp";
 315                         slew-rate = <SLEW_RATE_SLOW>;
 316                         power-source = <IO_STANDARD_LVCMOS18>;
 317                         bias-disable;
 318                 };
 319         };
 320
 321         pinctrl_sdhci1_default: sdhci1-default {
 322                 mux {
 323                         groups = "sdio1_0_grp";
 324                         function = "sdio1";
 325                 };
 326
 327                 conf {
 328                         groups = "sdio1_0_grp";
 329                         slew-rate = <SLEW_RATE_SLOW>;
 330                         power-source = <IO_STANDARD_LVCMOS18>;
 331                         bias-disable;
 332                         drive-strength = <12>;
 333                 };
 334
 335                 mux-cd {
 336                         groups = "sdio1_cd_0_grp";
 337                         function = "sdio1_cd";
 338                 };
 339
 340                 conf-cd {
 341                         groups = "sdio1_cd_0_grp";
 342                         bias-high-impedance;
 343                         bias-pull-up;
 344                         slew-rate = <SLEW_RATE_SLOW>;
 345                         power-source = <IO_STANDARD_LVCMOS18>;
 346                 };
 347         };
 348
 349         pinctrl_uart0_default: uart0-default {
 350                 mux {
 351                         groups = "uart0_4_grp";
 352                         function = "uart0";
 353                 };
 354
 355                 conf {
 356                         groups = "uart0_4_grp";
 357                         slew-rate = <SLEW_RATE_SLOW>;
 358                         power-source = <IO_STANDARD_LVCMOS18>;
 359                         drive-strength = <12>;
 360                 };
 361
 362                 conf-rx {
 363                         pins = "MIO18";
 364                         bias-high-impedance;
 365                 };
 366
 367                 conf-tx {
 368                         pins = "MIO19";
 369                         bias-disable;
 370                 };
 371         };
 372
 373         pinctrl_uart1_default: uart1-default {
 374                 mux {
 375                         groups = "uart1_5_grp";
 376                         function = "uart1";
 377                 };
 378
 379                 conf {
 380                         groups = "uart1_5_grp";
 381                         slew-rate = <SLEW_RATE_SLOW>;
 382                         power-source = <IO_STANDARD_LVCMOS18>;
 383                         drive-strength = <12>;
 384                 };
 385
 386                 conf-rx {
 387                         pins = "MIO21";
 388                         bias-high-impedance;
 389                 };
 390
 391                 conf-tx {
 392                         pins = "MIO20";
 393                         bias-disable;
 394                 };
 395         };
 396
 397         pinctrl_usb0_default: usb0-default {
 398                 mux {
 399                         groups = "usb0_0_grp";
 400                         function = "usb0";
 401                 };
 402
 403                 conf {
 404                         groups = "usb0_0_grp";
 405                         slew-rate = <SLEW_RATE_SLOW>;
 406                         power-source = <IO_STANDARD_LVCMOS18>;
 407                         drive-strength = <12>;
 408                 };
 409
 410                 conf-rx {
 411                         pins = "MIO52", "MIO53", "MIO55";
 412                         bias-high-impedance;
 413                 };
 414
 415                 conf-tx {
 416                         pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
 417                                "MIO60", "MIO61", "MIO62", "MIO63";
 418                         bias-disable;
 419                 };
 420         };
 421 };
 422
 423 &psgtr {
 424         status = "okay";
 425         /* nc, sata, usb3, dp */
 426         clocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>;
 427         clock-names = "ref1", "ref2", "ref3";
 428 };
 429
 430 &qspi {
 431         status = "okay";
 432         flash@0 {
 433                 compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */
 434                 #address-cells = <1>;
 435                 #size-cells = <1>;
 436                 reg = <0x0>;
 437                 spi-tx-bus-width = <1>;
 438                 spi-rx-bus-width = <4>;
 439                 spi-max-frequency = <108000000>; /* Based on DC1 spec */
 440                 partition@0 { /* for testing purpose */
 441                         label = "qspi-fsbl-uboot";
 442                         reg = <0x0 0x100000>;
 443                 };
 444                 partition@100000 { /* for testing purpose */
 445                         label = "qspi-linux";
 446                         reg = <0x100000 0x500000>;
 447                 };
 448                 partition@600000 { /* for testing purpose */
 449                         label = "qspi-device-tree";
 450                         reg = <0x600000 0x20000>;
 451                 };
 452                 partition@620000 { /* for testing purpose */
 453                         label = "qspi-rootfs";
 454                         reg = <0x620000 0x5E0000>;
 455                 };
 456         };
 457 };
 458
 459 &rtc {
 460         status = "okay";
 461 };
 462
 463 &sata {
 464         status = "okay";
 465         /* SATA OOB timing settings */
 466         ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
 467         ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
 468         ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 469         ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 470         ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
 471         ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
 472         ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 473         ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 474         phy-names = "sata-phy";
 475         phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
 476 };
 477
 478 /* SD1 with level shifter */
 479 &sdhci1 {
 480         status = "okay";
 481         no-1-8-v;
 482         pinctrl-names = "default";
 483         pinctrl-0 = <&pinctrl_sdhci1_default>;
 484         xlnx,mio-bank = <1>;
 485         disable-wp;
 486 };
 487
 488 &uart0 {
 489         status = "okay";
 490         pinctrl-names = "default";
 491         pinctrl-0 = <&pinctrl_uart0_default>;
 492 };
 493
 494 &uart1 {
 495         status = "okay";
 496         pinctrl-names = "default";
 497         pinctrl-0 = <&pinctrl_uart1_default>;
 498 };
 499
 500 /* ULPI SMSC USB3320 */
 501 &usb0 {
 502         status = "okay";
 503         pinctrl-names = "default";
 504         pinctrl-0 = <&pinctrl_usb0_default>;
 505 };
 506
 507 &dwc3_0 {
 508         status = "okay";
 509         dr_mode = "host";
 510         snps,usb3_lpm_capable;
 511         phy-names = "usb3-phy";
 512         phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
 513         maximum-speed = "super-speed";
 514 };
 515
 516 &watchdog0 {
 517         status = "okay";
 518 };
 519
 520 &xilinx_ams {
 521         status = "okay";
 522 };
 523
 524 &ams_ps {
 525         status = "okay";
 526 };
 527
 528 &ams_pl {
 529         status = "okay";
 530 };
 531
 532 &zynqmp_dpdma {
 533         status = "okay";
 534 };
 535
 536 &zynqmp_dpsub {
 537         status = "okay";
 538         phy-names = "dp-phy0", "dp-phy1";
 539         phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
 540                <&psgtr 0 PHY_TYPE_DP 1 3>;
 541 };