2 * dts file for Xilinx ZynqMP ZCU102 RevA
4 * (C) Copyright 2015, Xilinx, Inc.
6 * Michal Simek <michal.simek@xilinx.com>
8 * SPDX-License-Identifier: GPL-2.0+
13 #include "zynqmp.dtsi"
14 #include "zynqmp-clk.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
17 #include <dt-bindings/phy/phy.h>
20 model = "ZynqMP ZCU102 RevA";
21 compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
38 bootargs = "earlycon";
39 stdout-path = "serial0:115200n8";
43 device_type = "memory";
44 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
48 compatible = "gpio-keys";
54 gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
55 linux,code = <108>; /* down */
62 compatible = "gpio-leds";
65 gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
66 linux,default-trigger = "heartbeat";
73 pinctrl-names = "default";
74 pinctrl-0 = <&pinctrl_can1_default>;
81 /* fpd_dma clk 667MHz, lpd_dma 500MHz */
116 phy-handle = <&phy0>;
117 phy-mode = "rgmii-id";
118 pinctrl-names = "default";
119 pinctrl-0 = <&pinctrl_gem3_default>;
122 ti,rx-internal-delay = <0x8>;
123 ti,tx-internal-delay = <0xa>;
124 ti,fifo-depth = <0x1>;
130 pinctrl-names = "default";
131 pinctrl-0 = <&pinctrl_gpio_default>;
140 clock-frequency = <400000>;
141 pinctrl-names = "default", "gpio";
142 pinctrl-0 = <&pinctrl_i2c0_default>;
143 pinctrl-1 = <&pinctrl_i2c0_gpio>;
144 scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
145 sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
147 tca6416_u97: gpio@20 {
149 * Enable all GTs to out from U-Boot
150 * i2c mw 20 6 0 - setup IO to output
151 * i2c mw 20 2 ef - setup output values on pins 0-7
152 * i2c mw 20 3 ff - setup output values on pins 10-17
154 compatible = "ti,tca6416";
161 * 0 - PS_GTR_LAN_SEL0
162 * 1 - PS_GTR_LAN_SEL1
163 * 2 - PS_GTR_LAN_SEL2
164 * 3 - PS_GTR_LAN_SEL3
165 * 4 - PCI_CLK_DIR_SEL
166 * 5 - IIC_MUX_RESET_B
167 * 6 - GEM3_EXP_RESET_B
168 * 7, 10 - 17 - not connected
174 output-low; /* PCIE = 0, DP = 1 */
180 output-high; /* PCIE = 0, DP = 1 */
186 output-high; /* PCIE = 0, USB0 = 1 */
192 output-high; /* PCIE = 0, SATA = 1 */
197 tca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */
198 compatible = "ti,tca6416";
209 * 4 - MIO26_PMU_INPUT_LS
212 * 7 - MAXIM_PMBUS_ALERT
213 * 10 - PL_DDR4_VTERM_EN
214 * 11 - PL_DDR4_VPP_2V5_EN
215 * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON
216 * 13 - PS_DIMM_SUSPEND_EN
217 * 14 - PS_DDR4_VTERM_EN
218 * 15 - PS_DDR4_VPP_2V5_EN
219 * 16 - 17 - not connected
223 i2cswitch@75 { /* u60 */
224 compatible = "nxp,pca9544";
225 #address-cells = <1>;
228 i2c@0 { /* i2c mw 75 0 1 */
229 #address-cells = <1>;
233 ina226@40 { /* u76 */
234 compatible = "ti,ina226";
236 shunt-resistor = <5000>;
238 ina226@41 { /* u77 */
239 compatible = "ti,ina226";
241 shunt-resistor = <5000>;
243 ina226@42 { /* u78 */
244 compatible = "ti,ina226";
246 shunt-resistor = <5000>;
248 ina226@43 { /* u87 */
249 compatible = "ti,ina226";
251 shunt-resistor = <5000>;
253 ina226@44 { /* u85 */
254 compatible = "ti,ina226";
256 shunt-resistor = <5000>;
258 ina226@45 { /* u86 */
259 compatible = "ti,ina226";
261 shunt-resistor = <5000>;
263 ina226@46 { /* u93 */
264 compatible = "ti,ina226";
266 shunt-resistor = <5000>;
268 ina226@47 { /* u88 */
269 compatible = "ti,ina226";
271 shunt-resistor = <5000>;
273 ina226@4a { /* u15 */
274 compatible = "ti,ina226";
276 shunt-resistor = <5000>;
278 ina226@4b { /* u92 */
279 compatible = "ti,ina226";
281 shunt-resistor = <5000>;
284 i2c@1 { /* i2c mw 75 0 1 */
285 #address-cells = <1>;
289 ina226@40 { /* u79 */
290 compatible = "ti,ina226";
292 shunt-resistor = <2000>;
294 ina226@41 { /* u81 */
295 compatible = "ti,ina226";
297 shunt-resistor = <5000>;
299 ina226@42 { /* u80 */
300 compatible = "ti,ina226";
302 shunt-resistor = <5000>;
304 ina226@43 { /* u84 */
305 compatible = "ti,ina226";
307 shunt-resistor = <5000>;
309 ina226@44 { /* u16 */
310 compatible = "ti,ina226";
312 shunt-resistor = <5000>;
314 ina226@45 { /* u65 */
315 compatible = "ti,ina226";
317 shunt-resistor = <5000>;
319 ina226@46 { /* u74 */
320 compatible = "ti,ina226";
322 shunt-resistor = <5000>;
324 ina226@47 { /* u75 */
325 compatible = "ti,ina226";
327 shunt-resistor = <5000>;
330 i2c@2 { /* i2c mw 75 0 1 */
331 #address-cells = <1>;
334 /* MAXIM_PMBUS - 00 */
335 max15301@a { /* u46 */
336 compatible = "max15301";
339 max15303@b { /* u4 */
340 compatible = "max15303";
343 max15303@10 { /* u13 */
344 compatible = "max15303";
347 max15301@13 { /* u47 */
348 compatible = "max15301";
351 max15303@14 { /* u7 */
352 compatible = "max15303";
355 max15303@15 { /* u6 */
356 compatible = "max15303";
359 max15303@16 { /* u10 */
360 compatible = "max15303";
363 max15303@17 { /* u9 */
364 compatible = "max15303";
367 max15301@18 { /* u63 */
368 compatible = "max15301";
371 max15303@1a { /* u49 */
372 compatible = "max15303";
375 max15303@1d { /* u18 */
376 compatible = "max15303";
379 max15303@20 { /* u8 */
380 compatible = "max15303";
381 status = "disabled"; /* unreachable */
385 /* drivers/hwmon/pmbus/Kconfig:86: be called max20751.
386 drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o
388 max20751@72 { /* u95 FIXME - not detected */
389 compatible = "max20751";
392 max20751@73 { /* u96 FIXME - not detected */
393 compatible = "max20751";
397 /* Bus 3 is not connected */
400 /* FIXME PMOD - j160 */
401 /* FIXME MSP430F - u41 - not detected */
406 clock-frequency = <400000>;
407 pinctrl-names = "default", "gpio";
408 pinctrl-0 = <&pinctrl_i2c1_default>;
409 pinctrl-1 = <&pinctrl_i2c1_gpio>;
410 scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
411 sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
413 /* FIXME PL i2c via PCA9306 - u45 */
414 /* FIXME MSP430 - u41 - not detected */
415 i2cswitch@74 { /* u34 */
416 compatible = "nxp,pca9548";
417 #address-cells = <1>;
420 i2c@0 { /* i2c mw 74 0 1 */
421 #address-cells = <1>;
425 * IIC_EEPROM 1kB memory which uses 256B blocks
426 * where every block has different address.
427 * 0 - 256B address 0x54
428 * 256B - 512B address 0x55
429 * 512B - 768B address 0x56
430 * 768B - 1024B address 0x57
432 eeprom: eeprom@54 { /* u23 */
433 compatible = "at,24c08";
437 i2c@1 { /* i2c mw 74 0 2 */
438 #address-cells = <1>;
441 si5341: clock-generator1@36 { /* SI5341 - u69 */
442 compatible = "si5341";
447 i2c@2 { /* i2c mw 74 0 4 */
448 #address-cells = <1>;
451 si570_1: clock-generator2@5d { /* USER SI570 - u42 */
453 compatible = "silabs,si570";
455 temperature-stability = <50>;
456 factory-fout = <300000000>;
457 clock-frequency = <300000000>;
460 i2c@3 { /* i2c mw 74 0 8 */
461 #address-cells = <1>;
464 si570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */
466 compatible = "silabs,si570";
468 temperature-stability = <50>; /* copy from zc702 */
469 factory-fout = <156250000>;
470 clock-frequency = <148500000>;
473 i2c@4 { /* i2c mw 74 0 10 */
474 #address-cells = <1>;
477 si5328: clock-generator4@69 {/* SI5328 - u20 */
478 compatible = "silabs,si5328";
481 * Chip has interrupt present connected to PL
482 * interrupt-parent = <&>;
487 /* 5 - 7 unconnected */
491 compatible = "nxp,pca9548"; /* u135 */
492 #address-cells = <1>;
497 #address-cells = <1>;
503 #address-cells = <1>;
509 #address-cells = <1>;
514 i2c@3 { /* i2c mw 75 0 8 */
515 #address-cells = <1>;
519 dev@19 { /* u-boot detection */
523 dev@30 { /* u-boot detection */
527 dev@35 { /* u-boot detection */
531 dev@36 { /* u-boot detection */
535 dev@51 { /* u-boot detection - maybe SPD */
541 #address-cells = <1>;
547 #address-cells = <1>;
553 #address-cells = <1>;
559 #address-cells = <1>;
569 pinctrl_i2c0_default: i2c0-default {
571 groups = "i2c0_3_grp";
576 groups = "i2c0_3_grp";
578 slew-rate = <SLEW_RATE_SLOW>;
579 io-standard = <IO_STANDARD_LVCMOS18>;
583 pinctrl_i2c0_gpio: i2c0-gpio {
585 groups = "gpio0_14_grp", "gpio0_15_grp";
590 groups = "gpio0_14_grp", "gpio0_15_grp";
591 slew-rate = <SLEW_RATE_SLOW>;
592 io-standard = <IO_STANDARD_LVCMOS18>;
596 pinctrl_i2c1_default: i2c1-default {
598 groups = "i2c1_4_grp";
603 groups = "i2c1_4_grp";
605 slew-rate = <SLEW_RATE_SLOW>;
606 io-standard = <IO_STANDARD_LVCMOS18>;
610 pinctrl_i2c1_gpio: i2c1-gpio {
612 groups = "gpio0_16_grp", "gpio0_17_grp";
617 groups = "gpio0_16_grp", "gpio0_17_grp";
618 slew-rate = <SLEW_RATE_SLOW>;
619 io-standard = <IO_STANDARD_LVCMOS18>;
623 pinctrl_uart0_default: uart0-default {
625 groups = "uart0_4_grp";
630 groups = "uart0_4_grp";
631 slew-rate = <SLEW_RATE_SLOW>;
632 io-standard = <IO_STANDARD_LVCMOS18>;
646 pinctrl_uart1_default: uart1-default {
648 groups = "uart1_5_grp";
653 groups = "uart1_5_grp";
654 slew-rate = <SLEW_RATE_SLOW>;
655 io-standard = <IO_STANDARD_LVCMOS18>;
669 pinctrl_usb0_default: usb0-default {
671 groups = "usb0_0_grp";
676 groups = "usb0_0_grp";
677 slew-rate = <SLEW_RATE_SLOW>;
678 io-standard = <IO_STANDARD_LVCMOS18>;
682 pins = "MIO52", "MIO53", "MIO55";
687 pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
688 "MIO60", "MIO61", "MIO62", "MIO63";
693 pinctrl_gem3_default: gem3-default {
695 function = "ethernet3";
696 groups = "ethernet3_0_grp";
700 groups = "ethernet3_0_grp";
701 slew-rate = <SLEW_RATE_SLOW>;
702 io-standard = <IO_STANDARD_LVCMOS18>;
706 pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
713 pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
721 groups = "mdio3_0_grp";
725 groups = "mdio3_0_grp";
726 slew-rate = <SLEW_RATE_SLOW>;
727 io-standard = <IO_STANDARD_LVCMOS18>;
732 pinctrl_can1_default: can1-default {
735 groups = "can1_6_grp";
739 groups = "can1_6_grp";
740 slew-rate = <SLEW_RATE_SLOW>;
741 io-standard = <IO_STANDARD_LVCMOS18>;
755 pinctrl_sdhci1_default: sdhci1-default {
757 groups = "sdio1_0_grp";
762 groups = "sdio1_0_grp";
763 slew-rate = <SLEW_RATE_SLOW>;
764 io-standard = <IO_STANDARD_LVCMOS18>;
769 groups = "sdio1_0_cd_grp";
770 function = "sdio1_cd";
774 groups = "sdio1_0_cd_grp";
777 slew-rate = <SLEW_RATE_SLOW>;
778 io-standard = <IO_STANDARD_LVCMOS18>;
782 groups = "sdio1_0_wp_grp";
783 function = "sdio1_wp";
787 groups = "sdio1_0_wp_grp";
790 slew-rate = <SLEW_RATE_SLOW>;
791 io-standard = <IO_STANDARD_LVCMOS18>;
795 pinctrl_gpio_default: gpio-default {
798 groups = "gpio0_22_grp", "gpio0_23_grp";
802 groups = "gpio0_22_grp", "gpio0_23_grp";
803 slew-rate = <SLEW_RATE_SLOW>;
804 io-standard = <IO_STANDARD_LVCMOS18>;
809 groups = "gpio0_13_grp", "gpio0_38_grp";
813 groups = "gpio0_13_grp", "gpio0_38_grp";
814 slew-rate = <SLEW_RATE_SLOW>;
815 io-standard = <IO_STANDARD_LVCMOS18>;
819 pins = "MIO22", "MIO23";
824 pins = "MIO13", "MIO38";
838 compatible = "m25p80"; /* 32MB */
839 #address-cells = <1>;
842 spi-tx-bus-width = <1>;
843 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
844 spi-max-frequency = <108000000>; /* Based on DC1 spec */
845 partition@qspi-fsbl-uboot { /* for testing purpose */
846 label = "qspi-fsbl-uboot";
847 reg = <0x0 0x100000>;
849 partition@qspi-linux { /* for testing purpose */
850 label = "qspi-linux";
851 reg = <0x100000 0x500000>;
853 partition@qspi-device-tree { /* for testing purpose */
854 label = "qspi-device-tree";
855 reg = <0x600000 0x20000>;
857 partition@qspi-rootfs { /* for testing purpose */
858 label = "qspi-rootfs";
859 reg = <0x620000 0x5E0000>;
870 /* SATA OOB timing settings */
871 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
872 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
873 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
874 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
875 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
876 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
877 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
878 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
879 phy-names = "sata-phy";
880 phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;
883 /* SD1 with level shifter */
886 pinctrl-names = "default";
887 pinctrl-0 = <&pinctrl_sdhci1_default>;
888 no-1-8-v; /* for 1.0 silicon */
898 pinctrl-names = "default";
899 pinctrl-0 = <&pinctrl_uart0_default>;
904 pinctrl-names = "default";
905 pinctrl-0 = <&pinctrl_uart1_default>;
908 /* ULPI SMSC USB3320 */
911 pinctrl-names = "default";
912 pinctrl-0 = <&pinctrl_usb0_default>;
918 snps,usb3_lpm_capable;
919 phy-names = "usb3-phy";
920 phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
921 maximum-speed = "super-speed";
966 &xlnx_dp_snd_codec0 {