Merge git://git.denx.de/u-boot-imx
[platform/kernel/u-boot.git] / arch / arm / dts / zynqmp-zcu102-revA.dts
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * dts file for Xilinx ZynqMP ZCU102 RevA
4  *
5  * (C) Copyright 2015 - 2018, Xilinx, Inc.
6  *
7  * Michal Simek <michal.simek@xilinx.com>
8  */
9
10 /dts-v1/;
11
12 #include "zynqmp.dtsi"
13 #include "zynqmp-clk-ccf.dtsi"
14 #include <dt-bindings/input/input.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/phy/phy.h>
17
18 / {
19         model = "ZynqMP ZCU102 RevA";
20         compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
21
22         aliases {
23                 ethernet0 = &gem3;
24                 gpio0 = &gpio;
25                 i2c0 = &i2c0;
26                 i2c1 = &i2c1;
27                 mmc0 = &sdhci1;
28                 rtc0 = &rtc;
29                 serial0 = &uart0;
30                 serial1 = &uart1;
31                 serial2 = &dcc;
32                 spi0 = &qspi;
33                 usb0 = &usb0;
34         };
35
36         chosen {
37                 bootargs = "earlycon";
38                 stdout-path = "serial0:115200n8";
39         };
40
41         memory@0 {
42                 device_type = "memory";
43                 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
44         };
45
46         gpio-keys {
47                 compatible = "gpio-keys";
48                 #address-cells = <1>;
49                 #size-cells = <0>;
50                 autorepeat;
51                 sw19 {
52                         label = "sw19";
53                         gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
54                         linux,code = <KEY_DOWN>;
55                         gpio-key,wakeup;
56                         autorepeat;
57                 };
58         };
59
60         leds {
61                 compatible = "gpio-leds";
62                 heartbeat_led {
63                         label = "heartbeat";
64                         gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
65                         linux,default-trigger = "heartbeat";
66                 };
67         };
68 };
69
70 &can1 {
71         status = "okay";
72 };
73
74 &dcc {
75         status = "okay";
76 };
77
78 &fpd_dma_chan1 {
79         status = "okay";
80 };
81
82 &fpd_dma_chan2 {
83         status = "okay";
84 };
85
86 &fpd_dma_chan3 {
87         status = "okay";
88 };
89
90 &fpd_dma_chan4 {
91         status = "okay";
92 };
93
94 &fpd_dma_chan5 {
95         status = "okay";
96 };
97
98 &fpd_dma_chan6 {
99         status = "okay";
100 };
101
102 &fpd_dma_chan7 {
103         status = "okay";
104 };
105
106 &fpd_dma_chan8 {
107         status = "okay";
108 };
109
110 &gem3 {
111         status = "okay";
112         phy-handle = <&phy0>;
113         phy-mode = "rgmii-id";
114         phy0: phy@21 {
115                 reg = <21>;
116                 ti,rx-internal-delay = <0x8>;
117                 ti,tx-internal-delay = <0xa>;
118                 ti,fifo-depth = <0x1>;
119         };
120 };
121
122 &gpio {
123         status = "okay";
124 };
125
126 &gpu {
127         status = "okay";
128 };
129
130 &i2c0 {
131         status = "okay";
132         clock-frequency = <400000>;
133
134         tca6416_u97: gpio@20 {
135                 compatible = "ti,tca6416";
136                 reg = <0x20>;
137                 gpio-controller;
138                 #gpio-cells = <2>;
139                 /*
140                  * IRQ not connected
141                  * Lines:
142                  * 0 - PS_GTR_LAN_SEL0
143                  * 1 - PS_GTR_LAN_SEL1
144                  * 2 - PS_GTR_LAN_SEL2
145                  * 3 - PS_GTR_LAN_SEL3
146                  * 4 - PCI_CLK_DIR_SEL
147                  * 5 - IIC_MUX_RESET_B
148                  * 6 - GEM3_EXP_RESET_B
149                  * 7, 10 - 17 - not connected
150                  */
151
152                 gtr_sel0 {
153                         gpio-hog;
154                         gpios = <0 0>;
155                         output-low; /* PCIE = 0, DP = 1 */
156                         line-name = "sel0";
157                 };
158                 gtr_sel1 {
159                         gpio-hog;
160                         gpios = <1 0>;
161                         output-high; /* PCIE = 0, DP = 1 */
162                         line-name = "sel1";
163                 };
164                 gtr_sel2 {
165                         gpio-hog;
166                         gpios = <2 0>;
167                         output-high; /* PCIE = 0, USB0 = 1 */
168                         line-name = "sel2";
169                 };
170                 gtr_sel3 {
171                         gpio-hog;
172                         gpios = <3 0>;
173                         output-high; /* PCIE = 0, SATA = 1 */
174                         line-name = "sel3";
175                 };
176         };
177
178         tca6416_u61: gpio@21 {
179                 compatible = "ti,tca6416";
180                 reg = <0x21>;
181                 gpio-controller;
182                 #gpio-cells = <2>;
183                 /*
184                  * IRQ not connected
185                  * Lines:
186                  * 0 - VCCPSPLL_EN
187                  * 1 - MGTRAVCC_EN
188                  * 2 - MGTRAVTT_EN
189                  * 3 - VCCPSDDRPLL_EN
190                  * 4 - MIO26_PMU_INPUT_LS
191                  * 5 - PL_PMBUS_ALERT
192                  * 6 - PS_PMBUS_ALERT
193                  * 7 - MAXIM_PMBUS_ALERT
194                  * 10 - PL_DDR4_VTERM_EN
195                  * 11 - PL_DDR4_VPP_2V5_EN
196                  * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON
197                  * 13 - PS_DIMM_SUSPEND_EN
198                  * 14 - PS_DDR4_VTERM_EN
199                  * 15 - PS_DDR4_VPP_2V5_EN
200                  * 16 - 17 - not connected
201                  */
202         };
203
204         i2c-mux@75 { /* u60 */
205                 compatible = "nxp,pca9544";
206                 #address-cells = <1>;
207                 #size-cells = <0>;
208                 reg = <0x75>;
209                 i2c@0 {
210                         #address-cells = <1>;
211                         #size-cells = <0>;
212                         reg = <0>;
213                         /* PS_PMBUS */
214                         ina226@40 { /* u76 */
215                                 compatible = "ti,ina226";
216                                 reg = <0x40>;
217                                 shunt-resistor = <5000>;
218                         };
219                         ina226@41 { /* u77 */
220                                 compatible = "ti,ina226";
221                                 reg = <0x41>;
222                                 shunt-resistor = <5000>;
223                         };
224                         ina226@42 { /* u78 */
225                                 compatible = "ti,ina226";
226                                 reg = <0x42>;
227                                 shunt-resistor = <5000>;
228                         };
229                         ina226@43 { /* u87 */
230                                 compatible = "ti,ina226";
231                                 reg = <0x43>;
232                                 shunt-resistor = <5000>;
233                         };
234                         ina226@44 { /* u85 */
235                                 compatible = "ti,ina226";
236                                 reg = <0x44>;
237                                 shunt-resistor = <5000>;
238                         };
239                         ina226@45 { /* u86 */
240                                 compatible = "ti,ina226";
241                                 reg = <0x45>;
242                                 shunt-resistor = <5000>;
243                         };
244                         ina226@46 { /* u93 */
245                                 compatible = "ti,ina226";
246                                 reg = <0x46>;
247                                 shunt-resistor = <5000>;
248                         };
249                         ina226@47 { /* u88 */
250                                 compatible = "ti,ina226";
251                                 reg = <0x47>;
252                                 shunt-resistor = <5000>;
253                         };
254                         ina226@4a { /* u15 */
255                                 compatible = "ti,ina226";
256                                 reg = <0x4a>;
257                                 shunt-resistor = <5000>;
258                         };
259                         ina226@4b { /* u92 */
260                                 compatible = "ti,ina226";
261                                 reg = <0x4b>;
262                                 shunt-resistor = <5000>;
263                         };
264                 };
265                 i2c@1 {
266                         #address-cells = <1>;
267                         #size-cells = <0>;
268                         reg = <1>;
269                         /* PL_PMBUS */
270                         ina226@40 { /* u79 */
271                                 compatible = "ti,ina226";
272                                 reg = <0x40>;
273                                 shunt-resistor = <2000>;
274                         };
275                         ina226@41 { /* u81 */
276                                 compatible = "ti,ina226";
277                                 reg = <0x41>;
278                                 shunt-resistor = <5000>;
279                         };
280                         ina226@42 { /* u80 */
281                                 compatible = "ti,ina226";
282                                 reg = <0x42>;
283                                 shunt-resistor = <5000>;
284                         };
285                         ina226@43 { /* u84 */
286                                 compatible = "ti,ina226";
287                                 reg = <0x43>;
288                                 shunt-resistor = <5000>;
289                         };
290                         ina226@44 { /* u16 */
291                                 compatible = "ti,ina226";
292                                 reg = <0x44>;
293                                 shunt-resistor = <5000>;
294                         };
295                         ina226@45 { /* u65 */
296                                 compatible = "ti,ina226";
297                                 reg = <0x45>;
298                                 shunt-resistor = <5000>;
299                         };
300                         ina226@46 { /* u74 */
301                                 compatible = "ti,ina226";
302                                 reg = <0x46>;
303                                 shunt-resistor = <5000>;
304                         };
305                         ina226@47 { /* u75 */
306                                 compatible = "ti,ina226";
307                                 reg = <0x47>;
308                                 shunt-resistor = <5000>;
309                         };
310                 };
311                 i2c@2 {
312                         #address-cells = <1>;
313                         #size-cells = <0>;
314                         reg = <2>;
315                         /* MAXIM_PMBUS - 00 */
316                         max15301@a { /* u46 */
317                                 compatible = "maxim,max15301";
318                                 reg = <0xa>;
319                         };
320                         max15303@b { /* u4 */
321                                 compatible = "maxim,max15303";
322                                 reg = <0xb>;
323                         };
324                         max15303@10 { /* u13 */
325                                 compatible = "maxim,max15303";
326                                 reg = <0x10>;
327                         };
328                         max15301@13 { /* u47 */
329                                 compatible = "maxim,max15301";
330                                 reg = <0x13>;
331                         };
332                         max15303@14 { /* u7 */
333                                 compatible = "maxim,max15303";
334                                 reg = <0x14>;
335                         };
336                         max15303@15 { /* u6 */
337                                 compatible = "maxim,max15303";
338                                 reg = <0x15>;
339                         };
340                         max15303@16 { /* u10 */
341                                 compatible = "maxim,max15303";
342                                 reg = <0x16>;
343                         };
344                         max15303@17 { /* u9 */
345                                 compatible = "maxim,max15303";
346                                 reg = <0x17>;
347                         };
348                         max15301@18 { /* u63 */
349                                 compatible = "maxim,max15301";
350                                 reg = <0x18>;
351                         };
352                         max15303@1a { /* u49 */
353                                 compatible = "maxim,max15303";
354                                 reg = <0x1a>;
355                         };
356                         max15303@1d { /* u18 */
357                                 compatible = "maxim,max15303";
358                                 reg = <0x1d>;
359                         };
360                         max15303@20 { /* u8 */
361                                 compatible = "maxim,max15303";
362                                 status = "disabled"; /* unreachable */
363                                 reg = <0x20>;
364                         };
365
366                         max20751@72 { /* u95 */
367                                 compatible = "maxim,max20751";
368                                 reg = <0x72>;
369                         };
370                         max20751@73 { /* u96 */
371                                 compatible = "maxim,max20751";
372                                 reg = <0x73>;
373                         };
374                 };
375                 /* Bus 3 is not connected */
376         };
377 };
378
379 &i2c1 {
380         status = "okay";
381         clock-frequency = <400000>;
382
383         /* PL i2c via PCA9306 - u45 */
384         i2c-mux@74 { /* u34 */
385                 compatible = "nxp,pca9548";
386                 #address-cells = <1>;
387                 #size-cells = <0>;
388                 reg = <0x74>;
389                 i2c@0 {
390                         #address-cells = <1>;
391                         #size-cells = <0>;
392                         reg = <0>;
393                         /*
394                          * IIC_EEPROM 1kB memory which uses 256B blocks
395                          * where every block has different address.
396                          *    0 - 256B address 0x54
397                          * 256B - 512B address 0x55
398                          * 512B - 768B address 0x56
399                          * 768B - 1024B address 0x57
400                          */
401                         eeprom: eeprom@54 { /* u23 */
402                                 compatible = "atmel,24c08";
403                                 reg = <0x54>;
404                         };
405                 };
406                 i2c@1 {
407                         #address-cells = <1>;
408                         #size-cells = <0>;
409                         reg = <1>;
410                         si5341: clock-generator@36 { /* SI5341 - u69 */
411                                 compatible = "silabs,si5341";
412                                 reg = <0x36>;
413                         };
414
415                 };
416                 i2c@2 {
417                         #address-cells = <1>;
418                         #size-cells = <0>;
419                         reg = <2>;
420                         si570_1: clock-generator@5d { /* USER SI570 - u42 */
421                                 #clock-cells = <0>;
422                                 compatible = "silabs,si570";
423                                 reg = <0x5d>;
424                                 temperature-stability = <50>;
425                                 factory-fout = <300000000>;
426                                 clock-frequency = <300000000>;
427                         };
428                 };
429                 i2c@3 {
430                         #address-cells = <1>;
431                         #size-cells = <0>;
432                         reg = <3>;
433                         si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */
434                                 #clock-cells = <0>;
435                                 compatible = "silabs,si570";
436                                 reg = <0x5d>;
437                                 temperature-stability = <50>; /* copy from zc702 */
438                                 factory-fout = <156250000>;
439                                 clock-frequency = <148500000>;
440                         };
441                 };
442                 i2c@4 {
443                         #address-cells = <1>;
444                         #size-cells = <0>;
445                         reg = <4>;
446                         si5328: clock-generator@69 {/* SI5328 - u20 */
447                                 compatible = "silabs,si5328";
448                                 reg = <0x69>;
449                                 /*
450                                  * Chip has interrupt present connected to PL
451                                  * interrupt-parent = <&>;
452                                  * interrupts = <>;
453                                  */
454                         };
455                 };
456                 /* 5 - 7 unconnected */
457         };
458
459         i2c-mux@75 {
460                 compatible = "nxp,pca9548"; /* u135 */
461                 #address-cells = <1>;
462                 #size-cells = <0>;
463                 reg = <0x75>;
464
465                 i2c@0 {
466                         #address-cells = <1>;
467                         #size-cells = <0>;
468                         reg = <0>;
469                         /* HPC0_IIC */
470                 };
471                 i2c@1 {
472                         #address-cells = <1>;
473                         #size-cells = <0>;
474                         reg = <1>;
475                         /* HPC1_IIC */
476                 };
477                 i2c@2 {
478                         #address-cells = <1>;
479                         #size-cells = <0>;
480                         reg = <2>;
481                         /* SYSMON */
482                 };
483                 i2c@3 {
484                         #address-cells = <1>;
485                         #size-cells = <0>;
486                         reg = <3>;
487                         /* DDR4 SODIMM */
488                         dev@19 {
489                                 reg = <0x19>;
490                         };
491                         dev@30 {
492                                 reg = <0x30>;
493                         };
494                         dev@35 {
495                                 reg = <0x35>;
496                         };
497                         dev@36 {
498                                 reg = <0x36>;
499                         };
500                         dev@51 {
501                                 reg = <0x51>;
502                         };
503                 };
504                 i2c@4 {
505                         #address-cells = <1>;
506                         #size-cells = <0>;
507                         reg = <4>;
508                         /* SEP 3 */
509                 };
510                 i2c@5 {
511                         #address-cells = <1>;
512                         #size-cells = <0>;
513                         reg = <5>;
514                         /* SEP 2 */
515                 };
516                 i2c@6 {
517                         #address-cells = <1>;
518                         #size-cells = <0>;
519                         reg = <6>;
520                         /* SEP 1 */
521                 };
522                 i2c@7 {
523                         #address-cells = <1>;
524                         #size-cells = <0>;
525                         reg = <7>;
526                         /* SEP 0 */
527                 };
528         };
529 };
530
531 &pcie {
532         status = "okay";
533 };
534
535 &qspi {
536         status = "okay";
537         is-dual = <1>;
538         flash@0 {
539                 compatible = "m25p80"; /* 32MB */
540                 #address-cells = <1>;
541                 #size-cells = <1>;
542                 reg = <0x0>;
543                 spi-tx-bus-width = <1>;
544                 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
545                 spi-max-frequency = <108000000>; /* Based on DC1 spec */
546                 partition@qspi-fsbl-uboot { /* for testing purpose */
547                         label = "qspi-fsbl-uboot";
548                         reg = <0x0 0x100000>;
549                 };
550                 partition@qspi-linux { /* for testing purpose */
551                         label = "qspi-linux";
552                         reg = <0x100000 0x500000>;
553                 };
554                 partition@qspi-device-tree { /* for testing purpose */
555                         label = "qspi-device-tree";
556                         reg = <0x600000 0x20000>;
557                 };
558                 partition@qspi-rootfs { /* for testing purpose */
559                         label = "qspi-rootfs";
560                         reg = <0x620000 0x5E0000>;
561                 };
562         };
563 };
564
565 &rtc {
566         status = "okay";
567 };
568
569 &sata {
570         status = "okay";
571         /* SATA OOB timing settings */
572         ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
573         ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
574         ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
575         ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
576         ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
577         ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
578         ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
579         ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
580         phy-names = "sata-phy";
581         phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;
582 };
583
584 /* SD1 with level shifter */
585 &sdhci1 {
586         status = "okay";
587         no-1-8-v;       /* for 1.0 silicon */
588         xlnx,mio_bank = <1>;
589 };
590
591 &serdes {
592         status = "okay";
593 };
594
595 &uart0 {
596         status = "okay";
597 };
598
599 &uart1 {
600         status = "okay";
601 };
602
603 /* ULPI SMSC USB3320 */
604 &usb0 {
605         status = "okay";
606 };
607
608 &dwc3_0 {
609         status = "okay";
610         dr_mode = "host";
611         snps,usb3_lpm_capable;
612         phy-names = "usb3-phy";
613         phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
614         maximum-speed = "super-speed";
615 };
616
617 &watchdog0 {
618         status = "okay";
619 };
620
621 &xilinx_ams {
622         status = "okay";
623 };
624
625 &ams_ps {
626         status = "okay";
627 };
628
629 &ams_pl {
630         status = "okay";
631 };
632
633 &xilinx_drm {
634         status = "okay";
635         clocks = <&si570_1>;
636 };
637
638 &xlnx_dp {
639         status = "okay";
640 };
641
642 &xlnx_dp_sub {
643         status = "okay";
644         xlnx,vid-clk-pl;
645 };
646
647 &xlnx_dp_snd_pcm0 {
648         status = "okay";
649 };
650
651 &xlnx_dp_snd_pcm1 {
652         status = "okay";
653 };
654
655 &xlnx_dp_snd_card {
656         status = "okay";
657 };
658
659 &xlnx_dp_snd_codec0 {
660         status = "okay";
661 };
662
663 &xlnx_dpdma {
664         status = "okay";
665 };