1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP ZCU102 RevA
5 * (C) Copyright 2015 - 2018, Xilinx, Inc.
7 * Michal Simek <michal.simek@xilinx.com>
12 #include "zynqmp.dtsi"
13 #include "zynqmp-clk-ccf.dtsi"
14 #include <dt-bindings/input/input.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/phy/phy.h>
19 model = "ZynqMP ZCU102 RevA";
20 compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
37 bootargs = "earlycon";
38 stdout-path = "serial0:115200n8";
39 xlnx,eeprom = &eeprom;
43 device_type = "memory";
44 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
48 compatible = "gpio-keys";
52 gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
53 linux,code = <KEY_DOWN>;
60 compatible = "gpio-leds";
63 gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
64 linux,default-trigger = "heartbeat";
69 compatible = "iio-hwmon";
70 io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;
73 compatible = "iio-hwmon";
74 io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;
77 compatible = "iio-hwmon";
78 io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;
81 compatible = "iio-hwmon";
82 io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;
85 compatible = "iio-hwmon";
86 io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;
89 compatible = "iio-hwmon";
90 io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;
93 compatible = "iio-hwmon";
94 io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;
97 compatible = "iio-hwmon";
98 io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;
101 compatible = "iio-hwmon";
102 io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;
105 compatible = "iio-hwmon";
106 io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;
109 compatible = "iio-hwmon";
110 io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;
113 compatible = "iio-hwmon";
114 io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;
117 compatible = "iio-hwmon";
118 io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;
121 compatible = "iio-hwmon";
122 io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;
125 compatible = "iio-hwmon";
126 io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;
129 compatible = "iio-hwmon";
130 io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;
133 compatible = "iio-hwmon";
134 io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;
137 compatible = "iio-hwmon";
138 io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;
184 phy-handle = <&phy0>;
185 phy-mode = "rgmii-id";
186 phy0: ethernet-phy@21 {
188 ti,rx-internal-delay = <0x8>;
189 ti,tx-internal-delay = <0xa>;
190 ti,fifo-depth = <0x1>;
191 ti,dp83867-rxctrl-strap-quirk;
192 /* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */
206 clock-frequency = <400000>;
208 tca6416_u97: gpio@20 {
209 compatible = "ti,tca6416";
211 gpio-controller; /* IRQ not connected */
213 gpio-line-names = "PS_GTR_LAN_SEL0", "PS_GTR_LAN_SEL1", "PS_GTR_LAN_SEL2", "PS_GTR_LAN_SEL3",
214 "PCI_CLK_DIR_SEL", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B",
215 "", "", "", "", "", "", "", "", "";
219 output-low; /* PCIE = 0, DP = 1 */
225 output-high; /* PCIE = 0, DP = 1 */
231 output-high; /* PCIE = 0, USB0 = 1 */
237 output-high; /* PCIE = 0, SATA = 1 */
242 tca6416_u61: gpio@21 {
243 compatible = "ti,tca6416";
245 gpio-controller; /* IRQ not connected */
247 gpio-line-names = "VCCPSPLL_EN", "MGTRAVCC_EN", "MGTRAVTT_EN", "VCCPSDDRPLL_EN", "MIO26_PMU_INPUT_LS",
248 "PL_PMBUS_ALERT", "PS_PMBUS_ALERT", "MAXIM_PMBUS_ALERT", "PL_DDR4_VTERM_EN",
249 "PL_DDR4_VPP_2V5_EN", "PS_DIMM_VDDQ_TO_PSVCCO_ON", "PS_DIMM_SUSPEND_EN",
250 "PS_DDR4_VTERM_EN", "PS_DDR4_VPP_2V5_EN", "", "";
253 i2c-mux@75 { /* u60 */
254 compatible = "nxp,pca9544";
255 #address-cells = <1>;
259 #address-cells = <1>;
263 u76: ina226@40 { /* u76 */
264 compatible = "ti,ina226";
265 #io-channel-cells = <1>;
266 label = "ina226-u76";
268 shunt-resistor = <5000>;
270 u77: ina226@41 { /* u77 */
271 compatible = "ti,ina226";
272 #io-channel-cells = <1>;
273 label = "ina226-u77";
275 shunt-resistor = <5000>;
277 u78: ina226@42 { /* u78 */
278 compatible = "ti,ina226";
279 #io-channel-cells = <1>;
280 label = "ina226-u78";
282 shunt-resistor = <5000>;
284 u87: ina226@43 { /* u87 */
285 compatible = "ti,ina226";
286 #io-channel-cells = <1>;
287 label = "ina226-u87";
289 shunt-resistor = <5000>;
291 u85: ina226@44 { /* u85 */
292 compatible = "ti,ina226";
293 #io-channel-cells = <1>;
294 label = "ina226-u85";
296 shunt-resistor = <5000>;
298 u86: ina226@45 { /* u86 */
299 compatible = "ti,ina226";
300 #io-channel-cells = <1>;
301 label = "ina226-u86";
303 shunt-resistor = <5000>;
305 u93: ina226@46 { /* u93 */
306 compatible = "ti,ina226";
307 #io-channel-cells = <1>;
308 label = "ina226-u93";
310 shunt-resistor = <5000>;
312 u88: ina226@47 { /* u88 */
313 compatible = "ti,ina226";
314 #io-channel-cells = <1>;
315 label = "ina226-u88";
317 shunt-resistor = <5000>;
319 u15: ina226@4a { /* u15 */
320 compatible = "ti,ina226";
321 #io-channel-cells = <1>;
322 label = "ina226-u15";
324 shunt-resistor = <5000>;
326 u92: ina226@4b { /* u92 */
327 compatible = "ti,ina226";
328 #io-channel-cells = <1>;
329 label = "ina226-u92";
331 shunt-resistor = <5000>;
335 #address-cells = <1>;
339 u79: ina226@40 { /* u79 */
340 compatible = "ti,ina226";
341 #io-channel-cells = <1>;
342 label = "ina226-u79";
344 shunt-resistor = <2000>;
346 u81: ina226@41 { /* u81 */
347 compatible = "ti,ina226";
348 #io-channel-cells = <1>;
349 label = "ina226-u81";
351 shunt-resistor = <5000>;
353 u80: ina226@42 { /* u80 */
354 compatible = "ti,ina226";
355 #io-channel-cells = <1>;
356 label = "ina226-u80";
358 shunt-resistor = <5000>;
360 u84: ina226@43 { /* u84 */
361 compatible = "ti,ina226";
362 #io-channel-cells = <1>;
363 label = "ina226-u84";
365 shunt-resistor = <5000>;
367 u16: ina226@44 { /* u16 */
368 compatible = "ti,ina226";
369 #io-channel-cells = <1>;
370 label = "ina226-u16";
372 shunt-resistor = <5000>;
374 u65: ina226@45 { /* u65 */
375 compatible = "ti,ina226";
376 #io-channel-cells = <1>;
377 label = "ina226-u65";
379 shunt-resistor = <5000>;
381 u74: ina226@46 { /* u74 */
382 compatible = "ti,ina226";
383 #io-channel-cells = <1>;
384 label = "ina226-u74";
386 shunt-resistor = <5000>;
388 u75: ina226@47 { /* u75 */
389 compatible = "ti,ina226";
390 #io-channel-cells = <1>;
391 label = "ina226-u75";
393 shunt-resistor = <5000>;
397 #address-cells = <1>;
400 /* MAXIM_PMBUS - 00 */
401 max15301@a { /* u46 */
402 compatible = "maxim,max15301";
405 max15303@b { /* u4 */
406 compatible = "maxim,max15303";
409 max15303@10 { /* u13 */
410 compatible = "maxim,max15303";
413 max15301@13 { /* u47 */
414 compatible = "maxim,max15301";
417 max15303@14 { /* u7 */
418 compatible = "maxim,max15303";
421 max15303@15 { /* u6 */
422 compatible = "maxim,max15303";
425 max15303@16 { /* u10 */
426 compatible = "maxim,max15303";
429 max15303@17 { /* u9 */
430 compatible = "maxim,max15303";
433 max15301@18 { /* u63 */
434 compatible = "maxim,max15301";
437 max15303@1a { /* u49 */
438 compatible = "maxim,max15303";
441 max15303@1d { /* u18 */
442 compatible = "maxim,max15303";
445 max15303@20 { /* u8 */
446 compatible = "maxim,max15303";
447 status = "disabled"; /* unreachable */
450 max20751@72 { /* u95 */
451 compatible = "maxim,max20751";
454 max20751@73 { /* u96 */
455 compatible = "maxim,max20751";
459 /* Bus 3 is not connected */
465 clock-frequency = <400000>;
467 /* PL i2c via PCA9306 - u45 */
468 i2c-mux@74 { /* u34 */
469 compatible = "nxp,pca9548";
470 #address-cells = <1>;
474 #address-cells = <1>;
478 * IIC_EEPROM 1kB memory which uses 256B blocks
479 * where every block has different address.
480 * 0 - 256B address 0x54
481 * 256B - 512B address 0x55
482 * 512B - 768B address 0x56
483 * 768B - 1024B address 0x57
485 eeprom: eeprom@54 { /* u23 */
486 compatible = "atmel,24c08";
491 #address-cells = <1>;
494 si5341: clock-generator@36 { /* SI5341 - u69 */
495 compatible = "silabs,si5341";
501 #address-cells = <1>;
504 si570_1: clock-generator@5d { /* USER SI570 - u42 */
506 compatible = "silabs,si570";
508 temperature-stability = <50>;
509 factory-fout = <300000000>;
510 clock-frequency = <300000000>;
511 clock-output-names = "si570_user";
515 #address-cells = <1>;
518 si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */
520 compatible = "silabs,si570";
522 temperature-stability = <50>; /* copy from zc702 */
523 factory-fout = <156250000>;
524 clock-frequency = <148500000>;
525 clock-output-names = "si570_mgt";
529 #address-cells = <1>;
532 si5328: clock-generator@69 {/* SI5328 - u20 */
533 compatible = "silabs,si5328";
536 * Chip has interrupt present connected to PL
537 * interrupt-parent = <&>;
542 /* 5 - 7 unconnected */
546 compatible = "nxp,pca9548"; /* u135 */
547 #address-cells = <1>;
552 #address-cells = <1>;
558 #address-cells = <1>;
564 #address-cells = <1>;
570 #address-cells = <1>;
576 #address-cells = <1>;
582 #address-cells = <1>;
588 #address-cells = <1>;
594 #address-cells = <1>;
610 compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
611 #address-cells = <1>;
614 spi-tx-bus-width = <1>;
615 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
616 spi-max-frequency = <108000000>; /* Based on DC1 spec */
617 partition@qspi-fsbl-uboot { /* for testing purpose */
618 label = "qspi-fsbl-uboot";
619 reg = <0x0 0x100000>;
621 partition@qspi-linux { /* for testing purpose */
622 label = "qspi-linux";
623 reg = <0x100000 0x500000>;
625 partition@qspi-device-tree { /* for testing purpose */
626 label = "qspi-device-tree";
627 reg = <0x600000 0x20000>;
629 partition@qspi-rootfs { /* for testing purpose */
630 label = "qspi-rootfs";
631 reg = <0x620000 0x5E0000>;
642 /* SATA OOB timing settings */
643 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
644 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
645 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
646 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
647 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
648 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
649 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
650 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
651 phy-names = "sata-phy";
652 phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;
655 /* SD1 with level shifter */
658 no-1-8-v; /* for 1.0 silicon */
674 /* ULPI SMSC USB3320 */
682 snps,usb3_lpm_capable;
683 phy-names = "usb3-phy";
684 phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
685 maximum-speed = "super-speed";
730 &xlnx_dp_snd_codec0 {