arch/arm/dts/zynqmp-zcu102-revA.dts

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * dts file for Xilinx ZynqMP ZCU102 RevA
   4  *
   5  * (C) Copyright 2015 - 2021, Xilinx, Inc.
   6  *
   7  * Michal Simek <michal.simek@amd.com>
   8  */
   9
  10 /dts-v1/;
  11
  12 #include "zynqmp.dtsi"
  13 #include "zynqmp-clk-ccf.dtsi"
  14 #include <dt-bindings/input/input.h>
  15 #include <dt-bindings/gpio/gpio.h>
  16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
  17 #include <dt-bindings/phy/phy.h>
  18
  19 / {
  20         model = "ZynqMP ZCU102 RevA";
  21         compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
  22
  23         aliases {
  24                 ethernet0 = &gem3;
  25                 i2c0 = &i2c0;
  26                 i2c1 = &i2c1;
  27                 mmc0 = &sdhci1;
  28                 nvmem0 = &eeprom;
  29                 rtc0 = &rtc;
  30                 serial0 = &uart0;
  31                 serial1 = &uart1;
  32                 serial2 = &dcc;
  33                 spi0 = &qspi;
  34                 usb0 = &usb0;
  35         };
  36
  37         chosen {
  38                 bootargs = "earlycon";
  39                 stdout-path = "serial0:115200n8";
  40         };
  41
  42         memory@0 {
  43                 device_type = "memory";
  44                 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
  45         };
  46
  47         gpio-keys {
  48                 compatible = "gpio-keys";
  49                 autorepeat;
  50                 switch-19 {
  51                         label = "sw19";
  52                         gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
  53                         linux,code = <KEY_DOWN>;
  54                         wakeup-source;
  55                         autorepeat;
  56                 };
  57         };
  58
  59         leds {
  60                 compatible = "gpio-leds";
  61                 heartbeat-led {
  62                         label = "heartbeat";
  63                         gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
  64                         linux,default-trigger = "heartbeat";
  65                 };
  66         };
  67
  68         ina226-u76 {
  69                 compatible = "iio-hwmon";
  70                 io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;
  71         };
  72         ina226-u77 {
  73                 compatible = "iio-hwmon";
  74                 io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;
  75         };
  76         ina226-u78 {
  77                 compatible = "iio-hwmon";
  78                 io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;
  79         };
  80         ina226-u87 {
  81                 compatible = "iio-hwmon";
  82                 io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;
  83         };
  84         ina226-u85 {
  85                 compatible = "iio-hwmon";
  86                 io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;
  87         };
  88         ina226-u86 {
  89                 compatible = "iio-hwmon";
  90                 io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;
  91         };
  92         ina226-u93 {
  93                 compatible = "iio-hwmon";
  94                 io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;
  95         };
  96         ina226-u88 {
  97                 compatible = "iio-hwmon";
  98                 io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;
  99         };
 100         ina226-u15 {
 101                 compatible = "iio-hwmon";
 102                 io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;
 103         };
 104         ina226-u92 {
 105                 compatible = "iio-hwmon";
 106                 io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;
 107         };
 108         ina226-u79 {
 109                 compatible = "iio-hwmon";
 110                 io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;
 111         };
 112         ina226-u81 {
 113                 compatible = "iio-hwmon";
 114                 io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;
 115         };
 116         ina226-u80 {
 117                 compatible = "iio-hwmon";
 118                 io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;
 119         };
 120         ina226-u84 {
 121                 compatible = "iio-hwmon";
 122                 io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;
 123         };
 124         ina226-u16 {
 125                 compatible = "iio-hwmon";
 126                 io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;
 127         };
 128         ina226-u65 {
 129                 compatible = "iio-hwmon";
 130                 io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;
 131         };
 132         ina226-u74 {
 133                 compatible = "iio-hwmon";
 134                 io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;
 135         };
 136         ina226-u75 {
 137                 compatible = "iio-hwmon";
 138                 io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;
 139         };
 140
 141         /* 48MHz reference crystal */
 142         ref48: ref48M {
 143                 compatible = "fixed-clock";
 144                 #clock-cells = <0>;
 145                 clock-frequency = <48000000>;
 146         };
 147
 148         refhdmi: refhdmi {
 149                 compatible = "fixed-clock";
 150                 #clock-cells = <0>;
 151                 clock-frequency = <114285000>;
 152         };
 153 };
 154
 155 &can1 {
 156         status = "okay";
 157         pinctrl-names = "default";
 158         pinctrl-0 = <&pinctrl_can1_default>;
 159 };
 160
 161 &dcc {
 162         status = "okay";
 163 };
 164
 165 &fpd_dma_chan1 {
 166         status = "okay";
 167 };
 168
 169 &fpd_dma_chan2 {
 170         status = "okay";
 171 };
 172
 173 &fpd_dma_chan3 {
 174         status = "okay";
 175 };
 176
 177 &fpd_dma_chan4 {
 178         status = "okay";
 179 };
 180
 181 &fpd_dma_chan5 {
 182         status = "okay";
 183 };
 184
 185 &fpd_dma_chan6 {
 186         status = "okay";
 187 };
 188
 189 &fpd_dma_chan7 {
 190         status = "okay";
 191 };
 192
 193 &fpd_dma_chan8 {
 194         status = "okay";
 195 };
 196
 197 &gem3 {
 198         status = "okay";
 199         phy-handle = <&phy0>;
 200         phy-mode = "rgmii-id";
 201         pinctrl-names = "default";
 202         pinctrl-0 = <&pinctrl_gem3_default>;
 203         mdio: mdio {
 204                 #address-cells = <1>;
 205                 #size-cells = <0>;
 206                 phy0: ethernet-phy@21 {
 207                         #phy-cells = <1>;
 208                         compatible = "ethernet-phy-id2000.a231";
 209                         reg = <21>;
 210                         ti,rx-internal-delay = <0x8>;
 211                         ti,tx-internal-delay = <0xa>;
 212                         ti,fifo-depth = <0x1>;
 213                         ti,dp83867-rxctrl-strap-quirk;
 214                         reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;
 215                 };
 216         };
 217 };
 218
 219 &gpio {
 220         status = "okay";
 221         pinctrl-names = "default";
 222         pinctrl-0 = <&pinctrl_gpio_default>;
 223 };
 224
 225 &gpu {
 226         status = "okay";
 227 };
 228
 229 &i2c0 {
 230         status = "okay";
 231         clock-frequency = <400000>;
 232         pinctrl-names = "default", "gpio";
 233         pinctrl-0 = <&pinctrl_i2c0_default>;
 234         pinctrl-1 = <&pinctrl_i2c0_gpio>;
 235         scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 236         sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 237
 238         tca6416_u97: gpio@20 {
 239                 compatible = "ti,tca6416";
 240                 reg = <0x20>;
 241                 gpio-controller; /* IRQ not connected */
 242                 #gpio-cells = <2>;
 243                 gpio-line-names = "PS_GTR_LAN_SEL0", "PS_GTR_LAN_SEL1", "PS_GTR_LAN_SEL2", "PS_GTR_LAN_SEL3",
 244                                 "PCI_CLK_DIR_SEL", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B",
 245                                 "", "", "", "", "", "", "", "", "";
 246                 gtr-sel0-hog {
 247                         gpio-hog;
 248                         gpios = <0 0>;
 249                         output-low; /* PCIE = 0, DP = 1 */
 250                         line-name = "sel0";
 251                 };
 252                 gtr-sel1-hog {
 253                         gpio-hog;
 254                         gpios = <1 0>;
 255                         output-high; /* PCIE = 0, DP = 1 */
 256                         line-name = "sel1";
 257                 };
 258                 gtr-sel2-hog {
 259                         gpio-hog;
 260                         gpios = <2 0>;
 261                         output-high; /* PCIE = 0, USB0 = 1 */
 262                         line-name = "sel2";
 263                 };
 264                 gtr-sel3-hog {
 265                         gpio-hog;
 266                         gpios = <3 0>;
 267                         output-high; /* PCIE = 0, SATA = 1 */
 268                         line-name = "sel3";
 269                 };
 270         };
 271
 272         tca6416_u61: gpio@21 {
 273                 compatible = "ti,tca6416";
 274                 reg = <0x21>;
 275                 gpio-controller; /* IRQ not connected */
 276                 #gpio-cells = <2>;
 277                 gpio-line-names = "VCCPSPLL_EN", "MGTRAVCC_EN", "MGTRAVTT_EN", "VCCPSDDRPLL_EN", "MIO26_PMU_INPUT_LS",
 278                                 "PL_PMBUS_ALERT", "PS_PMBUS_ALERT", "MAXIM_PMBUS_ALERT", "PL_DDR4_VTERM_EN",
 279                                 "PL_DDR4_VPP_2V5_EN", "PS_DIMM_VDDQ_TO_PSVCCO_ON", "PS_DIMM_SUSPEND_EN",
 280                                 "PS_DDR4_VTERM_EN", "PS_DDR4_VPP_2V5_EN", "", "";
 281         };
 282
 283         i2c-mux@75 { /* u60 */
 284                 compatible = "nxp,pca9544";
 285                 #address-cells = <1>;
 286                 #size-cells = <0>;
 287                 reg = <0x75>;
 288                 i2c@0 {
 289                         #address-cells = <1>;
 290                         #size-cells = <0>;
 291                         reg = <0>;
 292                         /* PS_PMBUS */
 293                         u76: ina226@40 { /* u76 */
 294                                 compatible = "ti,ina226";
 295                                 #io-channel-cells = <1>;
 296                                 label = "ina226-u76";
 297                                 reg = <0x40>;
 298                                 shunt-resistor = <5000>;
 299                         };
 300                         u77: ina226@41 { /* u77 */
 301                                 compatible = "ti,ina226";
 302                                 #io-channel-cells = <1>;
 303                                 label = "ina226-u77";
 304                                 reg = <0x41>;
 305                                 shunt-resistor = <5000>;
 306                         };
 307                         u78: ina226@42 { /* u78 */
 308                                 compatible = "ti,ina226";
 309                                 #io-channel-cells = <1>;
 310                                 label = "ina226-u78";
 311                                 reg = <0x42>;
 312                                 shunt-resistor = <5000>;
 313                         };
 314                         u87: ina226@43 { /* u87 */
 315                                 compatible = "ti,ina226";
 316                                 #io-channel-cells = <1>;
 317                                 label = "ina226-u87";
 318                                 reg = <0x43>;
 319                                 shunt-resistor = <5000>;
 320                         };
 321                         u85: ina226@44 { /* u85 */
 322                                 compatible = "ti,ina226";
 323                                 #io-channel-cells = <1>;
 324                                 label = "ina226-u85";
 325                                 reg = <0x44>;
 326                                 shunt-resistor = <5000>;
 327                         };
 328                         u86: ina226@45 { /* u86 */
 329                                 compatible = "ti,ina226";
 330                                 #io-channel-cells = <1>;
 331                                 label = "ina226-u86";
 332                                 reg = <0x45>;
 333                                 shunt-resistor = <5000>;
 334                         };
 335                         u93: ina226@46 { /* u93 */
 336                                 compatible = "ti,ina226";
 337                                 #io-channel-cells = <1>;
 338                                 label = "ina226-u93";
 339                                 reg = <0x46>;
 340                                 shunt-resistor = <5000>;
 341                         };
 342                         u88: ina226@47 { /* u88 */
 343                                 compatible = "ti,ina226";
 344                                 #io-channel-cells = <1>;
 345                                 label = "ina226-u88";
 346                                 reg = <0x47>;
 347                                 shunt-resistor = <5000>;
 348                         };
 349                         u15: ina226@4a { /* u15 */
 350                                 compatible = "ti,ina226";
 351                                 #io-channel-cells = <1>;
 352                                 label = "ina226-u15";
 353                                 reg = <0x4a>;
 354                                 shunt-resistor = <5000>;
 355                         };
 356                         u92: ina226@4b { /* u92 */
 357                                 compatible = "ti,ina226";
 358                                 #io-channel-cells = <1>;
 359                                 label = "ina226-u92";
 360                                 reg = <0x4b>;
 361                                 shunt-resistor = <5000>;
 362                         };
 363                 };
 364                 i2c@1 {
 365                         #address-cells = <1>;
 366                         #size-cells = <0>;
 367                         reg = <1>;
 368                         /* PL_PMBUS */
 369                         u79: ina226@40 { /* u79 */
 370                                 compatible = "ti,ina226";
 371                                 #io-channel-cells = <1>;
 372                                 label = "ina226-u79";
 373                                 reg = <0x40>;
 374                                 shunt-resistor = <2000>;
 375                         };
 376                         u81: ina226@41 { /* u81 */
 377                                 compatible = "ti,ina226";
 378                                 #io-channel-cells = <1>;
 379                                 label = "ina226-u81";
 380                                 reg = <0x41>;
 381                                 shunt-resistor = <5000>;
 382                         };
 383                         u80: ina226@42 { /* u80 */
 384                                 compatible = "ti,ina226";
 385                                 #io-channel-cells = <1>;
 386                                 label = "ina226-u80";
 387                                 reg = <0x42>;
 388                                 shunt-resistor = <5000>;
 389                         };
 390                         u84: ina226@43 { /* u84 */
 391                                 compatible = "ti,ina226";
 392                                 #io-channel-cells = <1>;
 393                                 label = "ina226-u84";
 394                                 reg = <0x43>;
 395                                 shunt-resistor = <5000>;
 396                         };
 397                         u16: ina226@44 { /* u16 */
 398                                 compatible = "ti,ina226";
 399                                 #io-channel-cells = <1>;
 400                                 label = "ina226-u16";
 401                                 reg = <0x44>;
 402                                 shunt-resistor = <5000>;
 403                         };
 404                         u65: ina226@45 { /* u65 */
 405                                 compatible = "ti,ina226";
 406                                 #io-channel-cells = <1>;
 407                                 label = "ina226-u65";
 408                                 reg = <0x45>;
 409                                 shunt-resistor = <5000>;
 410                         };
 411                         u74: ina226@46 { /* u74 */
 412                                 compatible = "ti,ina226";
 413                                 #io-channel-cells = <1>;
 414                                 label = "ina226-u74";
 415                                 reg = <0x46>;
 416                                 shunt-resistor = <5000>;
 417                         };
 418                         u75: ina226@47 { /* u75 */
 419                                 compatible = "ti,ina226";
 420                                 #io-channel-cells = <1>;
 421                                 label = "ina226-u75";
 422                                 reg = <0x47>;
 423                                 shunt-resistor = <5000>;
 424                         };
 425                 };
 426                 i2c@2 {
 427                         #address-cells = <1>;
 428                         #size-cells = <0>;
 429                         reg = <2>;
 430                         /* MAXIM_PMBUS - 00 */
 431                         max15301@a { /* u46 */
 432                                 compatible = "maxim,max15301";
 433                                 reg = <0xa>;
 434                         };
 435                         max15303@b { /* u4 */
 436                                 compatible = "maxim,max15303";
 437                                 reg = <0xb>;
 438                         };
 439                         max15303@10 { /* u13 */
 440                                 compatible = "maxim,max15303";
 441                                 reg = <0x10>;
 442                         };
 443                         max15301@13 { /* u47 */
 444                                 compatible = "maxim,max15301";
 445                                 reg = <0x13>;
 446                         };
 447                         max15303@14 { /* u7 */
 448                                 compatible = "maxim,max15303";
 449                                 reg = <0x14>;
 450                         };
 451                         max15303@15 { /* u6 */
 452                                 compatible = "maxim,max15303";
 453                                 reg = <0x15>;
 454                         };
 455                         max15303@16 { /* u10 */
 456                                 compatible = "maxim,max15303";
 457                                 reg = <0x16>;
 458                         };
 459                         max15303@17 { /* u9 */
 460                                 compatible = "maxim,max15303";
 461                                 reg = <0x17>;
 462                         };
 463                         max15301@18 { /* u63 */
 464                                 compatible = "maxim,max15301";
 465                                 reg = <0x18>;
 466                         };
 467                         max15303@1a { /* u49 */
 468                                 compatible = "maxim,max15303";
 469                                 reg = <0x1a>;
 470                         };
 471                         max15303@1d { /* u18 */
 472                                 compatible = "maxim,max15303";
 473                                 reg = <0x1d>;
 474                         };
 475                         max15303@20 { /* u8 */
 476                                 compatible = "maxim,max15303";
 477                                 status = "disabled"; /* unreachable */
 478                                 reg = <0x20>;
 479                         };
 480                         max20751@72 { /* u95 */
 481                                 compatible = "maxim,max20751";
 482                                 reg = <0x72>;
 483                         };
 484                         max20751@73 { /* u96 */
 485                                 compatible = "maxim,max20751";
 486                                 reg = <0x73>;
 487                         };
 488                 };
 489                 /* Bus 3 is not connected */
 490         };
 491 };
 492
 493 &i2c1 {
 494         status = "okay";
 495         clock-frequency = <400000>;
 496         pinctrl-names = "default", "gpio";
 497         pinctrl-0 = <&pinctrl_i2c1_default>;
 498         pinctrl-1 = <&pinctrl_i2c1_gpio>;
 499         scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 500         sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 501
 502         /* PL i2c via PCA9306 - u45 */
 503         i2c-mux@74 { /* u34 */
 504                 compatible = "nxp,pca9548";
 505                 #address-cells = <1>;
 506                 #size-cells = <0>;
 507                 reg = <0x74>;
 508                 i2c@0 {
 509                         #address-cells = <1>;
 510                         #size-cells = <0>;
 511                         reg = <0>;
 512                         /*
 513                          * IIC_EEPROM 1kB memory which uses 256B blocks
 514                          * where every block has different address.
 515                          *    0 - 256B address 0x54
 516                          * 256B - 512B address 0x55
 517                          * 512B - 768B address 0x56
 518                          * 768B - 1024B address 0x57
 519                          */
 520                         eeprom: eeprom@54 { /* u23 */
 521                                 compatible = "atmel,24c08";
 522                                 reg = <0x54>;
 523                         };
 524                 };
 525                 i2c@1 {
 526                         #address-cells = <1>;
 527                         #size-cells = <0>;
 528                         reg = <1>;
 529                         si5341: clock-generator@36 { /* SI5341 - u69 */
 530                                 compatible = "silabs,si5341";
 531                                 reg = <0x36>;
 532                                 #clock-cells = <2>;
 533                                 #address-cells = <1>;
 534                                 #size-cells = <0>;
 535                                 clocks = <&ref48>;
 536                                 clock-names = "xtal";
 537                                 clock-output-names = "si5341";
 538
 539                                 si5341_0: out@0 {
 540                                         /* refclk0 for PS-GT, used for DP */
 541                                         reg = <0>;
 542                                         always-on;
 543                                 };
 544                                 si5341_2: out@2 {
 545                                         /* refclk2 for PS-GT, used for USB3 */
 546                                         reg = <2>;
 547                                         always-on;
 548                                 };
 549                                 si5341_3: out@3 {
 550                                         /* refclk3 for PS-GT, used for SATA */
 551                                         reg = <3>;
 552                                         always-on;
 553                                 };
 554                                 si5341_4: out@4 {
 555                                         /* refclk4 for PS-GT, used for PCIE slot */
 556                                         reg = <4>;
 557                                         always-on;
 558                                 };
 559                                 si5341_5: out@5 {
 560                                         /* refclk5 for PS-GT, used for PCIE */
 561                                         reg = <5>;
 562                                         always-on;
 563                                 };
 564                                 si5341_6: out@6 {
 565                                         /* refclk6 PL CLK125 */
 566                                         reg = <6>;
 567                                         always-on;
 568                                 };
 569                                 si5341_7: out@7 {
 570                                         /* refclk7 PL CLK74 */
 571                                         reg = <7>;
 572                                         always-on;
 573                                 };
 574                                 si5341_9: out@9 {
 575                                         /* refclk9 used for PS_REF_CLK 33.3 MHz */
 576                                         reg = <9>;
 577                                         always-on;
 578                                 };
 579                         };
 580                 };
 581                 i2c@2 {
 582                         #address-cells = <1>;
 583                         #size-cells = <0>;
 584                         reg = <2>;
 585                         si570_1: clock-generator@5d { /* USER SI570 - u42 */
 586                                 #clock-cells = <0>;
 587                                 compatible = "silabs,si570";
 588                                 reg = <0x5d>;
 589                                 temperature-stability = <50>;
 590                                 factory-fout = <300000000>;
 591                                 clock-frequency = <300000000>;
 592                                 clock-output-names = "si570_user";
 593                         };
 594                 };
 595                 i2c@3 {
 596                         #address-cells = <1>;
 597                         #size-cells = <0>;
 598                         reg = <3>;
 599                         si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */
 600                                 #clock-cells = <0>;
 601                                 compatible = "silabs,si570";
 602                                 reg = <0x5d>;
 603                                 temperature-stability = <50>; /* copy from zc702 */
 604                                 factory-fout = <156250000>;
 605                                 clock-frequency = <148500000>;
 606                                 clock-output-names = "si570_mgt";
 607                         };
 608                 };
 609                 i2c@4 {
 610                         #address-cells = <1>;
 611                         #size-cells = <0>;
 612                         reg = <4>;
 613                         si5328: clock-generator@69 {/* SI5328 - u20 */
 614                                 compatible = "silabs,si5328";
 615                                 reg = <0x69>;
 616                                 /*
 617                                  * Chip has interrupt present connected to PL
 618                                  * interrupt-parent = <&>;
 619                                  * interrupts = <>;
 620                                  */
 621                                 #address-cells = <1>;
 622                                 #size-cells = <0>;
 623                                 #clock-cells = <1>;
 624                                 clocks = <&refhdmi>;
 625                                 clock-names = "xtal";
 626                                 clock-output-names = "si5328";
 627
 628                                 si5328_clk: clk0@0 {
 629                                         reg = <0>;
 630                                         clock-frequency = <27000000>;
 631                                 };
 632                         };
 633                 };
 634                 /* 5 - 7 unconnected */
 635         };
 636
 637         i2c-mux@75 {
 638                 compatible = "nxp,pca9548"; /* u135 */
 639                 #address-cells = <1>;
 640                 #size-cells = <0>;
 641                 reg = <0x75>;
 642
 643                 i2c@0 {
 644                         #address-cells = <1>;
 645                         #size-cells = <0>;
 646                         reg = <0>;
 647                         /* HPC0_IIC */
 648                 };
 649                 i2c@1 {
 650                         #address-cells = <1>;
 651                         #size-cells = <0>;
 652                         reg = <1>;
 653                         /* HPC1_IIC */
 654                 };
 655                 i2c@2 {
 656                         #address-cells = <1>;
 657                         #size-cells = <0>;
 658                         reg = <2>;
 659                         /* SYSMON */
 660                 };
 661                 i2c@3 {
 662                         #address-cells = <1>;
 663                         #size-cells = <0>;
 664                         reg = <3>;
 665                         /* DDR4 SODIMM */
 666                 };
 667                 i2c@4 {
 668                         #address-cells = <1>;
 669                         #size-cells = <0>;
 670                         reg = <4>;
 671                         /* SEP 3 */
 672                 };
 673                 i2c@5 {
 674                         #address-cells = <1>;
 675                         #size-cells = <0>;
 676                         reg = <5>;
 677                         /* SEP 2 */
 678                 };
 679                 i2c@6 {
 680                         #address-cells = <1>;
 681                         #size-cells = <0>;
 682                         reg = <6>;
 683                         /* SEP 1 */
 684                 };
 685                 i2c@7 {
 686                         #address-cells = <1>;
 687                         #size-cells = <0>;
 688                         reg = <7>;
 689                         /* SEP 0 */
 690                 };
 691         };
 692 };
 693
 694 &pinctrl0 {
 695         status = "okay";
 696         pinctrl_i2c0_default: i2c0-default {
 697                 mux {
 698                         groups = "i2c0_3_grp";
 699                         function = "i2c0";
 700                 };
 701
 702                 conf {
 703                         groups = "i2c0_3_grp";
 704                         bias-pull-up;
 705                         slew-rate = <SLEW_RATE_SLOW>;
 706                         power-source = <IO_STANDARD_LVCMOS18>;
 707                 };
 708         };
 709
 710         pinctrl_i2c0_gpio: i2c0-gpio {
 711                 mux {
 712                         groups = "gpio0_14_grp", "gpio0_15_grp";
 713                         function = "gpio0";
 714                 };
 715
 716                 conf {
 717                         groups = "gpio0_14_grp", "gpio0_15_grp";
 718                         slew-rate = <SLEW_RATE_SLOW>;
 719                         power-source = <IO_STANDARD_LVCMOS18>;
 720                 };
 721         };
 722
 723         pinctrl_i2c1_default: i2c1-default {
 724                 mux {
 725                         groups = "i2c1_4_grp";
 726                         function = "i2c1";
 727                 };
 728
 729                 conf {
 730                         groups = "i2c1_4_grp";
 731                         bias-pull-up;
 732                         slew-rate = <SLEW_RATE_SLOW>;
 733                         power-source = <IO_STANDARD_LVCMOS18>;
 734                 };
 735         };
 736
 737         pinctrl_i2c1_gpio: i2c1-gpio {
 738                 mux {
 739                         groups = "gpio0_16_grp", "gpio0_17_grp";
 740                         function = "gpio0";
 741                 };
 742
 743                 conf {
 744                         groups = "gpio0_16_grp", "gpio0_17_grp";
 745                         slew-rate = <SLEW_RATE_SLOW>;
 746                         power-source = <IO_STANDARD_LVCMOS18>;
 747                 };
 748         };
 749
 750         pinctrl_uart0_default: uart0-default {
 751                 mux {
 752                         groups = "uart0_4_grp";
 753                         function = "uart0";
 754                 };
 755
 756                 conf {
 757                         groups = "uart0_4_grp";
 758                         slew-rate = <SLEW_RATE_SLOW>;
 759                         power-source = <IO_STANDARD_LVCMOS18>;
 760                 };
 761
 762                 conf-rx {
 763                         pins = "MIO18";
 764                         bias-high-impedance;
 765                 };
 766
 767                 conf-tx {
 768                         pins = "MIO19";
 769                         bias-disable;
 770                 };
 771         };
 772
 773         pinctrl_uart1_default: uart1-default {
 774                 mux {
 775                         groups = "uart1_5_grp";
 776                         function = "uart1";
 777                 };
 778
 779                 conf {
 780                         groups = "uart1_5_grp";
 781                         slew-rate = <SLEW_RATE_SLOW>;
 782                         power-source = <IO_STANDARD_LVCMOS18>;
 783                 };
 784
 785                 conf-rx {
 786                         pins = "MIO21";
 787                         bias-high-impedance;
 788                 };
 789
 790                 conf-tx {
 791                         pins = "MIO20";
 792                         bias-disable;
 793                 };
 794         };
 795
 796         pinctrl_usb0_default: usb0-default {
 797                 mux {
 798                         groups = "usb0_0_grp";
 799                         function = "usb0";
 800                 };
 801
 802                 conf {
 803                         groups = "usb0_0_grp";
 804                         power-source = <IO_STANDARD_LVCMOS18>;
 805                 };
 806
 807                 conf-rx {
 808                         pins = "MIO52", "MIO53", "MIO55";
 809                         bias-high-impedance;
 810                         drive-strength = <12>;
 811                         slew-rate = <SLEW_RATE_FAST>;
 812                 };
 813
 814                 conf-tx {
 815                         pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
 816                                "MIO60", "MIO61", "MIO62", "MIO63";
 817                         bias-disable;
 818                         drive-strength = <4>;
 819                         slew-rate = <SLEW_RATE_SLOW>;
 820                 };
 821         };
 822
 823         pinctrl_gem3_default: gem3-default {
 824                 mux {
 825                         function = "ethernet3";
 826                         groups = "ethernet3_0_grp";
 827                 };
 828
 829                 conf {
 830                         groups = "ethernet3_0_grp";
 831                         slew-rate = <SLEW_RATE_SLOW>;
 832                         power-source = <IO_STANDARD_LVCMOS18>;
 833                 };
 834
 835                 conf-rx {
 836                         pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
 837                                                                         "MIO75";
 838                         bias-high-impedance;
 839                         low-power-disable;
 840                 };
 841
 842                 conf-tx {
 843                         pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
 844                                                                         "MIO69";
 845                         bias-disable;
 846                         low-power-enable;
 847                 };
 848
 849                 mux-mdio {
 850                         function = "mdio3";
 851                         groups = "mdio3_0_grp";
 852                 };
 853
 854                 conf-mdio {
 855                         groups = "mdio3_0_grp";
 856                         slew-rate = <SLEW_RATE_SLOW>;
 857                         power-source = <IO_STANDARD_LVCMOS18>;
 858                         bias-disable;
 859                 };
 860         };
 861
 862         pinctrl_can1_default: can1-default {
 863                 mux {
 864                         function = "can1";
 865                         groups = "can1_6_grp";
 866                 };
 867
 868                 conf {
 869                         groups = "can1_6_grp";
 870                         slew-rate = <SLEW_RATE_SLOW>;
 871                         power-source = <IO_STANDARD_LVCMOS18>;
 872                 };
 873
 874                 conf-rx {
 875                         pins = "MIO25";
 876                         bias-high-impedance;
 877                 };
 878
 879                 conf-tx {
 880                         pins = "MIO24";
 881                         bias-disable;
 882                 };
 883         };
 884
 885         pinctrl_sdhci1_default: sdhci1-default {
 886                 mux {
 887                         groups = "sdio1_0_grp";
 888                         function = "sdio1";
 889                 };
 890
 891                 conf {
 892                         groups = "sdio1_0_grp";
 893                         slew-rate = <SLEW_RATE_SLOW>;
 894                         power-source = <IO_STANDARD_LVCMOS18>;
 895                         bias-disable;
 896                 };
 897
 898                 mux-cd {
 899                         groups = "sdio1_cd_0_grp";
 900                         function = "sdio1_cd";
 901                 };
 902
 903                 conf-cd {
 904                         groups = "sdio1_cd_0_grp";
 905                         bias-high-impedance;
 906                         bias-pull-up;
 907                         slew-rate = <SLEW_RATE_SLOW>;
 908                         power-source = <IO_STANDARD_LVCMOS18>;
 909                 };
 910
 911                 mux-wp {
 912                         groups = "sdio1_wp_0_grp";
 913                         function = "sdio1_wp";
 914                 };
 915
 916                 conf-wp {
 917                         groups = "sdio1_wp_0_grp";
 918                         bias-high-impedance;
 919                         bias-pull-up;
 920                         slew-rate = <SLEW_RATE_SLOW>;
 921                         power-source = <IO_STANDARD_LVCMOS18>;
 922                 };
 923         };
 924
 925         pinctrl_gpio_default: gpio-default {
 926                 mux-sw {
 927                         function = "gpio0";
 928                         groups = "gpio0_22_grp", "gpio0_23_grp";
 929                 };
 930
 931                 conf-sw {
 932                         groups = "gpio0_22_grp", "gpio0_23_grp";
 933                         slew-rate = <SLEW_RATE_SLOW>;
 934                         power-source = <IO_STANDARD_LVCMOS18>;
 935                 };
 936
 937                 mux-msp {
 938                         function = "gpio0";
 939                         groups = "gpio0_13_grp", "gpio0_38_grp";
 940                 };
 941
 942                 conf-msp {
 943                         groups = "gpio0_13_grp", "gpio0_38_grp";
 944                         slew-rate = <SLEW_RATE_SLOW>;
 945                         power-source = <IO_STANDARD_LVCMOS18>;
 946                 };
 947
 948                 conf-pull-up {
 949                         pins = "MIO22", "MIO23";
 950                         bias-pull-up;
 951                 };
 952
 953                 conf-pull-none {
 954                         pins = "MIO13", "MIO38";
 955                         bias-disable;
 956                 };
 957         };
 958 };
 959
 960 &pcie {
 961         status = "okay";
 962 };
 963
 964 &psgtr {
 965         status = "okay";
 966         /* pcie, sata, usb3, dp */
 967         clocks = <&si5341 0 5>, <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;
 968         clock-names = "ref0", "ref1", "ref2", "ref3";
 969 };
 970
 971 &qspi {
 972         status = "okay";
 973         is-dual = <1>;
 974         flash@0 {
 975                 compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
 976                 #address-cells = <1>;
 977                 #size-cells = <1>;
 978                 reg = <0x0>;
 979                 spi-tx-bus-width = <4>;
 980                 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
 981                 spi-max-frequency = <108000000>; /* Based on DC1 spec */
 982                 partition@0 { /* for testing purpose */
 983                         label = "qspi-fsbl-uboot";
 984                         reg = <0x0 0x100000>;
 985                 };
 986                 partition@100000 { /* for testing purpose */
 987                         label = "qspi-linux";
 988                         reg = <0x100000 0x500000>;
 989                 };
 990                 partition@600000 { /* for testing purpose */
 991                         label = "qspi-device-tree";
 992                         reg = <0x600000 0x20000>;
 993                 };
 994                 partition@620000 { /* for testing purpose */
 995                         label = "qspi-rootfs";
 996                         reg = <0x620000 0x5E0000>;
 997                 };
 998         };
 999 };
1000
1001 &rtc {
1002         status = "okay";
1003 };
1004
1005 &sata {
1006         status = "okay";
1007         /* SATA OOB timing settings */
1008         ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
1009         ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
1010         ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
1011         ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
1012         ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
1013         ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
1014         ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
1015         ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
1016         phy-names = "sata-phy";
1017         phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
1018 };
1019
1020 /* SD1 with level shifter */
1021 &sdhci1 {
1022         status = "okay";
1023         /*
1024          * 1.0 revision has level shifter and this property should be
1025          * removed for supporting UHS mode
1026          */
1027         no-1-8-v;
1028         pinctrl-names = "default";
1029         pinctrl-0 = <&pinctrl_sdhci1_default>;
1030         xlnx,mio-bank = <1>;
1031 };
1032
1033 &uart0 {
1034         status = "okay";
1035         pinctrl-names = "default";
1036         pinctrl-0 = <&pinctrl_uart0_default>;
1037 };
1038
1039 &uart1 {
1040         status = "okay";
1041         pinctrl-names = "default";
1042         pinctrl-0 = <&pinctrl_uart1_default>;
1043 };
1044
1045 /* ULPI SMSC USB3320 */
1046 &usb0 {
1047         status = "okay";
1048         pinctrl-names = "default";
1049         pinctrl-0 = <&pinctrl_usb0_default>;
1050         phy-names = "usb3-phy";
1051         phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
1052 };
1053
1054 &dwc3_0 {
1055         status = "okay";
1056         dr_mode = "host";
1057         snps,usb3_lpm_capable;
1058         maximum-speed = "super-speed";
1059 };
1060
1061 &watchdog0 {
1062         status = "okay";
1063 };
1064
1065 &xilinx_ams {
1066         status = "okay";
1067 };
1068
1069 &ams_ps {
1070         status = "okay";
1071 };
1072
1073 &ams_pl {
1074         status = "okay";
1075 };
1076
1077 &zynqmp_dpdma {
1078         status = "okay";
1079 };
1080
1081 &zynqmp_dpsub {
1082         status = "okay";
1083         phy-names = "dp-phy0";
1084         phys = <&psgtr 1 PHY_TYPE_DP 0 3>;
1085 };