1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP ZCU102 RevA
5 * (C) Copyright 2015 - 2018, Xilinx, Inc.
7 * Michal Simek <michal.simek@xilinx.com>
12 #include "zynqmp.dtsi"
13 #include "zynqmp-clk-ccf.dtsi"
14 #include <dt-bindings/input/input.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
17 #include <dt-bindings/phy/phy.h>
20 model = "ZynqMP ZCU102 RevA";
21 compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
38 bootargs = "earlycon";
39 stdout-path = "serial0:115200n8";
43 device_type = "memory";
44 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
48 compatible = "gpio-keys";
54 gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
55 linux,code = <KEY_DOWN>;
62 compatible = "gpio-leds";
65 gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
66 linux,default-trigger = "heartbeat";
73 pinctrl-names = "default";
74 pinctrl-0 = <&pinctrl_can1_default>;
115 phy-handle = <&phy0>;
116 phy-mode = "rgmii-id";
117 pinctrl-names = "default";
118 pinctrl-0 = <&pinctrl_gem3_default>;
121 ti,rx-internal-delay = <0x8>;
122 ti,tx-internal-delay = <0xa>;
123 ti,fifo-depth = <0x1>;
129 pinctrl-names = "default";
130 pinctrl-0 = <&pinctrl_gpio_default>;
139 clock-frequency = <400000>;
140 pinctrl-names = "default", "gpio";
141 pinctrl-0 = <&pinctrl_i2c0_default>;
142 pinctrl-1 = <&pinctrl_i2c0_gpio>;
143 scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
144 sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
146 tca6416_u97: gpio@20 {
148 * Enable all GTs to out from U-Boot
149 * i2c mw 20 6 0 - setup IO to output
150 * i2c mw 20 2 ef - setup output values on pins 0-7
151 * i2c mw 20 3 ff - setup output values on pins 10-17
153 compatible = "ti,tca6416";
160 * 0 - PS_GTR_LAN_SEL0
161 * 1 - PS_GTR_LAN_SEL1
162 * 2 - PS_GTR_LAN_SEL2
163 * 3 - PS_GTR_LAN_SEL3
164 * 4 - PCI_CLK_DIR_SEL
165 * 5 - IIC_MUX_RESET_B
166 * 6 - GEM3_EXP_RESET_B
167 * 7, 10 - 17 - not connected
173 output-low; /* PCIE = 0, DP = 1 */
179 output-high; /* PCIE = 0, DP = 1 */
185 output-high; /* PCIE = 0, USB0 = 1 */
191 output-high; /* PCIE = 0, SATA = 1 */
196 tca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */
197 compatible = "ti,tca6416";
208 * 4 - MIO26_PMU_INPUT_LS
211 * 7 - MAXIM_PMBUS_ALERT
212 * 10 - PL_DDR4_VTERM_EN
213 * 11 - PL_DDR4_VPP_2V5_EN
214 * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON
215 * 13 - PS_DIMM_SUSPEND_EN
216 * 14 - PS_DDR4_VTERM_EN
217 * 15 - PS_DDR4_VPP_2V5_EN
218 * 16 - 17 - not connected
222 i2c-mux@75 { /* u60 */
223 compatible = "nxp,pca9544";
224 #address-cells = <1>;
227 i2c@0 { /* i2c mw 75 0 1 */
228 #address-cells = <1>;
232 ina226@40 { /* u76 */
233 compatible = "ti,ina226";
235 shunt-resistor = <5000>;
237 ina226@41 { /* u77 */
238 compatible = "ti,ina226";
240 shunt-resistor = <5000>;
242 ina226@42 { /* u78 */
243 compatible = "ti,ina226";
245 shunt-resistor = <5000>;
247 ina226@43 { /* u87 */
248 compatible = "ti,ina226";
250 shunt-resistor = <5000>;
252 ina226@44 { /* u85 */
253 compatible = "ti,ina226";
255 shunt-resistor = <5000>;
257 ina226@45 { /* u86 */
258 compatible = "ti,ina226";
260 shunt-resistor = <5000>;
262 ina226@46 { /* u93 */
263 compatible = "ti,ina226";
265 shunt-resistor = <5000>;
267 ina226@47 { /* u88 */
268 compatible = "ti,ina226";
270 shunt-resistor = <5000>;
272 ina226@4a { /* u15 */
273 compatible = "ti,ina226";
275 shunt-resistor = <5000>;
277 ina226@4b { /* u92 */
278 compatible = "ti,ina226";
280 shunt-resistor = <5000>;
283 i2c@1 { /* i2c mw 75 0 1 */
284 #address-cells = <1>;
288 ina226@40 { /* u79 */
289 compatible = "ti,ina226";
291 shunt-resistor = <2000>;
293 ina226@41 { /* u81 */
294 compatible = "ti,ina226";
296 shunt-resistor = <5000>;
298 ina226@42 { /* u80 */
299 compatible = "ti,ina226";
301 shunt-resistor = <5000>;
303 ina226@43 { /* u84 */
304 compatible = "ti,ina226";
306 shunt-resistor = <5000>;
308 ina226@44 { /* u16 */
309 compatible = "ti,ina226";
311 shunt-resistor = <5000>;
313 ina226@45 { /* u65 */
314 compatible = "ti,ina226";
316 shunt-resistor = <5000>;
318 ina226@46 { /* u74 */
319 compatible = "ti,ina226";
321 shunt-resistor = <5000>;
323 ina226@47 { /* u75 */
324 compatible = "ti,ina226";
326 shunt-resistor = <5000>;
329 i2c@2 { /* i2c mw 75 0 1 */
330 #address-cells = <1>;
333 /* MAXIM_PMBUS - 00 */
334 max15301@a { /* u46 */
335 compatible = "maxim,max15301";
338 max15303@b { /* u4 */
339 compatible = "maxim,max15303";
342 max15303@10 { /* u13 */
343 compatible = "maxim,max15303";
346 max15301@13 { /* u47 */
347 compatible = "maxim,max15301";
350 max15303@14 { /* u7 */
351 compatible = "maxim,max15303";
354 max15303@15 { /* u6 */
355 compatible = "maxim,max15303";
358 max15303@16 { /* u10 */
359 compatible = "maxim,max15303";
362 max15303@17 { /* u9 */
363 compatible = "maxim,max15303";
366 max15301@18 { /* u63 */
367 compatible = "maxim,max15301";
370 max15303@1a { /* u49 */
371 compatible = "maxim,max15303";
374 max15303@1d { /* u18 */
375 compatible = "maxim,max15303";
378 max15303@20 { /* u8 */
379 compatible = "maxim,max15303";
380 status = "disabled"; /* unreachable */
384 max20751@72 { /* u95 */
385 compatible = "maxim,max20751";
388 max20751@73 { /* u96 */
389 compatible = "maxim,max20751";
393 /* Bus 3 is not connected */
399 clock-frequency = <400000>;
400 pinctrl-names = "default", "gpio";
401 pinctrl-0 = <&pinctrl_i2c1_default>;
402 pinctrl-1 = <&pinctrl_i2c1_gpio>;
403 scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
404 sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
406 /* PL i2c via PCA9306 - u45 */
407 i2c-mux@74 { /* u34 */
408 compatible = "nxp,pca9548";
409 #address-cells = <1>;
412 i2c@0 { /* i2c mw 74 0 1 */
413 #address-cells = <1>;
417 * IIC_EEPROM 1kB memory which uses 256B blocks
418 * where every block has different address.
419 * 0 - 256B address 0x54
420 * 256B - 512B address 0x55
421 * 512B - 768B address 0x56
422 * 768B - 1024B address 0x57
424 eeprom: eeprom@54 { /* u23 */
425 compatible = "at,24c08";
429 i2c@1 { /* i2c mw 74 0 2 */
430 #address-cells = <1>;
433 si5341: clock-generator1@36 { /* SI5341 - u69 */
434 compatible = "si5341";
439 i2c@2 { /* i2c mw 74 0 4 */
440 #address-cells = <1>;
443 si570_1: clock-generator2@5d { /* USER SI570 - u42 */
445 compatible = "silabs,si570";
447 temperature-stability = <50>;
448 factory-fout = <300000000>;
449 clock-frequency = <300000000>;
452 i2c@3 { /* i2c mw 74 0 8 */
453 #address-cells = <1>;
456 si570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */
458 compatible = "silabs,si570";
460 temperature-stability = <50>; /* copy from zc702 */
461 factory-fout = <156250000>;
462 clock-frequency = <148500000>;
465 i2c@4 { /* i2c mw 74 0 10 */
466 #address-cells = <1>;
469 si5328: clock-generator4@69 {/* SI5328 - u20 */
470 compatible = "silabs,si5328";
473 * Chip has interrupt present connected to PL
474 * interrupt-parent = <&>;
479 /* 5 - 7 unconnected */
483 compatible = "nxp,pca9548"; /* u135 */
484 #address-cells = <1>;
489 #address-cells = <1>;
495 #address-cells = <1>;
501 #address-cells = <1>;
506 i2c@3 { /* i2c mw 75 0 8 */
507 #address-cells = <1>;
528 #address-cells = <1>;
534 #address-cells = <1>;
540 #address-cells = <1>;
546 #address-cells = <1>;
556 pinctrl_i2c0_default: i2c0-default {
558 groups = "i2c0_3_grp";
563 groups = "i2c0_3_grp";
565 slew-rate = <SLEW_RATE_SLOW>;
566 io-standard = <IO_STANDARD_LVCMOS18>;
570 pinctrl_i2c0_gpio: i2c0-gpio {
572 groups = "gpio0_14_grp", "gpio0_15_grp";
577 groups = "gpio0_14_grp", "gpio0_15_grp";
578 slew-rate = <SLEW_RATE_SLOW>;
579 io-standard = <IO_STANDARD_LVCMOS18>;
583 pinctrl_i2c1_default: i2c1-default {
585 groups = "i2c1_4_grp";
590 groups = "i2c1_4_grp";
592 slew-rate = <SLEW_RATE_SLOW>;
593 io-standard = <IO_STANDARD_LVCMOS18>;
597 pinctrl_i2c1_gpio: i2c1-gpio {
599 groups = "gpio0_16_grp", "gpio0_17_grp";
604 groups = "gpio0_16_grp", "gpio0_17_grp";
605 slew-rate = <SLEW_RATE_SLOW>;
606 io-standard = <IO_STANDARD_LVCMOS18>;
610 pinctrl_uart0_default: uart0-default {
612 groups = "uart0_4_grp";
617 groups = "uart0_4_grp";
618 slew-rate = <SLEW_RATE_SLOW>;
619 io-standard = <IO_STANDARD_LVCMOS18>;
633 pinctrl_uart1_default: uart1-default {
635 groups = "uart1_5_grp";
640 groups = "uart1_5_grp";
641 slew-rate = <SLEW_RATE_SLOW>;
642 io-standard = <IO_STANDARD_LVCMOS18>;
656 pinctrl_usb0_default: usb0-default {
658 groups = "usb0_0_grp";
663 groups = "usb0_0_grp";
664 slew-rate = <SLEW_RATE_SLOW>;
665 io-standard = <IO_STANDARD_LVCMOS18>;
669 pins = "MIO52", "MIO53", "MIO55";
674 pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
675 "MIO60", "MIO61", "MIO62", "MIO63";
680 pinctrl_gem3_default: gem3-default {
682 function = "ethernet3";
683 groups = "ethernet3_0_grp";
687 groups = "ethernet3_0_grp";
688 slew-rate = <SLEW_RATE_SLOW>;
689 io-standard = <IO_STANDARD_LVCMOS18>;
693 pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
700 pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
708 groups = "mdio3_0_grp";
712 groups = "mdio3_0_grp";
713 slew-rate = <SLEW_RATE_SLOW>;
714 io-standard = <IO_STANDARD_LVCMOS18>;
719 pinctrl_can1_default: can1-default {
722 groups = "can1_6_grp";
726 groups = "can1_6_grp";
727 slew-rate = <SLEW_RATE_SLOW>;
728 io-standard = <IO_STANDARD_LVCMOS18>;
742 pinctrl_sdhci1_default: sdhci1-default {
744 groups = "sdio1_0_grp";
749 groups = "sdio1_0_grp";
750 slew-rate = <SLEW_RATE_SLOW>;
751 io-standard = <IO_STANDARD_LVCMOS18>;
756 groups = "sdio1_0_cd_grp";
757 function = "sdio1_cd";
761 groups = "sdio1_0_cd_grp";
764 slew-rate = <SLEW_RATE_SLOW>;
765 io-standard = <IO_STANDARD_LVCMOS18>;
769 groups = "sdio1_0_wp_grp";
770 function = "sdio1_wp";
774 groups = "sdio1_0_wp_grp";
777 slew-rate = <SLEW_RATE_SLOW>;
778 io-standard = <IO_STANDARD_LVCMOS18>;
782 pinctrl_gpio_default: gpio-default {
785 groups = "gpio0_22_grp", "gpio0_23_grp";
789 groups = "gpio0_22_grp", "gpio0_23_grp";
790 slew-rate = <SLEW_RATE_SLOW>;
791 io-standard = <IO_STANDARD_LVCMOS18>;
796 groups = "gpio0_13_grp", "gpio0_38_grp";
800 groups = "gpio0_13_grp", "gpio0_38_grp";
801 slew-rate = <SLEW_RATE_SLOW>;
802 io-standard = <IO_STANDARD_LVCMOS18>;
806 pins = "MIO22", "MIO23";
811 pins = "MIO13", "MIO38";
825 compatible = "m25p80"; /* 32MB */
826 #address-cells = <1>;
829 spi-tx-bus-width = <1>;
830 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
831 spi-max-frequency = <108000000>; /* Based on DC1 spec */
832 partition@qspi-fsbl-uboot { /* for testing purpose */
833 label = "qspi-fsbl-uboot";
834 reg = <0x0 0x100000>;
836 partition@qspi-linux { /* for testing purpose */
837 label = "qspi-linux";
838 reg = <0x100000 0x500000>;
840 partition@qspi-device-tree { /* for testing purpose */
841 label = "qspi-device-tree";
842 reg = <0x600000 0x20000>;
844 partition@qspi-rootfs { /* for testing purpose */
845 label = "qspi-rootfs";
846 reg = <0x620000 0x5E0000>;
857 /* SATA OOB timing settings */
858 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
859 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
860 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
861 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
862 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
863 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
864 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
865 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
866 phy-names = "sata-phy";
867 phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;
870 /* SD1 with level shifter */
873 pinctrl-names = "default";
874 pinctrl-0 = <&pinctrl_sdhci1_default>;
875 no-1-8-v; /* for 1.0 silicon */
885 pinctrl-names = "default";
886 pinctrl-0 = <&pinctrl_uart0_default>;
891 pinctrl-names = "default";
892 pinctrl-0 = <&pinctrl_uart1_default>;
895 /* ULPI SMSC USB3320 */
898 pinctrl-names = "default";
899 pinctrl-0 = <&pinctrl_usb0_default>;
905 snps,usb3_lpm_capable;
906 phy-names = "usb3-phy";
907 phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
908 maximum-speed = "super-speed";
953 &xlnx_dp_snd_codec0 {