2 * dts file for Xilinx ZynqMP ZCU102 RevA
4 * (C) Copyright 2015, Xilinx, Inc.
6 * Michal Simek <michal.simek@xilinx.com>
8 * SPDX-License-Identifier: GPL-2.0+
13 #include "zynqmp.dtsi"
14 #include "zynqmp-clk.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
18 model = "ZynqMP ZCU102 RevA";
19 compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
36 bootargs = "earlycon";
37 stdout-path = "serial0:115200n8";
41 device_type = "memory";
42 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
46 compatible = "gpio-keys";
52 gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
53 linux,code = <108>; /* down */
60 compatible = "gpio-leds";
63 gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
64 linux,default-trigger = "heartbeat";
77 /* fpd_dma clk 667MHz, lpd_dma 500MHz */
80 xlnx,include-sg; /* for testing purpose */
81 xlnx,overfetch; /* for testing purpose */
82 xlnx,ratectrl = <0>; /* for testing purpose */
83 xlnx,src-issue = <31>;
88 xlnx,ratectrl = <100>; /* for testing purpose */
89 xlnx,src-issue = <4>; /* for testing purpose */
98 xlnx,include-sg; /* for testing purpose */
107 xlnx,include-sg; /* for testing purpose */
116 xlnx,include-sg; /* for testing purpose */
121 phy-handle = <&phy0>;
122 phy-mode = "rgmii-id";
125 ti,rx-internal-delay = <0x8>;
126 ti,tx-internal-delay = <0xa>;
127 ti,fifo-depth = <0x1>;
141 clock-frequency = <400000>;
143 tca6416_u97: gpio@20 {
145 * Enable all GTs to out from U-Boot
146 * i2c mw 20 6 0 - setup IO to output
147 * i2c mw 20 2 ef - setup output values on pins 0-7
148 * i2c mw 20 3 ff - setup output values on pins 10-17
150 compatible = "ti,tca6416";
157 * 0 - PS_GTR_LAN_SEL0
158 * 1 - PS_GTR_LAN_SEL1
159 * 2 - PS_GTR_LAN_SEL2
160 * 3 - PS_GTR_LAN_SEL3
161 * 4 - PCI_CLK_DIR_SEL
162 * 5 - IIC_MUX_RESET_B
163 * 6 - GEM3_EXP_RESET_B
164 * 7, 10 - 17 - not connected
170 output-low; /* PCIE = 0, DP = 1 */
176 output-high; /* PCIE = 0, DP = 1 */
182 output-high; /* PCIE = 0, USB0 = 1 */
188 output-high; /* PCIE = 0, SATA = 1 */
193 tca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */
194 compatible = "ti,tca6416";
205 * 4 - MIO26_PMU_INPUT_LS
208 * 7 - MAXIM_PMBUS_ALERT
209 * 10 - PL_DDR4_VTERM_EN
210 * 11 - PL_DDR4_VPP_2V5_EN
211 * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON
212 * 13 - PS_DIMM_SUSPEND_EN
213 * 14 - PS_DDR4_VTERM_EN
214 * 15 - PS_DDR4_VPP_2V5_EN
215 * 16 - 17 - not connected
219 i2cswitch@75 { /* u60 */
220 compatible = "nxp,pca9544";
221 #address-cells = <1>;
224 i2c@0 { /* i2c mw 75 0 1 */
225 #address-cells = <1>;
229 ina226@40 { /* u76 */
230 compatible = "ti,ina226";
232 shunt-resistor = <5000>;
234 ina226@41 { /* u77 */
235 compatible = "ti,ina226";
237 shunt-resistor = <5000>;
239 ina226@42 { /* u78 */
240 compatible = "ti,ina226";
242 shunt-resistor = <5000>;
244 ina226@43 { /* u87 */
245 compatible = "ti,ina226";
247 shunt-resistor = <5000>;
249 ina226@44 { /* u85 */
250 compatible = "ti,ina226";
252 shunt-resistor = <5000>;
254 ina226@45 { /* u86 */
255 compatible = "ti,ina226";
257 shunt-resistor = <5000>;
259 ina226@46 { /* u93 */
260 compatible = "ti,ina226";
262 shunt-resistor = <5000>;
264 ina226@47 { /* u88 */
265 compatible = "ti,ina226";
267 shunt-resistor = <5000>;
269 ina226@4a { /* u15 */
270 compatible = "ti,ina226";
272 shunt-resistor = <5000>;
274 ina226@4b { /* u92 */
275 compatible = "ti,ina226";
277 shunt-resistor = <5000>;
280 i2c@1 { /* i2c mw 75 0 1 */
281 #address-cells = <1>;
285 ina226@40 { /* u79 */
286 compatible = "ti,ina226";
288 shunt-resistor = <2000>;
290 ina226@41 { /* u81 */
291 compatible = "ti,ina226";
293 shunt-resistor = <5000>;
295 ina226@42 { /* u80 */
296 compatible = "ti,ina226";
298 shunt-resistor = <5000>;
300 ina226@43 { /* u84 */
301 compatible = "ti,ina226";
303 shunt-resistor = <5000>;
305 ina226@44 { /* u16 */
306 compatible = "ti,ina226";
308 shunt-resistor = <5000>;
310 ina226@45 { /* u65 */
311 compatible = "ti,ina226";
313 shunt-resistor = <5000>;
315 ina226@46 { /* u74 */
316 compatible = "ti,ina226";
318 shunt-resistor = <5000>;
320 ina226@47 { /* u75 */
321 compatible = "ti,ina226";
323 shunt-resistor = <5000>;
326 i2c@2 { /* i2c mw 75 0 1 */
327 #address-cells = <1>;
330 /* MAXIM_PMBUS - 00 */
331 max15301@a { /* u46 */
332 compatible = "max15301";
335 max15303@b { /* u4 */
336 compatible = "max15303";
339 max15303@10 { /* u13 */
340 compatible = "max15303";
343 max15301@13 { /* u47 */
344 compatible = "max15301";
347 max15303@14 { /* u7 */
348 compatible = "max15303";
351 max15303@15 { /* u6 */
352 compatible = "max15303";
355 max15303@16 { /* u10 */
356 compatible = "max15303";
359 max15303@17 { /* u9 */
360 compatible = "max15303";
363 max15301@18 { /* u63 */
364 compatible = "max15301";
367 max15303@1a { /* u49 */
368 compatible = "max15303";
371 max15303@1d { /* u18 */
372 compatible = "max15303";
375 max15303@20 { /* u8 */
376 compatible = "max15303";
377 status = "disabled"; /* unreachable */
381 /* drivers/hwmon/pmbus/Kconfig:86: be called max20751.
382 drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o
384 max20751@72 { /* u95 FIXME - not detected */
385 compatible = "max20751";
388 max20751@73 { /* u96 FIXME - not detected */
389 compatible = "max20751";
393 /* Bus 3 is not connected */
396 /* FIXME PMOD - j160 */
397 /* FIXME MSP430F - u41 - not detected */
402 clock-frequency = <400000>;
403 /* FIXME PL i2c via PCA9306 - u45 */
404 /* FIXME MSP430 - u41 - not detected */
405 i2cswitch@74 { /* u34 */
406 compatible = "nxp,pca9548";
407 #address-cells = <1>;
410 i2c@0 { /* i2c mw 74 0 1 */
411 #address-cells = <1>;
415 * IIC_EEPROM 1kB memory which uses 256B blocks
416 * where every block has different address.
417 * 0 - 256B address 0x54
418 * 256B - 512B address 0x55
419 * 512B - 768B address 0x56
420 * 768B - 1024B address 0x57
422 eeprom@54 { /* u23 */
423 compatible = "at,24c08";
427 i2c@1 { /* i2c mw 74 0 2 */
428 #address-cells = <1>;
431 si5341: clock-generator1@36 { /* SI5341 - u69 */
432 compatible = "si5341";
437 i2c@2 { /* i2c mw 74 0 4 */
438 #address-cells = <1>;
441 si570_1: clock-generator2@5d { /* USER SI570 - u42 */
443 compatible = "silabs,si570";
445 temperature-stability = <50>;
446 factory-fout = <300000000>;
447 clock-frequency = <300000000>;
450 i2c@3 { /* i2c mw 74 0 8 */
451 #address-cells = <1>;
454 si570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */
456 compatible = "silabs,si570";
458 temperature-stability = <50>; /* copy from zc702 */
459 factory-fout = <156250000>;
460 clock-frequency = <148500000>;
463 i2c@4 { /* i2c mw 74 0 10 */
464 #address-cells = <1>;
467 si5328: clock-generator4@69 {/* SI5328 - u20 */
468 compatible = "silabs,si5328";
472 /* 5 - 7 unconnected */
476 compatible = "nxp,pca9548"; /* u135 */
477 #address-cells = <1>;
482 #address-cells = <1>;
488 #address-cells = <1>;
494 #address-cells = <1>;
499 i2c@3 { /* i2c mw 75 0 8 */
500 #address-cells = <1>;
504 dev@19 { /* u-boot detection */
508 dev@30 { /* u-boot detection */
512 dev@35 { /* u-boot detection */
516 dev@36 { /* u-boot detection */
520 dev@51 { /* u-boot detection - maybe SPD */
526 #address-cells = <1>;
532 #address-cells = <1>;
538 #address-cells = <1>;
544 #address-cells = <1>;
560 compatible = "m25p80"; /* 32MB */
561 #address-cells = <1>;
564 spi-tx-bus-width = <1>;
565 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
566 spi-max-frequency = <108000000>; /* Based on DC1 spec */
567 partition@qspi-fsbl-uboot { /* for testing purpose */
568 label = "qspi-fsbl-uboot";
569 reg = <0x0 0x100000>;
571 partition@qspi-linux { /* for testing purpose */
572 label = "qspi-linux";
573 reg = <0x100000 0x500000>;
575 partition@qspi-device-tree { /* for testing purpose */
576 label = "qspi-device-tree";
577 reg = <0x600000 0x20000>;
579 partition@qspi-rootfs { /* for testing purpose */
580 label = "qspi-rootfs";
581 reg = <0x620000 0x5E0000>;
592 /* SATA OOB timing settings */
593 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
594 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
595 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
596 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
597 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
598 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
599 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
600 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
603 /* SD1 with level shifter */
606 no-1-8-v; /* for 1.0 silicon */
618 /* ULPI SMSC USB3320 */
654 &xlnx_dp_snd_codec0 {