arch/arm/dts/zynqmp-zcu102-revA.dts

   1 /*
   2  * dts file for Xilinx ZynqMP ZCU102 RevA
   3  *
   4  * (C) Copyright 2015, Xilinx, Inc.
   5  *
   6  * Michal Simek <michal.simek@xilinx.com>
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 /dts-v1/;
  12
  13 #include "zynqmp.dtsi"
  14 #include "zynqmp-clk.dtsi"
  15 #include <dt-bindings/gpio/gpio.h>
  16
  17 / {
  18         model = "ZynqMP ZCU102 RevA";
  19         compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
  20
  21         aliases {
  22                 ethernet0 = &gem3;
  23                 gpio0 = &gpio;
  24                 i2c0 = &i2c0;
  25                 i2c1 = &i2c1;
  26                 mmc0 = &sdhci1;
  27                 rtc0 = &rtc;
  28                 serial0 = &uart0;
  29                 serial1 = &uart1;
  30                 serial2 = &dcc;
  31                 spi0 = &qspi;
  32                 usb0 = &usb0;
  33         };
  34
  35         chosen {
  36                 bootargs = "earlycon";
  37                 stdout-path = "serial0:115200n8";
  38         };
  39
  40         memory@0 {
  41                 device_type = "memory";
  42                 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
  43         };
  44
  45         gpio-keys {
  46                 compatible = "gpio-keys";
  47                 #address-cells = <1>;
  48                 #size-cells = <0>;
  49                 autorepeat;
  50                 sw19 {
  51                         label = "sw19";
  52                         gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
  53                         linux,code = <108>; /* down */
  54                         gpio-key,wakeup;
  55                         autorepeat;
  56                 };
  57         };
  58
  59         leds {
  60                 compatible = "gpio-leds";
  61                 heartbeat_led {
  62                         label = "heartbeat";
  63                         gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
  64                         linux,default-trigger = "heartbeat";
  65                 };
  66         };
  67 };
  68
  69 &can1 {
  70         status = "okay";
  71 };
  72
  73 &dcc {
  74         status = "okay";
  75 };
  76
  77 /* fpd_dma clk 667MHz, lpd_dma 500MHz */
  78 &fpd_dma_chan1 {
  79         status = "okay";
  80         xlnx,include-sg; /* for testing purpose */
  81         xlnx,overfetch; /* for testing purpose */
  82         xlnx,ratectrl = <0>; /* for testing purpose */
  83         xlnx,src-issue = <31>;
  84 };
  85
  86 &fpd_dma_chan2 {
  87         status = "okay";
  88         xlnx,ratectrl = <100>; /* for testing purpose */
  89         xlnx,src-issue = <4>; /* for testing purpose */
  90 };
  91
  92 &fpd_dma_chan3 {
  93         status = "okay";
  94 };
  95
  96 &fpd_dma_chan4 {
  97         status = "okay";
  98         xlnx,include-sg; /* for testing purpose */
  99 };
 100
 101 &fpd_dma_chan5 {
 102         status = "okay";
 103 };
 104
 105 &fpd_dma_chan6 {
 106         status = "okay";
 107         xlnx,include-sg; /* for testing purpose */
 108 };
 109
 110 &fpd_dma_chan7 {
 111         status = "okay";
 112 };
 113
 114 &fpd_dma_chan8 {
 115         status = "okay";
 116         xlnx,include-sg; /* for testing purpose */
 117 };
 118
 119 &gem3 {
 120         status = "okay";
 121         phy-handle = <&phy0>;
 122         phy-mode = "rgmii-id";
 123         phy0: phy@21 {
 124                 reg = <21>;
 125                 ti,rx-internal-delay = <0x8>;
 126                 ti,tx-internal-delay = <0xa>;
 127                 ti,fifo-depth = <0x1>;
 128         };
 129 };
 130
 131 &gpio {
 132         status = "okay";
 133 };
 134
 135 &gpu {
 136         status = "okay";
 137 };
 138
 139 &i2c0 {
 140         status = "okay";
 141         clock-frequency = <400000>;
 142
 143         tca6416_u97: gpio@20 {
 144                 /*
 145                  * Enable all GTs to out from U-Boot
 146                  * i2c mw 20 6 0  - setup IO to output
 147                  * i2c mw 20 2 ef - setup output values on pins 0-7
 148                  * i2c mw 20 3 ff - setup output values on pins 10-17
 149                  */
 150                 compatible = "ti,tca6416";
 151                 reg = <0x20>;
 152                 gpio-controller;
 153                 #gpio-cells = <2>;
 154                 /*
 155                  * IRQ not connected
 156                  * Lines:
 157                  * 0 - PS_GTR_LAN_SEL0
 158                  * 1 - PS_GTR_LAN_SEL1
 159                  * 2 - PS_GTR_LAN_SEL2
 160                  * 3 - PS_GTR_LAN_SEL3
 161                  * 4 - PCI_CLK_DIR_SEL
 162                  * 5 - IIC_MUX_RESET_B
 163                  * 6 - GEM3_EXP_RESET_B
 164                  * 7, 10 - 17 - not connected
 165                  */
 166
 167                 gtr_sel0 {
 168                         gpio-hog;
 169                         gpios = <0 0>;
 170                         output-low; /* PCIE = 0, DP = 1 */
 171                         line-name = "sel0";
 172                 };
 173                 gtr_sel1 {
 174                         gpio-hog;
 175                         gpios = <1 0>;
 176                         output-high; /* PCIE = 0, DP = 1 */
 177                         line-name = "sel1";
 178                 };
 179                 gtr_sel2 {
 180                         gpio-hog;
 181                         gpios = <2 0>;
 182                         output-high; /* PCIE = 0, USB0 = 1 */
 183                         line-name = "sel2";
 184                 };
 185                 gtr_sel3 {
 186                         gpio-hog;
 187                         gpios = <3 0>;
 188                         output-high; /* PCIE = 0, SATA = 1 */
 189                         line-name = "sel3";
 190                 };
 191         };
 192
 193         tca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */
 194                 compatible = "ti,tca6416";
 195                 reg = <0x21>;
 196                 gpio-controller;
 197                 #gpio-cells = <2>;
 198                 /*
 199                  * IRQ not connected
 200                  * Lines:
 201                  * 0 - VCCPSPLL_EN
 202                  * 1 - MGTRAVCC_EN
 203                  * 2 - MGTRAVTT_EN
 204                  * 3 - VCCPSDDRPLL_EN
 205                  * 4 - MIO26_PMU_INPUT_LS
 206                  * 5 - PL_PMBUS_ALERT
 207                  * 6 - PS_PMBUS_ALERT
 208                  * 7 - MAXIM_PMBUS_ALERT
 209                  * 10 - PL_DDR4_VTERM_EN
 210                  * 11 - PL_DDR4_VPP_2V5_EN
 211                  * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON
 212                  * 13 - PS_DIMM_SUSPEND_EN
 213                  * 14 - PS_DDR4_VTERM_EN
 214                  * 15 - PS_DDR4_VPP_2V5_EN
 215                  * 16 - 17 - not connected
 216                  */
 217         };
 218
 219         i2cswitch@75 { /* u60 */
 220                 compatible = "nxp,pca9544";
 221                 #address-cells = <1>;
 222                 #size-cells = <0>;
 223                 reg = <0x75>;
 224                 i2c@0 { /* i2c mw 75 0 1 */
 225                         #address-cells = <1>;
 226                         #size-cells = <0>;
 227                         reg = <0>;
 228                         /* PS_PMBUS */
 229                         ina226@40 { /* u76 */
 230                                 compatible = "ti,ina226";
 231                                 reg = <0x40>;
 232                                 shunt-resistor = <5000>;
 233                         };
 234                         ina226@41 { /* u77 */
 235                                 compatible = "ti,ina226";
 236                                 reg = <0x41>;
 237                                 shunt-resistor = <5000>;
 238                         };
 239                         ina226@42 { /* u78 */
 240                                 compatible = "ti,ina226";
 241                                 reg = <0x42>;
 242                                 shunt-resistor = <5000>;
 243                         };
 244                         ina226@43 { /* u87 */
 245                                 compatible = "ti,ina226";
 246                                 reg = <0x43>;
 247                                 shunt-resistor = <5000>;
 248                         };
 249                         ina226@44 { /* u85 */
 250                                 compatible = "ti,ina226";
 251                                 reg = <0x44>;
 252                                 shunt-resistor = <5000>;
 253                         };
 254                         ina226@45 { /* u86 */
 255                                 compatible = "ti,ina226";
 256                                 reg = <0x45>;
 257                                 shunt-resistor = <5000>;
 258                         };
 259                         ina226@46 { /* u93 */
 260                                 compatible = "ti,ina226";
 261                                 reg = <0x46>;
 262                                 shunt-resistor = <5000>;
 263                         };
 264                         ina226@47 { /* u88 */
 265                                 compatible = "ti,ina226";
 266                                 reg = <0x47>;
 267                                 shunt-resistor = <5000>;
 268                         };
 269                         ina226@4a { /* u15 */
 270                                 compatible = "ti,ina226";
 271                                 reg = <0x4a>;
 272                                 shunt-resistor = <5000>;
 273                         };
 274                         ina226@4b { /* u92 */
 275                                 compatible = "ti,ina226";
 276                                 reg = <0x4b>;
 277                                 shunt-resistor = <5000>;
 278                         };
 279                 };
 280                 i2c@1 { /* i2c mw 75 0 1 */
 281                         #address-cells = <1>;
 282                         #size-cells = <0>;
 283                         reg = <1>;
 284                         /* PL_PMBUS */
 285                         ina226@40 { /* u79 */
 286                                 compatible = "ti,ina226";
 287                                 reg = <0x40>;
 288                                 shunt-resistor = <2000>;
 289                         };
 290                         ina226@41 { /* u81 */
 291                                 compatible = "ti,ina226";
 292                                 reg = <0x41>;
 293                                 shunt-resistor = <5000>;
 294                         };
 295                         ina226@42 { /* u80 */
 296                                 compatible = "ti,ina226";
 297                                 reg = <0x42>;
 298                                 shunt-resistor = <5000>;
 299                         };
 300                         ina226@43 { /* u84 */
 301                                 compatible = "ti,ina226";
 302                                 reg = <0x43>;
 303                                 shunt-resistor = <5000>;
 304                         };
 305                         ina226@44 { /* u16 */
 306                                 compatible = "ti,ina226";
 307                                 reg = <0x44>;
 308                                 shunt-resistor = <5000>;
 309                         };
 310                         ina226@45 { /* u65 */
 311                                 compatible = "ti,ina226";
 312                                 reg = <0x45>;
 313                                 shunt-resistor = <5000>;
 314                         };
 315                         ina226@46 { /* u74 */
 316                                 compatible = "ti,ina226";
 317                                 reg = <0x46>;
 318                                 shunt-resistor = <5000>;
 319                         };
 320                         ina226@47 { /* u75 */
 321                                 compatible = "ti,ina226";
 322                                 reg = <0x47>;
 323                                 shunt-resistor = <5000>;
 324                         };
 325                 };
 326                 i2c@2 { /* i2c mw 75 0 1 */
 327                         #address-cells = <1>;
 328                         #size-cells = <0>;
 329                         reg = <2>;
 330                         /* MAXIM_PMBUS - 00 */
 331                         max15301@a { /* u46 */
 332                                 compatible = "max15301";
 333                                 reg = <0xa>;
 334                         };
 335                         max15303@b { /* u4 */
 336                                 compatible = "max15303";
 337                                 reg = <0xb>;
 338                         };
 339                         max15303@10 { /* u13 */
 340                                 compatible = "max15303";
 341                                 reg = <0x10>;
 342                         };
 343                         max15301@13 { /* u47 */
 344                                 compatible = "max15301";
 345                                 reg = <0x13>;
 346                         };
 347                         max15303@14 { /* u7 */
 348                                 compatible = "max15303";
 349                                 reg = <0x14>;
 350                         };
 351                         max15303@15 { /* u6 */
 352                                 compatible = "max15303";
 353                                 reg = <0x15>;
 354                         };
 355                         max15303@16 { /* u10 */
 356                                 compatible = "max15303";
 357                                 reg = <0x16>;
 358                         };
 359                         max15303@17 { /* u9 */
 360                                 compatible = "max15303";
 361                                 reg = <0x17>;
 362                         };
 363                         max15301@18 { /* u63 */
 364                                 compatible = "max15301";
 365                                 reg = <0x18>;
 366                         };
 367                         max15303@1a { /* u49 */
 368                                 compatible = "max15303";
 369                                 reg = <0x1a>;
 370                         };
 371                         max15303@1d { /* u18 */
 372                                 compatible = "max15303";
 373                                 reg = <0x1d>;
 374                         };
 375                         max15303@20 { /* u8 */
 376                                 compatible = "max15303";
 377                                 status = "disabled"; /* unreachable */
 378                                 reg = <0x20>;
 379                         };
 380
 381 /*                      drivers/hwmon/pmbus/Kconfig:86:   be called max20751.
 382 drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751)  += max20751.o
 383 */
 384                         max20751@72 { /* u95 FIXME - not detected */
 385                                 compatible = "max20751";
 386                                 reg = <0x72>;
 387                         };
 388                         max20751@73 { /* u96 FIXME - not detected */
 389                                 compatible = "max20751";
 390                                 reg = <0x73>;
 391                         };
 392                 };
 393                 /* Bus 3 is not connected */
 394         };
 395
 396         /* FIXME PMOD - j160 */
 397         /* FIXME MSP430F - u41 - not detected */
 398 };
 399
 400 &i2c1 {
 401         status = "okay";
 402         clock-frequency = <400000>;
 403         /* FIXME PL i2c via PCA9306 - u45 */
 404         /* FIXME MSP430 - u41 - not detected */
 405         i2cswitch@74 { /* u34 */
 406                 compatible = "nxp,pca9548";
 407                 #address-cells = <1>;
 408                 #size-cells = <0>;
 409                 reg = <0x74>;
 410                 i2c@0 { /* i2c mw 74 0 1 */
 411                         #address-cells = <1>;
 412                         #size-cells = <0>;
 413                         reg = <0>;
 414                         /*
 415                          * IIC_EEPROM 1kB memory which uses 256B blocks
 416                          * where every block has different address.
 417                          *    0 - 256B address 0x54
 418                          * 256B - 512B address 0x55
 419                          * 512B - 768B address 0x56
 420                          * 768B - 1024B address 0x57
 421                          */
 422                         eeprom@54 { /* u23 */
 423                                 compatible = "at,24c08";
 424                                 reg = <0x54>;
 425                         };
 426                 };
 427                 i2c@1 { /* i2c mw 74 0 2 */
 428                         #address-cells = <1>;
 429                         #size-cells = <0>;
 430                         reg = <1>;
 431                         si5341: clock-generator1@36 { /* SI5341 - u69 */
 432                                 compatible = "si5341";
 433                                 reg = <0x36>;
 434                         };
 435
 436                 };
 437                 i2c@2 { /* i2c mw 74 0 4 */
 438                         #address-cells = <1>;
 439                         #size-cells = <0>;
 440                         reg = <2>;
 441                         si570_1: clock-generator2@5d { /* USER SI570 - u42 */
 442                                 #clock-cells = <0>;
 443                                 compatible = "silabs,si570";
 444                                 reg = <0x5d>;
 445                                 temperature-stability = <50>;
 446                                 factory-fout = <300000000>;
 447                                 clock-frequency = <300000000>;
 448                         };
 449                 };
 450                 i2c@3 { /* i2c mw 74 0 8 */
 451                         #address-cells = <1>;
 452                         #size-cells = <0>;
 453                         reg = <3>;
 454                         si570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */
 455                                 #clock-cells = <0>;
 456                                 compatible = "silabs,si570";
 457                                 reg = <0x5d>;
 458                                 temperature-stability = <50>; /* copy from zc702 */
 459                                 factory-fout = <156250000>;
 460                                 clock-frequency = <148500000>;
 461                         };
 462                 };
 463                 i2c@4 { /* i2c mw 74 0 10 */
 464                         #address-cells = <1>;
 465                         #size-cells = <0>;
 466                         reg = <4>;
 467                         si5328: clock-generator4@69 {/* SI5328 - u20 */
 468                                 compatible = "silabs,si5328";
 469                                 reg = <0x69>;
 470                         };
 471                 };
 472                 /* 5 - 7 unconnected */
 473         };
 474
 475         i2cswitch@75 {
 476                 compatible = "nxp,pca9548"; /* u135 */
 477                 #address-cells = <1>;
 478                 #size-cells = <0>;
 479                 reg = <0x75>;
 480
 481                 i2c@0 {
 482                         #address-cells = <1>;
 483                         #size-cells = <0>;
 484                         reg = <0>;
 485                         /* HPC0_IIC */
 486                 };
 487                 i2c@1 {
 488                         #address-cells = <1>;
 489                         #size-cells = <0>;
 490                         reg = <1>;
 491                         /* HPC1_IIC */
 492                 };
 493                 i2c@2 {
 494                         #address-cells = <1>;
 495                         #size-cells = <0>;
 496                         reg = <2>;
 497                         /* SYSMON */
 498                 };
 499                 i2c@3 { /* i2c mw 75 0 8 */
 500                         #address-cells = <1>;
 501                         #size-cells = <0>;
 502                         reg = <3>;
 503                         /* DDR4 SODIMM */
 504                         dev@19 { /* u-boot detection */
 505                                 compatible = "xxx";
 506                                 reg = <0x19>;
 507                         };
 508                         dev@30 { /* u-boot detection */
 509                                 compatible = "xxx";
 510                                 reg = <0x30>;
 511                         };
 512                         dev@35 { /* u-boot detection */
 513                                 compatible = "xxx";
 514                                 reg = <0x35>;
 515                         };
 516                         dev@36 { /* u-boot detection */
 517                                 compatible = "xxx";
 518                                 reg = <0x36>;
 519                         };
 520                         dev@51 { /* u-boot detection - maybe SPD */
 521                                 compatible = "xxx";
 522                                 reg = <0x51>;
 523                         };
 524                 };
 525                 i2c@4 {
 526                         #address-cells = <1>;
 527                         #size-cells = <0>;
 528                         reg = <4>;
 529                         /* SEP 3 */
 530                 };
 531                 i2c@5 {
 532                         #address-cells = <1>;
 533                         #size-cells = <0>;
 534                         reg = <5>;
 535                         /* SEP 2 */
 536                 };
 537                 i2c@6 {
 538                         #address-cells = <1>;
 539                         #size-cells = <0>;
 540                         reg = <6>;
 541                         /* SEP 1 */
 542                 };
 543                 i2c@7 {
 544                         #address-cells = <1>;
 545                         #size-cells = <0>;
 546                         reg = <7>;
 547                         /* SEP 0 */
 548                 };
 549         };
 550 };
 551
 552 &pcie {
 553         status = "okay";
 554 };
 555
 556 &qspi {
 557         status = "okay";
 558         is-dual = <1>;
 559         flash@0 {
 560                 compatible = "m25p80"; /* 32MB */
 561                 #address-cells = <1>;
 562                 #size-cells = <1>;
 563                 reg = <0x0>;
 564                 spi-tx-bus-width = <1>;
 565                 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
 566                 spi-max-frequency = <108000000>; /* Based on DC1 spec */
 567                 partition@qspi-fsbl-uboot { /* for testing purpose */
 568                         label = "qspi-fsbl-uboot";
 569                         reg = <0x0 0x100000>;
 570                 };
 571                 partition@qspi-linux { /* for testing purpose */
 572                         label = "qspi-linux";
 573                         reg = <0x100000 0x500000>;
 574                 };
 575                 partition@qspi-device-tree { /* for testing purpose */
 576                         label = "qspi-device-tree";
 577                         reg = <0x600000 0x20000>;
 578                 };
 579                 partition@qspi-rootfs { /* for testing purpose */
 580                         label = "qspi-rootfs";
 581                         reg = <0x620000 0x5E0000>;
 582                 };
 583         };
 584 };
 585
 586 &rtc {
 587         status = "okay";
 588 };
 589
 590 &sata {
 591         status = "okay";
 592         /* SATA OOB timing settings */
 593         ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
 594         ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
 595         ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 596         ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 597         ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
 598         ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
 599         ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 600         ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 601 };
 602
 603 /* SD1 with level shifter */
 604 &sdhci1 {
 605         status = "okay";
 606         no-1-8-v;       /* for 1.0 silicon */
 607         xlnx,mio_bank = <1>;
 608 };
 609
 610 &uart0 {
 611         status = "okay";
 612 };
 613
 614 &uart1 {
 615         status = "okay";
 616 };
 617
 618 /* ULPI SMSC USB3320 */
 619 &usb0 {
 620         status = "okay";
 621 };
 622
 623 &dwc3_0 {
 624         status = "okay";
 625         dr_mode = "host";
 626 };
 627
 628 &xilinx_drm {
 629         status = "okay";
 630         clocks = <&si570_1>;
 631 };
 632
 633 &xlnx_dp {
 634         status = "okay";
 635 };
 636
 637 &xlnx_dp_sub {
 638         status = "okay";
 639         xlnx,vid-clk-pl;
 640 };
 641
 642 &xlnx_dp_snd_pcm0 {
 643         status = "okay";
 644 };
 645
 646 &xlnx_dp_snd_pcm1 {
 647         status = "okay";
 648 };
 649
 650 &xlnx_dp_snd_card {
 651         status = "okay";
 652 };
 653
 654 &xlnx_dp_snd_codec0 {
 655         status = "okay";
 656 };
 657
 658 &xlnx_dpdma {
 659         status = "okay";
 660 };