1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP ZCU102 RevA
5 * (C) Copyright 2015 - 2018, Xilinx, Inc.
7 * Michal Simek <michal.simek@xilinx.com>
12 #include "zynqmp.dtsi"
13 #include "zynqmp-clk-ccf.dtsi"
14 #include <dt-bindings/input/input.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/phy/phy.h>
19 model = "ZynqMP ZCU102 RevA";
20 compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
37 bootargs = "earlycon";
38 stdout-path = "serial0:115200n8";
42 device_type = "memory";
43 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
47 compatible = "gpio-keys";
53 gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
54 linux,code = <KEY_DOWN>;
61 compatible = "gpio-leds";
64 gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
65 linux,default-trigger = "heartbeat";
112 phy-handle = <&phy0>;
113 phy-mode = "rgmii-id";
116 ti,rx-internal-delay = <0x8>;
117 ti,tx-internal-delay = <0xa>;
118 ti,fifo-depth = <0x1>;
132 clock-frequency = <400000>;
134 tca6416_u97: gpio@20 {
135 compatible = "ti,tca6416";
142 * 0 - PS_GTR_LAN_SEL0
143 * 1 - PS_GTR_LAN_SEL1
144 * 2 - PS_GTR_LAN_SEL2
145 * 3 - PS_GTR_LAN_SEL3
146 * 4 - PCI_CLK_DIR_SEL
147 * 5 - IIC_MUX_RESET_B
148 * 6 - GEM3_EXP_RESET_B
149 * 7, 10 - 17 - not connected
155 output-low; /* PCIE = 0, DP = 1 */
161 output-high; /* PCIE = 0, DP = 1 */
167 output-high; /* PCIE = 0, USB0 = 1 */
173 output-high; /* PCIE = 0, SATA = 1 */
178 tca6416_u61: gpio@21 {
179 compatible = "ti,tca6416";
190 * 4 - MIO26_PMU_INPUT_LS
193 * 7 - MAXIM_PMBUS_ALERT
194 * 10 - PL_DDR4_VTERM_EN
195 * 11 - PL_DDR4_VPP_2V5_EN
196 * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON
197 * 13 - PS_DIMM_SUSPEND_EN
198 * 14 - PS_DDR4_VTERM_EN
199 * 15 - PS_DDR4_VPP_2V5_EN
200 * 16 - 17 - not connected
204 i2c-mux@75 { /* u60 */
205 compatible = "nxp,pca9544";
206 #address-cells = <1>;
210 #address-cells = <1>;
214 ina226@40 { /* u76 */
215 compatible = "ti,ina226";
217 shunt-resistor = <5000>;
219 ina226@41 { /* u77 */
220 compatible = "ti,ina226";
222 shunt-resistor = <5000>;
224 ina226@42 { /* u78 */
225 compatible = "ti,ina226";
227 shunt-resistor = <5000>;
229 ina226@43 { /* u87 */
230 compatible = "ti,ina226";
232 shunt-resistor = <5000>;
234 ina226@44 { /* u85 */
235 compatible = "ti,ina226";
237 shunt-resistor = <5000>;
239 ina226@45 { /* u86 */
240 compatible = "ti,ina226";
242 shunt-resistor = <5000>;
244 ina226@46 { /* u93 */
245 compatible = "ti,ina226";
247 shunt-resistor = <5000>;
249 ina226@47 { /* u88 */
250 compatible = "ti,ina226";
252 shunt-resistor = <5000>;
254 ina226@4a { /* u15 */
255 compatible = "ti,ina226";
257 shunt-resistor = <5000>;
259 ina226@4b { /* u92 */
260 compatible = "ti,ina226";
262 shunt-resistor = <5000>;
266 #address-cells = <1>;
270 ina226@40 { /* u79 */
271 compatible = "ti,ina226";
273 shunt-resistor = <2000>;
275 ina226@41 { /* u81 */
276 compatible = "ti,ina226";
278 shunt-resistor = <5000>;
280 ina226@42 { /* u80 */
281 compatible = "ti,ina226";
283 shunt-resistor = <5000>;
285 ina226@43 { /* u84 */
286 compatible = "ti,ina226";
288 shunt-resistor = <5000>;
290 ina226@44 { /* u16 */
291 compatible = "ti,ina226";
293 shunt-resistor = <5000>;
295 ina226@45 { /* u65 */
296 compatible = "ti,ina226";
298 shunt-resistor = <5000>;
300 ina226@46 { /* u74 */
301 compatible = "ti,ina226";
303 shunt-resistor = <5000>;
305 ina226@47 { /* u75 */
306 compatible = "ti,ina226";
308 shunt-resistor = <5000>;
312 #address-cells = <1>;
315 /* MAXIM_PMBUS - 00 */
316 max15301@a { /* u46 */
317 compatible = "maxim,max15301";
320 max15303@b { /* u4 */
321 compatible = "maxim,max15303";
324 max15303@10 { /* u13 */
325 compatible = "maxim,max15303";
328 max15301@13 { /* u47 */
329 compatible = "maxim,max15301";
332 max15303@14 { /* u7 */
333 compatible = "maxim,max15303";
336 max15303@15 { /* u6 */
337 compatible = "maxim,max15303";
340 max15303@16 { /* u10 */
341 compatible = "maxim,max15303";
344 max15303@17 { /* u9 */
345 compatible = "maxim,max15303";
348 max15301@18 { /* u63 */
349 compatible = "maxim,max15301";
352 max15303@1a { /* u49 */
353 compatible = "maxim,max15303";
356 max15303@1d { /* u18 */
357 compatible = "maxim,max15303";
360 max15303@20 { /* u8 */
361 compatible = "maxim,max15303";
362 status = "disabled"; /* unreachable */
366 max20751@72 { /* u95 */
367 compatible = "maxim,max20751";
370 max20751@73 { /* u96 */
371 compatible = "maxim,max20751";
375 /* Bus 3 is not connected */
381 clock-frequency = <400000>;
383 /* PL i2c via PCA9306 - u45 */
384 i2c-mux@74 { /* u34 */
385 compatible = "nxp,pca9548";
386 #address-cells = <1>;
390 #address-cells = <1>;
394 * IIC_EEPROM 1kB memory which uses 256B blocks
395 * where every block has different address.
396 * 0 - 256B address 0x54
397 * 256B - 512B address 0x55
398 * 512B - 768B address 0x56
399 * 768B - 1024B address 0x57
401 eeprom: eeprom@54 { /* u23 */
402 compatible = "atmel,24c08";
407 #address-cells = <1>;
410 si5341: clock-generator@36 { /* SI5341 - u69 */
411 compatible = "silabs,si5341";
417 #address-cells = <1>;
420 si570_1: clock-generator@5d { /* USER SI570 - u42 */
422 compatible = "silabs,si570";
424 temperature-stability = <50>;
425 factory-fout = <300000000>;
426 clock-frequency = <300000000>;
430 #address-cells = <1>;
433 si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */
435 compatible = "silabs,si570";
437 temperature-stability = <50>; /* copy from zc702 */
438 factory-fout = <156250000>;
439 clock-frequency = <148500000>;
443 #address-cells = <1>;
446 si5328: clock-generator@69 {/* SI5328 - u20 */
447 compatible = "silabs,si5328";
450 * Chip has interrupt present connected to PL
451 * interrupt-parent = <&>;
456 /* 5 - 7 unconnected */
460 compatible = "nxp,pca9548"; /* u135 */
461 #address-cells = <1>;
466 #address-cells = <1>;
472 #address-cells = <1>;
478 #address-cells = <1>;
484 #address-cells = <1>;
505 #address-cells = <1>;
511 #address-cells = <1>;
517 #address-cells = <1>;
523 #address-cells = <1>;
539 compatible = "m25p80"; /* 32MB */
540 #address-cells = <1>;
543 spi-tx-bus-width = <1>;
544 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
545 spi-max-frequency = <108000000>; /* Based on DC1 spec */
546 partition@qspi-fsbl-uboot { /* for testing purpose */
547 label = "qspi-fsbl-uboot";
548 reg = <0x0 0x100000>;
550 partition@qspi-linux { /* for testing purpose */
551 label = "qspi-linux";
552 reg = <0x100000 0x500000>;
554 partition@qspi-device-tree { /* for testing purpose */
555 label = "qspi-device-tree";
556 reg = <0x600000 0x20000>;
558 partition@qspi-rootfs { /* for testing purpose */
559 label = "qspi-rootfs";
560 reg = <0x620000 0x5E0000>;
571 /* SATA OOB timing settings */
572 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
573 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
574 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
575 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
576 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
577 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
578 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
579 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
580 phy-names = "sata-phy";
581 phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;
584 /* SD1 with level shifter */
587 no-1-8-v; /* for 1.0 silicon */
603 /* ULPI SMSC USB3320 */
611 snps,usb3_lpm_capable;
612 phy-names = "usb3-phy";
613 phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
614 maximum-speed = "super-speed";
659 &xlnx_dp_snd_codec0 {