arch/arm/dts/zynqmp-zcu102-revA.dts

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * dts file for Xilinx ZynqMP ZCU102 RevA
   4  *
   5  * (C) Copyright 2015 - 2020, Xilinx, Inc.
   6  *
   7  * Michal Simek <michal.simek@xilinx.com>
   8  */
   9
  10 /dts-v1/;
  11
  12 #include "zynqmp.dtsi"
  13 #include "zynqmp-clk-ccf.dtsi"
  14 #include <dt-bindings/input/input.h>
  15 #include <dt-bindings/gpio/gpio.h>
  16 #include <dt-bindings/phy/phy.h>
  17
  18 / {
  19         model = "ZynqMP ZCU102 RevA";
  20         compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
  21
  22         aliases {
  23                 ethernet0 = &gem3;
  24                 gpio0 = &gpio;
  25                 i2c0 = &i2c0;
  26                 i2c1 = &i2c1;
  27                 mmc0 = &sdhci1;
  28                 rtc0 = &rtc;
  29                 serial0 = &uart0;
  30                 serial1 = &uart1;
  31                 serial2 = &dcc;
  32                 spi0 = &qspi;
  33                 usb0 = &usb0;
  34         };
  35
  36         chosen {
  37                 bootargs = "earlycon";
  38                 stdout-path = "serial0:115200n8";
  39                 xlnx,eeprom = &eeprom;
  40         };
  41
  42         memory@0 {
  43                 device_type = "memory";
  44                 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
  45         };
  46
  47         gpio-keys {
  48                 compatible = "gpio-keys";
  49                 autorepeat;
  50                 sw19 {
  51                         label = "sw19";
  52                         gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
  53                         linux,code = <KEY_DOWN>;
  54                         wakeup-source;
  55                         autorepeat;
  56                 };
  57         };
  58
  59         leds {
  60                 compatible = "gpio-leds";
  61                 heartbeat-led {
  62                         label = "heartbeat";
  63                         gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
  64                         linux,default-trigger = "heartbeat";
  65                 };
  66         };
  67
  68         ina226-u76 {
  69                 compatible = "iio-hwmon";
  70                 io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;
  71         };
  72         ina226-u77 {
  73                 compatible = "iio-hwmon";
  74                 io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;
  75         };
  76         ina226-u78 {
  77                 compatible = "iio-hwmon";
  78                 io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;
  79         };
  80         ina226-u87 {
  81                 compatible = "iio-hwmon";
  82                 io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;
  83         };
  84         ina226-u85 {
  85                 compatible = "iio-hwmon";
  86                 io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;
  87         };
  88         ina226-u86 {
  89                 compatible = "iio-hwmon";
  90                 io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;
  91         };
  92         ina226-u93 {
  93                 compatible = "iio-hwmon";
  94                 io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;
  95         };
  96         ina226-u88 {
  97                 compatible = "iio-hwmon";
  98                 io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;
  99         };
 100         ina226-u15 {
 101                 compatible = "iio-hwmon";
 102                 io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;
 103         };
 104         ina226-u92 {
 105                 compatible = "iio-hwmon";
 106                 io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;
 107         };
 108         ina226-u79 {
 109                 compatible = "iio-hwmon";
 110                 io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;
 111         };
 112         ina226-u81 {
 113                 compatible = "iio-hwmon";
 114                 io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;
 115         };
 116         ina226-u80 {
 117                 compatible = "iio-hwmon";
 118                 io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;
 119         };
 120         ina226-u84 {
 121                 compatible = "iio-hwmon";
 122                 io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;
 123         };
 124         ina226-u16 {
 125                 compatible = "iio-hwmon";
 126                 io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;
 127         };
 128         ina226-u65 {
 129                 compatible = "iio-hwmon";
 130                 io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;
 131         };
 132         ina226-u74 {
 133                 compatible = "iio-hwmon";
 134                 io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;
 135         };
 136         ina226-u75 {
 137                 compatible = "iio-hwmon";
 138                 io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;
 139         };
 140 };
 141
 142 &can1 {
 143         status = "okay";
 144 };
 145
 146 &dcc {
 147         status = "okay";
 148 };
 149
 150 &fpd_dma_chan1 {
 151         status = "okay";
 152 };
 153
 154 &fpd_dma_chan2 {
 155         status = "okay";
 156 };
 157
 158 &fpd_dma_chan3 {
 159         status = "okay";
 160 };
 161
 162 &fpd_dma_chan4 {
 163         status = "okay";
 164 };
 165
 166 &fpd_dma_chan5 {
 167         status = "okay";
 168 };
 169
 170 &fpd_dma_chan6 {
 171         status = "okay";
 172 };
 173
 174 &fpd_dma_chan7 {
 175         status = "okay";
 176 };
 177
 178 &fpd_dma_chan8 {
 179         status = "okay";
 180 };
 181
 182 &gem3 {
 183         status = "okay";
 184         phy-handle = <&phy0>;
 185         phy-mode = "rgmii-id";
 186         phy0: ethernet-phy@21 {
 187                 reg = <21>;
 188                 ti,rx-internal-delay = <0x8>;
 189                 ti,tx-internal-delay = <0xa>;
 190                 ti,fifo-depth = <0x1>;
 191                 ti,dp83867-rxctrl-strap-quirk;
 192                 /* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */
 193         };
 194 };
 195
 196 &gpio {
 197         status = "okay";
 198 };
 199
 200 &gpu {
 201         status = "okay";
 202 };
 203
 204 &i2c0 {
 205         status = "okay";
 206         clock-frequency = <400000>;
 207
 208         tca6416_u97: gpio@20 {
 209                 compatible = "ti,tca6416";
 210                 reg = <0x20>;
 211                 gpio-controller; /* IRQ not connected */
 212                 #gpio-cells = <2>;
 213                 gpio-line-names = "PS_GTR_LAN_SEL0", "PS_GTR_LAN_SEL1", "PS_GTR_LAN_SEL2", "PS_GTR_LAN_SEL3",
 214                                 "PCI_CLK_DIR_SEL", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B",
 215                                 "", "", "", "", "", "", "", "", "";
 216                 gtr-sel0 {
 217                         gpio-hog;
 218                         gpios = <0 0>;
 219                         output-low; /* PCIE = 0, DP = 1 */
 220                         line-name = "sel0";
 221                 };
 222                 gtr-sel1 {
 223                         gpio-hog;
 224                         gpios = <1 0>;
 225                         output-high; /* PCIE = 0, DP = 1 */
 226                         line-name = "sel1";
 227                 };
 228                 gtr-sel2 {
 229                         gpio-hog;
 230                         gpios = <2 0>;
 231                         output-high; /* PCIE = 0, USB0 = 1 */
 232                         line-name = "sel2";
 233                 };
 234                 gtr-sel3 {
 235                         gpio-hog;
 236                         gpios = <3 0>;
 237                         output-high; /* PCIE = 0, SATA = 1 */
 238                         line-name = "sel3";
 239                 };
 240         };
 241
 242         tca6416_u61: gpio@21 {
 243                 compatible = "ti,tca6416";
 244                 reg = <0x21>;
 245                 gpio-controller; /* IRQ not connected */
 246                 #gpio-cells = <2>;
 247                 gpio-line-names = "VCCPSPLL_EN", "MGTRAVCC_EN", "MGTRAVTT_EN", "VCCPSDDRPLL_EN", "MIO26_PMU_INPUT_LS",
 248                                 "PL_PMBUS_ALERT", "PS_PMBUS_ALERT", "MAXIM_PMBUS_ALERT", "PL_DDR4_VTERM_EN",
 249                                 "PL_DDR4_VPP_2V5_EN", "PS_DIMM_VDDQ_TO_PSVCCO_ON", "PS_DIMM_SUSPEND_EN",
 250                                 "PS_DDR4_VTERM_EN", "PS_DDR4_VPP_2V5_EN", "", "";
 251         };
 252
 253         i2c-mux@75 { /* u60 */
 254                 compatible = "nxp,pca9544";
 255                 #address-cells = <1>;
 256                 #size-cells = <0>;
 257                 reg = <0x75>;
 258                 i2c@0 {
 259                         #address-cells = <1>;
 260                         #size-cells = <0>;
 261                         reg = <0>;
 262                         /* PS_PMBUS */
 263                         u76: ina226@40 { /* u76 */
 264                                 compatible = "ti,ina226";
 265                                 #io-channel-cells = <1>;
 266                                 label = "ina226-u76";
 267                                 reg = <0x40>;
 268                                 shunt-resistor = <5000>;
 269                         };
 270                         u77: ina226@41 { /* u77 */
 271                                 compatible = "ti,ina226";
 272                                 #io-channel-cells = <1>;
 273                                 label = "ina226-u77";
 274                                 reg = <0x41>;
 275                                 shunt-resistor = <5000>;
 276                         };
 277                         u78: ina226@42 { /* u78 */
 278                                 compatible = "ti,ina226";
 279                                 #io-channel-cells = <1>;
 280                                 label = "ina226-u78";
 281                                 reg = <0x42>;
 282                                 shunt-resistor = <5000>;
 283                         };
 284                         u87: ina226@43 { /* u87 */
 285                                 compatible = "ti,ina226";
 286                                 #io-channel-cells = <1>;
 287                                 label = "ina226-u87";
 288                                 reg = <0x43>;
 289                                 shunt-resistor = <5000>;
 290                         };
 291                         u85: ina226@44 { /* u85 */
 292                                 compatible = "ti,ina226";
 293                                 #io-channel-cells = <1>;
 294                                 label = "ina226-u85";
 295                                 reg = <0x44>;
 296                                 shunt-resistor = <5000>;
 297                         };
 298                         u86: ina226@45 { /* u86 */
 299                                 compatible = "ti,ina226";
 300                                 #io-channel-cells = <1>;
 301                                 label = "ina226-u86";
 302                                 reg = <0x45>;
 303                                 shunt-resistor = <5000>;
 304                         };
 305                         u93: ina226@46 { /* u93 */
 306                                 compatible = "ti,ina226";
 307                                 #io-channel-cells = <1>;
 308                                 label = "ina226-u93";
 309                                 reg = <0x46>;
 310                                 shunt-resistor = <5000>;
 311                         };
 312                         u88: ina226@47 { /* u88 */
 313                                 compatible = "ti,ina226";
 314                                 #io-channel-cells = <1>;
 315                                 label = "ina226-u88";
 316                                 reg = <0x47>;
 317                                 shunt-resistor = <5000>;
 318                         };
 319                         u15: ina226@4a { /* u15 */
 320                                 compatible = "ti,ina226";
 321                                 #io-channel-cells = <1>;
 322                                 label = "ina226-u15";
 323                                 reg = <0x4a>;
 324                                 shunt-resistor = <5000>;
 325                         };
 326                         u92: ina226@4b { /* u92 */
 327                                 compatible = "ti,ina226";
 328                                 #io-channel-cells = <1>;
 329                                 label = "ina226-u92";
 330                                 reg = <0x4b>;
 331                                 shunt-resistor = <5000>;
 332                         };
 333                 };
 334                 i2c@1 {
 335                         #address-cells = <1>;
 336                         #size-cells = <0>;
 337                         reg = <1>;
 338                         /* PL_PMBUS */
 339                         u79: ina226@40 { /* u79 */
 340                                 compatible = "ti,ina226";
 341                                 #io-channel-cells = <1>;
 342                                 label = "ina226-u79";
 343                                 reg = <0x40>;
 344                                 shunt-resistor = <2000>;
 345                         };
 346                         u81: ina226@41 { /* u81 */
 347                                 compatible = "ti,ina226";
 348                                 #io-channel-cells = <1>;
 349                                 label = "ina226-u81";
 350                                 reg = <0x41>;
 351                                 shunt-resistor = <5000>;
 352                         };
 353                         u80: ina226@42 { /* u80 */
 354                                 compatible = "ti,ina226";
 355                                 #io-channel-cells = <1>;
 356                                 label = "ina226-u80";
 357                                 reg = <0x42>;
 358                                 shunt-resistor = <5000>;
 359                         };
 360                         u84: ina226@43 { /* u84 */
 361                                 compatible = "ti,ina226";
 362                                 #io-channel-cells = <1>;
 363                                 label = "ina226-u84";
 364                                 reg = <0x43>;
 365                                 shunt-resistor = <5000>;
 366                         };
 367                         u16: ina226@44 { /* u16 */
 368                                 compatible = "ti,ina226";
 369                                 #io-channel-cells = <1>;
 370                                 label = "ina226-u16";
 371                                 reg = <0x44>;
 372                                 shunt-resistor = <5000>;
 373                         };
 374                         u65: ina226@45 { /* u65 */
 375                                 compatible = "ti,ina226";
 376                                 #io-channel-cells = <1>;
 377                                 label = "ina226-u65";
 378                                 reg = <0x45>;
 379                                 shunt-resistor = <5000>;
 380                         };
 381                         u74: ina226@46 { /* u74 */
 382                                 compatible = "ti,ina226";
 383                                 #io-channel-cells = <1>;
 384                                 label = "ina226-u74";
 385                                 reg = <0x46>;
 386                                 shunt-resistor = <5000>;
 387                         };
 388                         u75: ina226@47 { /* u75 */
 389                                 compatible = "ti,ina226";
 390                                 #io-channel-cells = <1>;
 391                                 label = "ina226-u75";
 392                                 reg = <0x47>;
 393                                 shunt-resistor = <5000>;
 394                         };
 395                 };
 396                 i2c@2 {
 397                         #address-cells = <1>;
 398                         #size-cells = <0>;
 399                         reg = <2>;
 400                         /* MAXIM_PMBUS - 00 */
 401                         max15301@a { /* u46 */
 402                                 compatible = "maxim,max15301";
 403                                 reg = <0xa>;
 404                         };
 405                         max15303@b { /* u4 */
 406                                 compatible = "maxim,max15303";
 407                                 reg = <0xb>;
 408                         };
 409                         max15303@10 { /* u13 */
 410                                 compatible = "maxim,max15303";
 411                                 reg = <0x10>;
 412                         };
 413                         max15301@13 { /* u47 */
 414                                 compatible = "maxim,max15301";
 415                                 reg = <0x13>;
 416                         };
 417                         max15303@14 { /* u7 */
 418                                 compatible = "maxim,max15303";
 419                                 reg = <0x14>;
 420                         };
 421                         max15303@15 { /* u6 */
 422                                 compatible = "maxim,max15303";
 423                                 reg = <0x15>;
 424                         };
 425                         max15303@16 { /* u10 */
 426                                 compatible = "maxim,max15303";
 427                                 reg = <0x16>;
 428                         };
 429                         max15303@17 { /* u9 */
 430                                 compatible = "maxim,max15303";
 431                                 reg = <0x17>;
 432                         };
 433                         max15301@18 { /* u63 */
 434                                 compatible = "maxim,max15301";
 435                                 reg = <0x18>;
 436                         };
 437                         max15303@1a { /* u49 */
 438                                 compatible = "maxim,max15303";
 439                                 reg = <0x1a>;
 440                         };
 441                         max15303@1d { /* u18 */
 442                                 compatible = "maxim,max15303";
 443                                 reg = <0x1d>;
 444                         };
 445                         max15303@20 { /* u8 */
 446                                 compatible = "maxim,max15303";
 447                                 status = "disabled"; /* unreachable */
 448                                 reg = <0x20>;
 449                         };
 450                         max20751@72 { /* u95 */
 451                                 compatible = "maxim,max20751";
 452                                 reg = <0x72>;
 453                         };
 454                         max20751@73 { /* u96 */
 455                                 compatible = "maxim,max20751";
 456                                 reg = <0x73>;
 457                         };
 458                 };
 459                 /* Bus 3 is not connected */
 460         };
 461 };
 462
 463 &i2c1 {
 464         status = "okay";
 465         clock-frequency = <400000>;
 466
 467         /* PL i2c via PCA9306 - u45 */
 468         i2c-mux@74 { /* u34 */
 469                 compatible = "nxp,pca9548";
 470                 #address-cells = <1>;
 471                 #size-cells = <0>;
 472                 reg = <0x74>;
 473                 i2c@0 {
 474                         #address-cells = <1>;
 475                         #size-cells = <0>;
 476                         reg = <0>;
 477                         /*
 478                          * IIC_EEPROM 1kB memory which uses 256B blocks
 479                          * where every block has different address.
 480                          *    0 - 256B address 0x54
 481                          * 256B - 512B address 0x55
 482                          * 512B - 768B address 0x56
 483                          * 768B - 1024B address 0x57
 484                          */
 485                         eeprom: eeprom@54 { /* u23 */
 486                                 compatible = "atmel,24c08";
 487                                 reg = <0x54>;
 488                         };
 489                 };
 490                 i2c@1 {
 491                         #address-cells = <1>;
 492                         #size-cells = <0>;
 493                         reg = <1>;
 494                         si5341: clock-generator@36 { /* SI5341 - u69 */
 495                                 compatible = "silabs,si5341";
 496                                 reg = <0x36>;
 497                         };
 498
 499                 };
 500                 i2c@2 {
 501                         #address-cells = <1>;
 502                         #size-cells = <0>;
 503                         reg = <2>;
 504                         si570_1: clock-generator@5d { /* USER SI570 - u42 */
 505                                 #clock-cells = <0>;
 506                                 compatible = "silabs,si570";
 507                                 reg = <0x5d>;
 508                                 temperature-stability = <50>;
 509                                 factory-fout = <300000000>;
 510                                 clock-frequency = <300000000>;
 511                                 clock-output-names = "si570_user";
 512                         };
 513                 };
 514                 i2c@3 {
 515                         #address-cells = <1>;
 516                         #size-cells = <0>;
 517                         reg = <3>;
 518                         si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */
 519                                 #clock-cells = <0>;
 520                                 compatible = "silabs,si570";
 521                                 reg = <0x5d>;
 522                                 temperature-stability = <50>; /* copy from zc702 */
 523                                 factory-fout = <156250000>;
 524                                 clock-frequency = <148500000>;
 525                                 clock-output-names = "si570_mgt";
 526                         };
 527                 };
 528                 i2c@4 {
 529                         #address-cells = <1>;
 530                         #size-cells = <0>;
 531                         reg = <4>;
 532                         si5328: clock-generator@69 {/* SI5328 - u20 */
 533                                 compatible = "silabs,si5328";
 534                                 reg = <0x69>;
 535                                 /*
 536                                  * Chip has interrupt present connected to PL
 537                                  * interrupt-parent = <&>;
 538                                  * interrupts = <>;
 539                                  */
 540                         };
 541                 };
 542                 /* 5 - 7 unconnected */
 543         };
 544
 545         i2c-mux@75 {
 546                 compatible = "nxp,pca9548"; /* u135 */
 547                 #address-cells = <1>;
 548                 #size-cells = <0>;
 549                 reg = <0x75>;
 550
 551                 i2c@0 {
 552                         #address-cells = <1>;
 553                         #size-cells = <0>;
 554                         reg = <0>;
 555                         /* HPC0_IIC */
 556                 };
 557                 i2c@1 {
 558                         #address-cells = <1>;
 559                         #size-cells = <0>;
 560                         reg = <1>;
 561                         /* HPC1_IIC */
 562                 };
 563                 i2c@2 {
 564                         #address-cells = <1>;
 565                         #size-cells = <0>;
 566                         reg = <2>;
 567                         /* SYSMON */
 568                 };
 569                 i2c@3 {
 570                         #address-cells = <1>;
 571                         #size-cells = <0>;
 572                         reg = <3>;
 573                         /* DDR4 SODIMM */
 574                 };
 575                 i2c@4 {
 576                         #address-cells = <1>;
 577                         #size-cells = <0>;
 578                         reg = <4>;
 579                         /* SEP 3 */
 580                 };
 581                 i2c@5 {
 582                         #address-cells = <1>;
 583                         #size-cells = <0>;
 584                         reg = <5>;
 585                         /* SEP 2 */
 586                 };
 587                 i2c@6 {
 588                         #address-cells = <1>;
 589                         #size-cells = <0>;
 590                         reg = <6>;
 591                         /* SEP 1 */
 592                 };
 593                 i2c@7 {
 594                         #address-cells = <1>;
 595                         #size-cells = <0>;
 596                         reg = <7>;
 597                         /* SEP 0 */
 598                 };
 599         };
 600 };
 601
 602 &pcie {
 603         status = "okay";
 604 };
 605
 606 &qspi {
 607         status = "okay";
 608         is-dual = <1>;
 609         flash@0 {
 610                 compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
 611                 #address-cells = <1>;
 612                 #size-cells = <1>;
 613                 reg = <0x0>;
 614                 spi-tx-bus-width = <1>;
 615                 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
 616                 spi-max-frequency = <108000000>; /* Based on DC1 spec */
 617                 partition@0 { /* for testing purpose */
 618                         label = "qspi-fsbl-uboot";
 619                         reg = <0x0 0x100000>;
 620                 };
 621                 partition@100000 { /* for testing purpose */
 622                         label = "qspi-linux";
 623                         reg = <0x100000 0x500000>;
 624                 };
 625                 partition@600000 { /* for testing purpose */
 626                         label = "qspi-device-tree";
 627                         reg = <0x600000 0x20000>;
 628                 };
 629                 partition@620000 { /* for testing purpose */
 630                         label = "qspi-rootfs";
 631                         reg = <0x620000 0x5E0000>;
 632                 };
 633         };
 634 };
 635
 636 &rtc {
 637         status = "okay";
 638 };
 639
 640 &sata {
 641         status = "okay";
 642         /* SATA OOB timing settings */
 643         ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
 644         ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
 645         ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 646         ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 647         ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
 648         ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
 649         ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 650         ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 651         phy-names = "sata-phy";
 652         phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;
 653 };
 654
 655 /* SD1 with level shifter */
 656 &sdhci1 {
 657         status = "okay";
 658         /*
 659          * 1.0 revision has level shifter and this property should be
 660          * removed for supporting UHS mode
 661          */
 662         no-1-8-v;
 663         xlnx,mio_bank = <1>;
 664 };
 665
 666 &serdes {
 667         status = "okay";
 668 };
 669
 670 &uart0 {
 671         status = "okay";
 672 };
 673
 674 &uart1 {
 675         status = "okay";
 676 };
 677
 678 /* ULPI SMSC USB3320 */
 679 &usb0 {
 680         status = "okay";
 681 };
 682
 683 &dwc3_0 {
 684         status = "okay";
 685         dr_mode = "host";
 686         snps,usb3_lpm_capable;
 687         phy-names = "usb3-phy";
 688         phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
 689         maximum-speed = "super-speed";
 690 };
 691
 692 &watchdog0 {
 693         status = "okay";
 694 };
 695
 696 &xilinx_ams {
 697         status = "okay";
 698 };
 699
 700 &ams_ps {
 701         status = "okay";
 702 };
 703
 704 &ams_pl {
 705         status = "okay";
 706 };
 707
 708 &zynqmp_dpsub {
 709         status = "okay";
 710 };
 711
 712 &zynqmp_dp_snd_codec0 {
 713         status = "okay";
 714 };
 715
 716 &zynqmp_dp_snd_pcm0 {
 717         status = "okay";
 718 };
 719
 720 &zynqmp_dp_snd_pcm1 {
 721         status = "okay";
 722 };
 723
 724 &zynqmp_dp_snd_card0 {
 725         status = "okay";
 726 };
 727
 728 &xlnx_dpdma {
 729         status = "okay";
 730 };