arch/arm/dts/zynqmp-zcu102-revA.dts

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * dts file for Xilinx ZynqMP ZCU102 RevA
   4  *
   5  * (C) Copyright 2015 - 2021, Xilinx, Inc.
   6  *
   7  * Michal Simek <michal.simek@xilinx.com>
   8  */
   9
  10 /dts-v1/;
  11
  12 #include "zynqmp.dtsi"
  13 #include "zynqmp-clk-ccf.dtsi"
  14 #include <dt-bindings/input/input.h>
  15 #include <dt-bindings/gpio/gpio.h>
  16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
  17 #include <dt-bindings/phy/phy.h>
  18
  19 / {
  20         model = "ZynqMP ZCU102 RevA";
  21         compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
  22
  23         aliases {
  24                 ethernet0 = &gem3;
  25                 i2c0 = &i2c0;
  26                 i2c1 = &i2c1;
  27                 mmc0 = &sdhci1;
  28                 nvmem0 = &eeprom;
  29                 rtc0 = &rtc;
  30                 serial0 = &uart0;
  31                 serial1 = &uart1;
  32                 serial2 = &dcc;
  33                 spi0 = &qspi;
  34                 usb0 = &usb0;
  35         };
  36
  37         chosen {
  38                 bootargs = "earlycon";
  39                 stdout-path = "serial0:115200n8";
  40         };
  41
  42         memory@0 {
  43                 device_type = "memory";
  44                 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
  45         };
  46
  47         gpio-keys {
  48                 compatible = "gpio-keys";
  49                 autorepeat;
  50                 sw19 {
  51                         label = "sw19";
  52                         gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
  53                         linux,code = <KEY_DOWN>;
  54                         wakeup-source;
  55                         autorepeat;
  56                 };
  57         };
  58
  59         leds {
  60                 compatible = "gpio-leds";
  61                 heartbeat-led {
  62                         label = "heartbeat";
  63                         gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
  64                         linux,default-trigger = "heartbeat";
  65                 };
  66         };
  67
  68         ina226-u76 {
  69                 compatible = "iio-hwmon";
  70                 io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;
  71         };
  72         ina226-u77 {
  73                 compatible = "iio-hwmon";
  74                 io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;
  75         };
  76         ina226-u78 {
  77                 compatible = "iio-hwmon";
  78                 io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;
  79         };
  80         ina226-u87 {
  81                 compatible = "iio-hwmon";
  82                 io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;
  83         };
  84         ina226-u85 {
  85                 compatible = "iio-hwmon";
  86                 io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;
  87         };
  88         ina226-u86 {
  89                 compatible = "iio-hwmon";
  90                 io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;
  91         };
  92         ina226-u93 {
  93                 compatible = "iio-hwmon";
  94                 io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;
  95         };
  96         ina226-u88 {
  97                 compatible = "iio-hwmon";
  98                 io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;
  99         };
 100         ina226-u15 {
 101                 compatible = "iio-hwmon";
 102                 io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;
 103         };
 104         ina226-u92 {
 105                 compatible = "iio-hwmon";
 106                 io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;
 107         };
 108         ina226-u79 {
 109                 compatible = "iio-hwmon";
 110                 io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;
 111         };
 112         ina226-u81 {
 113                 compatible = "iio-hwmon";
 114                 io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;
 115         };
 116         ina226-u80 {
 117                 compatible = "iio-hwmon";
 118                 io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;
 119         };
 120         ina226-u84 {
 121                 compatible = "iio-hwmon";
 122                 io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;
 123         };
 124         ina226-u16 {
 125                 compatible = "iio-hwmon";
 126                 io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;
 127         };
 128         ina226-u65 {
 129                 compatible = "iio-hwmon";
 130                 io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;
 131         };
 132         ina226-u74 {
 133                 compatible = "iio-hwmon";
 134                 io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;
 135         };
 136         ina226-u75 {
 137                 compatible = "iio-hwmon";
 138                 io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;
 139         };
 140
 141         /* 48MHz reference crystal */
 142         ref48: ref48M {
 143                 compatible = "fixed-clock";
 144                 #clock-cells = <0>;
 145                 clock-frequency = <48000000>;
 146         };
 147
 148         refhdmi: refhdmi {
 149                 compatible = "fixed-clock";
 150                 #clock-cells = <0>;
 151                 clock-frequency = <114285000>;
 152         };
 153 };
 154
 155 &can1 {
 156         status = "okay";
 157         pinctrl-names = "default";
 158         pinctrl-0 = <&pinctrl_can1_default>;
 159 };
 160
 161 &dcc {
 162         status = "okay";
 163 };
 164
 165 &fpd_dma_chan1 {
 166         status = "okay";
 167 };
 168
 169 &fpd_dma_chan2 {
 170         status = "okay";
 171 };
 172
 173 &fpd_dma_chan3 {
 174         status = "okay";
 175 };
 176
 177 &fpd_dma_chan4 {
 178         status = "okay";
 179 };
 180
 181 &fpd_dma_chan5 {
 182         status = "okay";
 183 };
 184
 185 &fpd_dma_chan6 {
 186         status = "okay";
 187 };
 188
 189 &fpd_dma_chan7 {
 190         status = "okay";
 191 };
 192
 193 &fpd_dma_chan8 {
 194         status = "okay";
 195 };
 196
 197 &gem3 {
 198         status = "okay";
 199         phy-handle = <&phy0>;
 200         phy-mode = "rgmii-id";
 201         pinctrl-names = "default";
 202         pinctrl-0 = <&pinctrl_gem3_default>;
 203         phy0: ethernet-phy@21 {
 204                 reg = <21>;
 205                 ti,rx-internal-delay = <0x8>;
 206                 ti,tx-internal-delay = <0xa>;
 207                 ti,fifo-depth = <0x1>;
 208                 ti,dp83867-rxctrl-strap-quirk;
 209                 /* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */
 210         };
 211 };
 212
 213 &gpio {
 214         status = "okay";
 215         pinctrl-names = "default";
 216         pinctrl-0 = <&pinctrl_gpio_default>;
 217 };
 218
 219 &gpu {
 220         status = "okay";
 221 };
 222
 223 &i2c0 {
 224         status = "okay";
 225         clock-frequency = <400000>;
 226         pinctrl-names = "default", "gpio";
 227         pinctrl-0 = <&pinctrl_i2c0_default>;
 228         pinctrl-1 = <&pinctrl_i2c0_gpio>;
 229         scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
 230         sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
 231
 232         tca6416_u97: gpio@20 {
 233                 compatible = "ti,tca6416";
 234                 reg = <0x20>;
 235                 gpio-controller; /* IRQ not connected */
 236                 #gpio-cells = <2>;
 237                 gpio-line-names = "PS_GTR_LAN_SEL0", "PS_GTR_LAN_SEL1", "PS_GTR_LAN_SEL2", "PS_GTR_LAN_SEL3",
 238                                 "PCI_CLK_DIR_SEL", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B",
 239                                 "", "", "", "", "", "", "", "", "";
 240                 gtr-sel0-hog {
 241                         gpio-hog;
 242                         gpios = <0 0>;
 243                         output-low; /* PCIE = 0, DP = 1 */
 244                         line-name = "sel0";
 245                 };
 246                 gtr-sel1-hog {
 247                         gpio-hog;
 248                         gpios = <1 0>;
 249                         output-high; /* PCIE = 0, DP = 1 */
 250                         line-name = "sel1";
 251                 };
 252                 gtr-sel2-hog {
 253                         gpio-hog;
 254                         gpios = <2 0>;
 255                         output-high; /* PCIE = 0, USB0 = 1 */
 256                         line-name = "sel2";
 257                 };
 258                 gtr-sel3-hog {
 259                         gpio-hog;
 260                         gpios = <3 0>;
 261                         output-high; /* PCIE = 0, SATA = 1 */
 262                         line-name = "sel3";
 263                 };
 264         };
 265
 266         tca6416_u61: gpio@21 {
 267                 compatible = "ti,tca6416";
 268                 reg = <0x21>;
 269                 gpio-controller; /* IRQ not connected */
 270                 #gpio-cells = <2>;
 271                 gpio-line-names = "VCCPSPLL_EN", "MGTRAVCC_EN", "MGTRAVTT_EN", "VCCPSDDRPLL_EN", "MIO26_PMU_INPUT_LS",
 272                                 "PL_PMBUS_ALERT", "PS_PMBUS_ALERT", "MAXIM_PMBUS_ALERT", "PL_DDR4_VTERM_EN",
 273                                 "PL_DDR4_VPP_2V5_EN", "PS_DIMM_VDDQ_TO_PSVCCO_ON", "PS_DIMM_SUSPEND_EN",
 274                                 "PS_DDR4_VTERM_EN", "PS_DDR4_VPP_2V5_EN", "", "";
 275         };
 276
 277         i2c-mux@75 { /* u60 */
 278                 compatible = "nxp,pca9544";
 279                 #address-cells = <1>;
 280                 #size-cells = <0>;
 281                 reg = <0x75>;
 282                 i2c@0 {
 283                         #address-cells = <1>;
 284                         #size-cells = <0>;
 285                         reg = <0>;
 286                         /* PS_PMBUS */
 287                         u76: ina226@40 { /* u76 */
 288                                 compatible = "ti,ina226";
 289                                 #io-channel-cells = <1>;
 290                                 label = "ina226-u76";
 291                                 reg = <0x40>;
 292                                 shunt-resistor = <5000>;
 293                         };
 294                         u77: ina226@41 { /* u77 */
 295                                 compatible = "ti,ina226";
 296                                 #io-channel-cells = <1>;
 297                                 label = "ina226-u77";
 298                                 reg = <0x41>;
 299                                 shunt-resistor = <5000>;
 300                         };
 301                         u78: ina226@42 { /* u78 */
 302                                 compatible = "ti,ina226";
 303                                 #io-channel-cells = <1>;
 304                                 label = "ina226-u78";
 305                                 reg = <0x42>;
 306                                 shunt-resistor = <5000>;
 307                         };
 308                         u87: ina226@43 { /* u87 */
 309                                 compatible = "ti,ina226";
 310                                 #io-channel-cells = <1>;
 311                                 label = "ina226-u87";
 312                                 reg = <0x43>;
 313                                 shunt-resistor = <5000>;
 314                         };
 315                         u85: ina226@44 { /* u85 */
 316                                 compatible = "ti,ina226";
 317                                 #io-channel-cells = <1>;
 318                                 label = "ina226-u85";
 319                                 reg = <0x44>;
 320                                 shunt-resistor = <5000>;
 321                         };
 322                         u86: ina226@45 { /* u86 */
 323                                 compatible = "ti,ina226";
 324                                 #io-channel-cells = <1>;
 325                                 label = "ina226-u86";
 326                                 reg = <0x45>;
 327                                 shunt-resistor = <5000>;
 328                         };
 329                         u93: ina226@46 { /* u93 */
 330                                 compatible = "ti,ina226";
 331                                 #io-channel-cells = <1>;
 332                                 label = "ina226-u93";
 333                                 reg = <0x46>;
 334                                 shunt-resistor = <5000>;
 335                         };
 336                         u88: ina226@47 { /* u88 */
 337                                 compatible = "ti,ina226";
 338                                 #io-channel-cells = <1>;
 339                                 label = "ina226-u88";
 340                                 reg = <0x47>;
 341                                 shunt-resistor = <5000>;
 342                         };
 343                         u15: ina226@4a { /* u15 */
 344                                 compatible = "ti,ina226";
 345                                 #io-channel-cells = <1>;
 346                                 label = "ina226-u15";
 347                                 reg = <0x4a>;
 348                                 shunt-resistor = <5000>;
 349                         };
 350                         u92: ina226@4b { /* u92 */
 351                                 compatible = "ti,ina226";
 352                                 #io-channel-cells = <1>;
 353                                 label = "ina226-u92";
 354                                 reg = <0x4b>;
 355                                 shunt-resistor = <5000>;
 356                         };
 357                 };
 358                 i2c@1 {
 359                         #address-cells = <1>;
 360                         #size-cells = <0>;
 361                         reg = <1>;
 362                         /* PL_PMBUS */
 363                         u79: ina226@40 { /* u79 */
 364                                 compatible = "ti,ina226";
 365                                 #io-channel-cells = <1>;
 366                                 label = "ina226-u79";
 367                                 reg = <0x40>;
 368                                 shunt-resistor = <2000>;
 369                         };
 370                         u81: ina226@41 { /* u81 */
 371                                 compatible = "ti,ina226";
 372                                 #io-channel-cells = <1>;
 373                                 label = "ina226-u81";
 374                                 reg = <0x41>;
 375                                 shunt-resistor = <5000>;
 376                         };
 377                         u80: ina226@42 { /* u80 */
 378                                 compatible = "ti,ina226";
 379                                 #io-channel-cells = <1>;
 380                                 label = "ina226-u80";
 381                                 reg = <0x42>;
 382                                 shunt-resistor = <5000>;
 383                         };
 384                         u84: ina226@43 { /* u84 */
 385                                 compatible = "ti,ina226";
 386                                 #io-channel-cells = <1>;
 387                                 label = "ina226-u84";
 388                                 reg = <0x43>;
 389                                 shunt-resistor = <5000>;
 390                         };
 391                         u16: ina226@44 { /* u16 */
 392                                 compatible = "ti,ina226";
 393                                 #io-channel-cells = <1>;
 394                                 label = "ina226-u16";
 395                                 reg = <0x44>;
 396                                 shunt-resistor = <5000>;
 397                         };
 398                         u65: ina226@45 { /* u65 */
 399                                 compatible = "ti,ina226";
 400                                 #io-channel-cells = <1>;
 401                                 label = "ina226-u65";
 402                                 reg = <0x45>;
 403                                 shunt-resistor = <5000>;
 404                         };
 405                         u74: ina226@46 { /* u74 */
 406                                 compatible = "ti,ina226";
 407                                 #io-channel-cells = <1>;
 408                                 label = "ina226-u74";
 409                                 reg = <0x46>;
 410                                 shunt-resistor = <5000>;
 411                         };
 412                         u75: ina226@47 { /* u75 */
 413                                 compatible = "ti,ina226";
 414                                 #io-channel-cells = <1>;
 415                                 label = "ina226-u75";
 416                                 reg = <0x47>;
 417                                 shunt-resistor = <5000>;
 418                         };
 419                 };
 420                 i2c@2 {
 421                         #address-cells = <1>;
 422                         #size-cells = <0>;
 423                         reg = <2>;
 424                         /* MAXIM_PMBUS - 00 */
 425                         max15301@a { /* u46 */
 426                                 compatible = "maxim,max15301";
 427                                 reg = <0xa>;
 428                         };
 429                         max15303@b { /* u4 */
 430                                 compatible = "maxim,max15303";
 431                                 reg = <0xb>;
 432                         };
 433                         max15303@10 { /* u13 */
 434                                 compatible = "maxim,max15303";
 435                                 reg = <0x10>;
 436                         };
 437                         max15301@13 { /* u47 */
 438                                 compatible = "maxim,max15301";
 439                                 reg = <0x13>;
 440                         };
 441                         max15303@14 { /* u7 */
 442                                 compatible = "maxim,max15303";
 443                                 reg = <0x14>;
 444                         };
 445                         max15303@15 { /* u6 */
 446                                 compatible = "maxim,max15303";
 447                                 reg = <0x15>;
 448                         };
 449                         max15303@16 { /* u10 */
 450                                 compatible = "maxim,max15303";
 451                                 reg = <0x16>;
 452                         };
 453                         max15303@17 { /* u9 */
 454                                 compatible = "maxim,max15303";
 455                                 reg = <0x17>;
 456                         };
 457                         max15301@18 { /* u63 */
 458                                 compatible = "maxim,max15301";
 459                                 reg = <0x18>;
 460                         };
 461                         max15303@1a { /* u49 */
 462                                 compatible = "maxim,max15303";
 463                                 reg = <0x1a>;
 464                         };
 465                         max15303@1d { /* u18 */
 466                                 compatible = "maxim,max15303";
 467                                 reg = <0x1d>;
 468                         };
 469                         max15303@20 { /* u8 */
 470                                 compatible = "maxim,max15303";
 471                                 status = "disabled"; /* unreachable */
 472                                 reg = <0x20>;
 473                         };
 474                         max20751@72 { /* u95 */
 475                                 compatible = "maxim,max20751";
 476                                 reg = <0x72>;
 477                         };
 478                         max20751@73 { /* u96 */
 479                                 compatible = "maxim,max20751";
 480                                 reg = <0x73>;
 481                         };
 482                 };
 483                 /* Bus 3 is not connected */
 484         };
 485 };
 486
 487 &i2c1 {
 488         status = "okay";
 489         clock-frequency = <400000>;
 490         pinctrl-names = "default", "gpio";
 491         pinctrl-0 = <&pinctrl_i2c1_default>;
 492         pinctrl-1 = <&pinctrl_i2c1_gpio>;
 493         scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
 494         sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
 495
 496         /* PL i2c via PCA9306 - u45 */
 497         i2c-mux@74 { /* u34 */
 498                 compatible = "nxp,pca9548";
 499                 #address-cells = <1>;
 500                 #size-cells = <0>;
 501                 reg = <0x74>;
 502                 i2c@0 {
 503                         #address-cells = <1>;
 504                         #size-cells = <0>;
 505                         reg = <0>;
 506                         /*
 507                          * IIC_EEPROM 1kB memory which uses 256B blocks
 508                          * where every block has different address.
 509                          *    0 - 256B address 0x54
 510                          * 256B - 512B address 0x55
 511                          * 512B - 768B address 0x56
 512                          * 768B - 1024B address 0x57
 513                          */
 514                         eeprom: eeprom@54 { /* u23 */
 515                                 compatible = "atmel,24c08";
 516                                 reg = <0x54>;
 517                         };
 518                 };
 519                 i2c@1 {
 520                         #address-cells = <1>;
 521                         #size-cells = <0>;
 522                         reg = <1>;
 523                         si5341: clock-generator@36 { /* SI5341 - u69 */
 524                                 compatible = "silabs,si5341";
 525                                 reg = <0x36>;
 526                                 #clock-cells = <2>;
 527                                 #address-cells = <1>;
 528                                 #size-cells = <0>;
 529                                 clocks = <&ref48>;
 530                                 clock-names = "xtal";
 531                                 clock-output-names = "si5341";
 532
 533                                 si5341_0: out@0 {
 534                                         /* refclk0 for PS-GT, used for DP */
 535                                         reg = <0>;
 536                                         always-on;
 537                                 };
 538                                 si5341_2: out@2 {
 539                                         /* refclk2 for PS-GT, used for USB3 */
 540                                         reg = <2>;
 541                                         always-on;
 542                                 };
 543                                 si5341_3: out@3 {
 544                                         /* refclk3 for PS-GT, used for SATA */
 545                                         reg = <3>;
 546                                         always-on;
 547                                 };
 548                                 si5341_4: out@4 {
 549                                         /* refclk4 for PS-GT, used for PCIE slot */
 550                                         reg = <4>;
 551                                         always-on;
 552                                 };
 553                                 si5341_5: out@5 {
 554                                         /* refclk5 for PS-GT, used for PCIE */
 555                                         reg = <5>;
 556                                         always-on;
 557                                 };
 558                                 si5341_6: out@6 {
 559                                         /* refclk6 PL CLK125 */
 560                                         reg = <6>;
 561                                         always-on;
 562                                 };
 563                                 si5341_7: out@7 {
 564                                         /* refclk7 PL CLK74 */
 565                                         reg = <7>;
 566                                         always-on;
 567                                 };
 568                                 si5341_9: out@9 {
 569                                         /* refclk9 used for PS_REF_CLK 33.3 MHz */
 570                                         reg = <9>;
 571                                         always-on;
 572                                 };
 573                         };
 574                 };
 575                 i2c@2 {
 576                         #address-cells = <1>;
 577                         #size-cells = <0>;
 578                         reg = <2>;
 579                         si570_1: clock-generator@5d { /* USER SI570 - u42 */
 580                                 #clock-cells = <0>;
 581                                 compatible = "silabs,si570";
 582                                 reg = <0x5d>;
 583                                 temperature-stability = <50>;
 584                                 factory-fout = <300000000>;
 585                                 clock-frequency = <300000000>;
 586                                 clock-output-names = "si570_user";
 587                         };
 588                 };
 589                 i2c@3 {
 590                         #address-cells = <1>;
 591                         #size-cells = <0>;
 592                         reg = <3>;
 593                         si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */
 594                                 #clock-cells = <0>;
 595                                 compatible = "silabs,si570";
 596                                 reg = <0x5d>;
 597                                 temperature-stability = <50>; /* copy from zc702 */
 598                                 factory-fout = <156250000>;
 599                                 clock-frequency = <148500000>;
 600                                 clock-output-names = "si570_mgt";
 601                         };
 602                 };
 603                 i2c@4 {
 604                         #address-cells = <1>;
 605                         #size-cells = <0>;
 606                         reg = <4>;
 607                         /* SI5328 - u20 */
 608                 };
 609                 /* 5 - 7 unconnected */
 610         };
 611
 612         i2c-mux@75 {
 613                 compatible = "nxp,pca9548"; /* u135 */
 614                 #address-cells = <1>;
 615                 #size-cells = <0>;
 616                 reg = <0x75>;
 617
 618                 i2c@0 {
 619                         #address-cells = <1>;
 620                         #size-cells = <0>;
 621                         reg = <0>;
 622                         /* HPC0_IIC */
 623                 };
 624                 i2c@1 {
 625                         #address-cells = <1>;
 626                         #size-cells = <0>;
 627                         reg = <1>;
 628                         /* HPC1_IIC */
 629                 };
 630                 i2c@2 {
 631                         #address-cells = <1>;
 632                         #size-cells = <0>;
 633                         reg = <2>;
 634                         /* SYSMON */
 635                 };
 636                 i2c@3 {
 637                         #address-cells = <1>;
 638                         #size-cells = <0>;
 639                         reg = <3>;
 640                         /* DDR4 SODIMM */
 641                 };
 642                 i2c@4 {
 643                         #address-cells = <1>;
 644                         #size-cells = <0>;
 645                         reg = <4>;
 646                         /* SEP 3 */
 647                 };
 648                 i2c@5 {
 649                         #address-cells = <1>;
 650                         #size-cells = <0>;
 651                         reg = <5>;
 652                         /* SEP 2 */
 653                 };
 654                 i2c@6 {
 655                         #address-cells = <1>;
 656                         #size-cells = <0>;
 657                         reg = <6>;
 658                         /* SEP 1 */
 659                 };
 660                 i2c@7 {
 661                         #address-cells = <1>;
 662                         #size-cells = <0>;
 663                         reg = <7>;
 664                         /* SEP 0 */
 665                 };
 666         };
 667 };
 668
 669 &pinctrl0 {
 670         status = "okay";
 671         pinctrl_i2c0_default: i2c0-default {
 672                 mux {
 673                         groups = "i2c0_3_grp";
 674                         function = "i2c0";
 675                 };
 676
 677                 conf {
 678                         groups = "i2c0_3_grp";
 679                         bias-pull-up;
 680                         slew-rate = <SLEW_RATE_SLOW>;
 681                         power-source = <IO_STANDARD_LVCMOS18>;
 682                 };
 683         };
 684
 685         pinctrl_i2c0_gpio: i2c0-gpio {
 686                 mux {
 687                         groups = "gpio0_14_grp", "gpio0_15_grp";
 688                         function = "gpio0";
 689                 };
 690
 691                 conf {
 692                         groups = "gpio0_14_grp", "gpio0_15_grp";
 693                         slew-rate = <SLEW_RATE_SLOW>;
 694                         power-source = <IO_STANDARD_LVCMOS18>;
 695                 };
 696         };
 697
 698         pinctrl_i2c1_default: i2c1-default {
 699                 mux {
 700                         groups = "i2c1_4_grp";
 701                         function = "i2c1";
 702                 };
 703
 704                 conf {
 705                         groups = "i2c1_4_grp";
 706                         bias-pull-up;
 707                         slew-rate = <SLEW_RATE_SLOW>;
 708                         power-source = <IO_STANDARD_LVCMOS18>;
 709                 };
 710         };
 711
 712         pinctrl_i2c1_gpio: i2c1-gpio {
 713                 mux {
 714                         groups = "gpio0_16_grp", "gpio0_17_grp";
 715                         function = "gpio0";
 716                 };
 717
 718                 conf {
 719                         groups = "gpio0_16_grp", "gpio0_17_grp";
 720                         slew-rate = <SLEW_RATE_SLOW>;
 721                         power-source = <IO_STANDARD_LVCMOS18>;
 722                 };
 723         };
 724
 725         pinctrl_uart0_default: uart0-default {
 726                 mux {
 727                         groups = "uart0_4_grp";
 728                         function = "uart0";
 729                 };
 730
 731                 conf {
 732                         groups = "uart0_4_grp";
 733                         slew-rate = <SLEW_RATE_SLOW>;
 734                         power-source = <IO_STANDARD_LVCMOS18>;
 735                 };
 736
 737                 conf-rx {
 738                         pins = "MIO18";
 739                         bias-high-impedance;
 740                 };
 741
 742                 conf-tx {
 743                         pins = "MIO19";
 744                         bias-disable;
 745                 };
 746         };
 747
 748         pinctrl_uart1_default: uart1-default {
 749                 mux {
 750                         groups = "uart1_5_grp";
 751                         function = "uart1";
 752                 };
 753
 754                 conf {
 755                         groups = "uart1_5_grp";
 756                         slew-rate = <SLEW_RATE_SLOW>;
 757                         power-source = <IO_STANDARD_LVCMOS18>;
 758                 };
 759
 760                 conf-rx {
 761                         pins = "MIO21";
 762                         bias-high-impedance;
 763                 };
 764
 765                 conf-tx {
 766                         pins = "MIO20";
 767                         bias-disable;
 768                 };
 769         };
 770
 771         pinctrl_usb0_default: usb0-default {
 772                 mux {
 773                         groups = "usb0_0_grp";
 774                         function = "usb0";
 775                 };
 776
 777                 conf {
 778                         groups = "usb0_0_grp";
 779                         slew-rate = <SLEW_RATE_SLOW>;
 780                         power-source = <IO_STANDARD_LVCMOS18>;
 781                 };
 782
 783                 conf-rx {
 784                         pins = "MIO52", "MIO53", "MIO55";
 785                         bias-high-impedance;
 786                 };
 787
 788                 conf-tx {
 789                         pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
 790                                "MIO60", "MIO61", "MIO62", "MIO63";
 791                         bias-disable;
 792                 };
 793         };
 794
 795         pinctrl_gem3_default: gem3-default {
 796                 mux {
 797                         function = "ethernet3";
 798                         groups = "ethernet3_0_grp";
 799                 };
 800
 801                 conf {
 802                         groups = "ethernet3_0_grp";
 803                         slew-rate = <SLEW_RATE_SLOW>;
 804                         power-source = <IO_STANDARD_LVCMOS18>;
 805                 };
 806
 807                 conf-rx {
 808                         pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
 809                                                                         "MIO75";
 810                         bias-high-impedance;
 811                         low-power-disable;
 812                 };
 813
 814                 conf-tx {
 815                         pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
 816                                                                         "MIO69";
 817                         bias-disable;
 818                         low-power-enable;
 819                 };
 820
 821                 mux-mdio {
 822                         function = "mdio3";
 823                         groups = "mdio3_0_grp";
 824                 };
 825
 826                 conf-mdio {
 827                         groups = "mdio3_0_grp";
 828                         slew-rate = <SLEW_RATE_SLOW>;
 829                         power-source = <IO_STANDARD_LVCMOS18>;
 830                         bias-disable;
 831                 };
 832         };
 833
 834         pinctrl_can1_default: can1-default {
 835                 mux {
 836                         function = "can1";
 837                         groups = "can1_6_grp";
 838                 };
 839
 840                 conf {
 841                         groups = "can1_6_grp";
 842                         slew-rate = <SLEW_RATE_SLOW>;
 843                         power-source = <IO_STANDARD_LVCMOS18>;
 844                 };
 845
 846                 conf-rx {
 847                         pins = "MIO25";
 848                         bias-high-impedance;
 849                 };
 850
 851                 conf-tx {
 852                         pins = "MIO24";
 853                         bias-disable;
 854                 };
 855         };
 856
 857         pinctrl_sdhci1_default: sdhci1-default {
 858                 mux {
 859                         groups = "sdio1_0_grp";
 860                         function = "sdio1";
 861                 };
 862
 863                 conf {
 864                         groups = "sdio1_0_grp";
 865                         slew-rate = <SLEW_RATE_SLOW>;
 866                         power-source = <IO_STANDARD_LVCMOS18>;
 867                         bias-disable;
 868                 };
 869
 870                 mux-cd {
 871                         groups = "sdio1_cd_0_grp";
 872                         function = "sdio1_cd";
 873                 };
 874
 875                 conf-cd {
 876                         groups = "sdio1_cd_0_grp";
 877                         bias-high-impedance;
 878                         bias-pull-up;
 879                         slew-rate = <SLEW_RATE_SLOW>;
 880                         power-source = <IO_STANDARD_LVCMOS18>;
 881                 };
 882
 883                 mux-wp {
 884                         groups = "sdio1_wp_0_grp";
 885                         function = "sdio1_wp";
 886                 };
 887
 888                 conf-wp {
 889                         groups = "sdio1_wp_0_grp";
 890                         bias-high-impedance;
 891                         bias-pull-up;
 892                         slew-rate = <SLEW_RATE_SLOW>;
 893                         power-source = <IO_STANDARD_LVCMOS18>;
 894                 };
 895         };
 896
 897         pinctrl_gpio_default: gpio-default {
 898                 mux-sw {
 899                         function = "gpio0";
 900                         groups = "gpio0_22_grp", "gpio0_23_grp";
 901                 };
 902
 903                 conf-sw {
 904                         groups = "gpio0_22_grp", "gpio0_23_grp";
 905                         slew-rate = <SLEW_RATE_SLOW>;
 906                         power-source = <IO_STANDARD_LVCMOS18>;
 907                 };
 908
 909                 mux-msp {
 910                         function = "gpio0";
 911                         groups = "gpio0_13_grp", "gpio0_38_grp";
 912                 };
 913
 914                 conf-msp {
 915                         groups = "gpio0_13_grp", "gpio0_38_grp";
 916                         slew-rate = <SLEW_RATE_SLOW>;
 917                         power-source = <IO_STANDARD_LVCMOS18>;
 918                 };
 919
 920                 conf-pull-up {
 921                         pins = "MIO22", "MIO23";
 922                         bias-pull-up;
 923                 };
 924
 925                 conf-pull-none {
 926                         pins = "MIO13", "MIO38";
 927                         bias-disable;
 928                 };
 929         };
 930 };
 931
 932 &pcie {
 933         status = "okay";
 934 };
 935
 936 &psgtr {
 937         status = "okay";
 938         /* pcie, sata, usb3, dp */
 939         clocks = <&si5341 0 5>, <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;
 940         clock-names = "ref0", "ref1", "ref2", "ref3";
 941 };
 942
 943 &qspi {
 944         status = "okay";
 945         is-dual = <1>;
 946         flash@0 {
 947                 compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
 948                 #address-cells = <1>;
 949                 #size-cells = <1>;
 950                 reg = <0x0>;
 951                 spi-tx-bus-width = <1>;
 952                 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
 953                 spi-max-frequency = <108000000>; /* Based on DC1 spec */
 954                 partition@0 { /* for testing purpose */
 955                         label = "qspi-fsbl-uboot";
 956                         reg = <0x0 0x100000>;
 957                 };
 958                 partition@100000 { /* for testing purpose */
 959                         label = "qspi-linux";
 960                         reg = <0x100000 0x500000>;
 961                 };
 962                 partition@600000 { /* for testing purpose */
 963                         label = "qspi-device-tree";
 964                         reg = <0x600000 0x20000>;
 965                 };
 966                 partition@620000 { /* for testing purpose */
 967                         label = "qspi-rootfs";
 968                         reg = <0x620000 0x5E0000>;
 969                 };
 970         };
 971 };
 972
 973 &rtc {
 974         status = "okay";
 975 };
 976
 977 &sata {
 978         status = "okay";
 979         /* SATA OOB timing settings */
 980         ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
 981         ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
 982         ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 983         ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 984         ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
 985         ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
 986         ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 987         ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 988         phy-names = "sata-phy";
 989         phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
 990 };
 991
 992 /* SD1 with level shifter */
 993 &sdhci1 {
 994         status = "okay";
 995         /*
 996          * 1.0 revision has level shifter and this property should be
 997          * removed for supporting UHS mode
 998          */
 999         no-1-8-v;
1000         pinctrl-names = "default";
1001         pinctrl-0 = <&pinctrl_sdhci1_default>;
1002         xlnx,mio-bank = <1>;
1003 };
1004
1005 &uart0 {
1006         status = "okay";
1007         pinctrl-names = "default";
1008         pinctrl-0 = <&pinctrl_uart0_default>;
1009 };
1010
1011 &uart1 {
1012         status = "okay";
1013         pinctrl-names = "default";
1014         pinctrl-0 = <&pinctrl_uart1_default>;
1015 };
1016
1017 /* ULPI SMSC USB3320 */
1018 &usb0 {
1019         status = "okay";
1020         pinctrl-names = "default";
1021         pinctrl-0 = <&pinctrl_usb0_default>;
1022 };
1023
1024 &dwc3_0 {
1025         status = "okay";
1026         dr_mode = "host";
1027         snps,usb3_lpm_capable;
1028         phy-names = "usb3-phy";
1029         phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
1030         maximum-speed = "super-speed";
1031 };
1032
1033 &watchdog0 {
1034         status = "okay";
1035 };
1036
1037 &xilinx_ams {
1038         status = "okay";
1039 };
1040
1041 &ams_ps {
1042         status = "okay";
1043 };
1044
1045 &ams_pl {
1046         status = "okay";
1047 };
1048
1049 &zynqmp_dpdma {
1050         status = "okay";
1051 };
1052
1053 &zynqmp_dpsub {
1054         status = "okay";
1055         phy-names = "dp-phy0";
1056         phys = <&psgtr 1 PHY_TYPE_DP 0 3>;
1057 };