arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * dts file for Xilinx ZynqMP zc1751-xm018-dc4
   4  *
   5  * (C) Copyright 2015 - 2021, Xilinx, Inc.
   6  *
   7  * Michal Simek <michal.simek@xilinx.com>
   8  */
   9
  10 /dts-v1/;
  11
  12 #include "zynqmp.dtsi"
  13 #include "zynqmp-clk-ccf.dtsi"
  14
  15 / {
  16         model = "ZynqMP zc1751-xm018-dc4";
  17         compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
  18
  19         aliases {
  20                 ethernet0 = &gem0;
  21                 ethernet1 = &gem1;
  22                 ethernet2 = &gem2;
  23                 ethernet3 = &gem3;
  24                 gpio0 = &gpio;
  25                 i2c0 = &i2c0;
  26                 i2c1 = &i2c1;
  27                 rtc0 = &rtc;
  28                 serial0 = &uart0;
  29                 serial1 = &uart1;
  30                 spi0 = &qspi;
  31         };
  32
  33         chosen {
  34                 bootargs = "earlycon";
  35                 stdout-path = "serial0:115200n8";
  36         };
  37
  38         memory@0 {
  39                 device_type = "memory";
  40                 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
  41         };
  42 };
  43
  44 &can0 {
  45         status = "okay";
  46 };
  47
  48 &can1 {
  49         status = "okay";
  50 };
  51
  52 &fpd_dma_chan1 {
  53         status = "okay";
  54 };
  55
  56 &fpd_dma_chan2 {
  57         status = "okay";
  58 };
  59
  60 &fpd_dma_chan3 {
  61         status = "okay";
  62 };
  63
  64 &fpd_dma_chan4 {
  65         status = "okay";
  66 };
  67
  68 &fpd_dma_chan5 {
  69         status = "okay";
  70 };
  71
  72 &fpd_dma_chan6 {
  73         status = "okay";
  74 };
  75
  76 &fpd_dma_chan7 {
  77         status = "okay";
  78 };
  79
  80 &fpd_dma_chan8 {
  81         status = "okay";
  82 };
  83
  84 &lpd_dma_chan1 {
  85         status = "okay";
  86 };
  87
  88 &lpd_dma_chan2 {
  89         status = "okay";
  90 };
  91
  92 &lpd_dma_chan3 {
  93         status = "okay";
  94 };
  95
  96 &lpd_dma_chan4 {
  97         status = "okay";
  98 };
  99
 100 &lpd_dma_chan5 {
 101         status = "okay";
 102 };
 103
 104 &lpd_dma_chan6 {
 105         status = "okay";
 106 };
 107
 108 &lpd_dma_chan7 {
 109         status = "okay";
 110 };
 111
 112 &lpd_dma_chan8 {
 113         status = "okay";
 114 };
 115
 116 &gem0 {
 117         status = "okay";
 118         phy-mode = "rgmii-id";
 119         phy-handle = <&ethernet_phy0>;
 120         ethernet_phy0: ethernet-phy@0 { /* Marvell 88e1512 */
 121                 reg = <0>;
 122         };
 123         ethernet_phy7: ethernet-phy@7 { /* Vitesse VSC8211 */
 124                 reg = <7>;
 125         };
 126         ethernet_phy3: ethernet-phy@3 { /* Realtek RTL8211DN */
 127                 reg = <3>;
 128         };
 129         ethernet_phy8: ethernet-phy@8 { /* Vitesse VSC8211 */
 130                 reg = <8>;
 131         };
 132 };
 133
 134 &gem1 {
 135         status = "okay";
 136         phy-mode = "rgmii-id";
 137         phy-handle = <&ethernet_phy7>;
 138 };
 139
 140 &gem2 {
 141         status = "okay";
 142         phy-mode = "rgmii-id";
 143         phy-handle = <&ethernet_phy3>;
 144 };
 145
 146 &gem3 {
 147         status = "okay";
 148         phy-mode = "rgmii-id";
 149         phy-handle = <&ethernet_phy8>;
 150 };
 151
 152 &gpio {
 153         status = "okay";
 154 };
 155
 156 &gpu {
 157         status = "okay";
 158 };
 159
 160 &i2c0 {
 161         clock-frequency = <400000>;
 162         status = "okay";
 163 };
 164
 165 &i2c1 {
 166         clock-frequency = <400000>;
 167         status = "okay";
 168 };
 169
 170 &qspi {
 171         status = "okay";
 172         flash@0 {
 173                 compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
 174                 #address-cells = <1>;
 175                 #size-cells = <1>;
 176                 reg = <0x0>;
 177                 spi-tx-bus-width = <1>;
 178                 spi-rx-bus-width = <4>; /* also DUAL configuration possible */
 179                 spi-max-frequency = <108000000>; /* Based on DC1 spec */
 180                 partition@0 { /* for testing purpose */
 181                         label = "qspi-fsbl-uboot";
 182                         reg = <0x0 0x100000>;
 183                 };
 184                 partition@100000 { /* for testing purpose */
 185                         label = "qspi-linux";
 186                         reg = <0x100000 0x500000>;
 187                 };
 188                 partition@600000 { /* for testing purpose */
 189                         label = "qspi-device-tree";
 190                         reg = <0x600000 0x20000>;
 191                 };
 192                 partition@620000 { /* for testing purpose */
 193                         label = "qspi-rootfs";
 194                         reg = <0x620000 0x5E0000>;
 195                 };
 196         };
 197 };
 198
 199 &rtc {
 200         status = "okay";
 201 };
 202
 203 &uart0 {
 204         status = "okay";
 205 };
 206
 207 &uart1 {
 208         status = "okay";
 209 };
 210
 211 &watchdog0 {
 212         status = "okay";
 213 };
 214
 215 &zynqmp_dpdma {
 216         status = "okay";
 217 };
 218
 219 &zynqmp_dpsub {
 220         status = "okay";
 221 };