1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm018-dc4
5 * (C) Copyright 2015 - 2021, Xilinx, Inc.
7 * Michal Simek <michal.simek@xilinx.com>
12 #include "zynqmp.dtsi"
13 #include "zynqmp-clk-ccf.dtsi"
16 model = "ZynqMP zc1751-xm018-dc4";
17 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
34 bootargs = "earlycon";
35 stdout-path = "serial0:115200n8";
39 device_type = "memory";
40 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
118 phy-mode = "rgmii-id";
119 phy-handle = <ðernet_phy0>;
120 ethernet_phy0: ethernet-phy@0 { /* Marvell 88e1512 */
123 ethernet_phy7: ethernet-phy@7 { /* Vitesse VSC8211 */
126 ethernet_phy3: ethernet-phy@3 { /* Realtek RTL8211DN */
129 ethernet_phy8: ethernet-phy@8 { /* Vitesse VSC8211 */
136 phy-mode = "rgmii-id";
137 phy-handle = <ðernet_phy7>;
142 phy-mode = "rgmii-id";
143 phy-handle = <ðernet_phy3>;
148 phy-mode = "rgmii-id";
149 phy-handle = <ðernet_phy8>;
161 clock-frequency = <400000>;
166 clock-frequency = <400000>;
173 compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
174 #address-cells = <1>;
177 spi-tx-bus-width = <1>;
178 spi-rx-bus-width = <4>; /* also DUAL configuration possible */
179 spi-max-frequency = <108000000>; /* Based on DC1 spec */
180 partition@0 { /* for testing purpose */
181 label = "qspi-fsbl-uboot";
182 reg = <0x0 0x100000>;
184 partition@100000 { /* for testing purpose */
185 label = "qspi-linux";
186 reg = <0x100000 0x500000>;
188 partition@600000 { /* for testing purpose */
189 label = "qspi-device-tree";
190 reg = <0x600000 0x20000>;
192 partition@620000 { /* for testing purpose */
193 label = "qspi-rootfs";
194 reg = <0x620000 0x5E0000>;