1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm015-dc1
5 * (C) Copyright 2015 - 2020, Xilinx, Inc.
7 * Michal Simek <michal.simek@xilinx.com>
12 #include "zynqmp.dtsi"
13 #include "zynqmp-clk-ccf.dtsi"
16 model = "ZynqMP zc1751-xm015-dc1 RevA";
17 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
32 bootargs = "earlycon";
33 stdout-path = "serial0:115200n8";
37 device_type = "memory";
38 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
77 phy-mode = "rgmii-id";
78 phy0: ethernet-phy@0 {
93 clock-frequency = <400000>;
96 compatible = "atmel,24c64"; /* 24AA64 */
104 compatible = "m25p80", "jedec,spi-nor"; /* Micron MT25QU512ABB8ESF */
105 #address-cells = <1>;
108 spi-tx-bus-width = <1>;
109 spi-rx-bus-width = <4>;
110 spi-max-frequency = <108000000>; /* Based on DC1 spec */
111 partition@qspi-fsbl-uboot { /* for testing purpose */
112 label = "qspi-fsbl-uboot";
113 reg = <0x0 0x100000>;
115 partition@qspi-linux { /* for testing purpose */
116 label = "qspi-linux";
117 reg = <0x100000 0x500000>;
119 partition@qspi-device-tree { /* for testing purpose */
120 label = "qspi-device-tree";
121 reg = <0x600000 0x20000>;
123 partition@qspi-rootfs { /* for testing purpose */
124 label = "qspi-rootfs";
125 reg = <0x620000 0x5E0000>;
136 /* SATA phy OOB timing settings */
137 ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
138 ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
139 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
140 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
141 ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
142 ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
143 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
144 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
154 /* SD1 with level shifter */
158 * This property should be removed for supporting UHS mode
168 /* ULPI SMSC USB3320 */
182 &zynqmp_dp_snd_pcm0 {
186 &zynqmp_dp_snd_pcm1 {
190 &zynqmp_dp_snd_card0 {
194 &zynqmp_dp_snd_codec0 {