arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts

   1 /*
   2  * dts file for Xilinx ZynqMP zc1751-xm015-dc1
   3  *
   4  * (C) Copyright 2015, Xilinx, Inc.
   5  *
   6  * Michal Simek <michal.simek@xilinx.com>
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 /dts-v1/;
  12
  13 #include "zynqmp.dtsi"
  14 #include "zynqmp-clk.dtsi"
  15
  16 / {
  17         model = "ZynqMP zc1751-xm015-dc1 RevA";
  18         compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
  19
  20         aliases {
  21                 ethernet0 = &gem3;
  22                 gpio0 = &gpio;
  23                 i2c0 = &i2c1;
  24                 mmc0 = &sdhci0;
  25                 mmc1 = &sdhci1;
  26                 rtc0 = &rtc;
  27                 serial0 = &uart0;
  28                 spi0 = &qspi;
  29                 usb0 = &usb0;
  30         };
  31
  32         chosen {
  33                 bootargs = "earlycon";
  34                 stdout-path = "serial0:115200n8";
  35         };
  36
  37         memory@0 {
  38                 device_type = "memory";
  39                 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
  40         };
  41 };
  42
  43 /* fpd_dma clk 667MHz, lpd_dma 500MHz */
  44 &fpd_dma_chan1 {
  45         status = "okay";
  46         xlnx,include-sg; /* for testing purpose */
  47         xlnx,overfetch; /* for testing purpose */
  48         xlnx,ratectrl = <0>; /* for testing purpose */
  49         xlnx,src-issue = <31>;
  50 };
  51
  52 &fpd_dma_chan2 {
  53         status = "okay";
  54         xlnx,ratectrl = <100>; /* for testing purpose */
  55         xlnx,src-issue = <4>; /* for testing purpose */
  56 };
  57
  58 &fpd_dma_chan3 {
  59         status = "okay";
  60 };
  61
  62 &fpd_dma_chan4 {
  63         status = "okay";
  64         xlnx,include-sg; /* for testing purpose */
  65 };
  66
  67 &fpd_dma_chan5 {
  68         status = "okay";
  69 };
  70
  71 &fpd_dma_chan6 {
  72         status = "okay";
  73         xlnx,include-sg; /* for testing purpose */
  74 };
  75
  76 &fpd_dma_chan7 {
  77         status = "okay";
  78 };
  79
  80 &fpd_dma_chan8 {
  81         status = "okay";
  82         xlnx,include-sg; /* for testing purpose */
  83 };
  84
  85 &gem3 {
  86         status = "okay";
  87         phy-handle = <&phy0>;
  88         phy-mode = "rgmii-id";
  89         phy0: phy@0 {
  90                 reg = <0>;
  91         };
  92 };
  93
  94 &gpio {
  95         status = "okay";
  96 };
  97
  98 &gpu {
  99         status = "okay";
 100 };
 101
 102 &i2c1 {
 103         status = "okay";
 104         clock-frequency = <400000>;
 105         eeprom@55 {
 106                 compatible = "at,24c64"; /* 24AA64 */
 107                 reg = <0x55>;
 108         };
 109 };
 110
 111 &qspi {
 112         status = "okay";
 113         flash@0 {
 114                 compatible = "m25p80"; /* Micron MT25QU512ABB8ESF */
 115                 #address-cells = <1>;
 116                 #size-cells = <1>;
 117                 reg = <0x0>;
 118                 spi-tx-bus-width = <1>;
 119                 spi-rx-bus-width = <4>;
 120                 spi-max-frequency = <108000000>; /* Based on DC1 spec */
 121                 partition@qspi-fsbl-uboot { /* for testing purpose */
 122                         label = "qspi-fsbl-uboot";
 123                         reg = <0x0 0x100000>;
 124                 };
 125                 partition@qspi-linux { /* for testing purpose */
 126                         label = "qspi-linux";
 127                         reg = <0x100000 0x500000>;
 128                 };
 129                 partition@qspi-device-tree { /* for testing purpose */
 130                         label = "qspi-device-tree";
 131                         reg = <0x600000 0x20000>;
 132                 };
 133                 partition@qspi-rootfs { /* for testing purpose */
 134                         label = "qspi-rootfs";
 135                         reg = <0x620000 0x5E0000>;
 136                 };
 137         };
 138 };
 139
 140 &rtc {
 141         status = "okay";
 142 };
 143
 144 &sata {
 145         status = "okay";
 146         /* SATA phy OOB timing settings */
 147         ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
 148         ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
 149         ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 150         ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 151         ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
 152         ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
 153         ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 154         ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 155 };
 156
 157 /* eMMC */
 158 &sdhci0 {
 159         status = "okay";
 160         bus-width = <8>;
 161         xlnx,mio_bank = <0>;
 162 };
 163
 164 /* SD1 with level shifter */
 165 &sdhci1 {
 166         status = "okay";
 167         no-1-8-v;       /* for 1.0 silicon */
 168         xlnx,mio_bank = <1>;
 169 };
 170
 171 &uart0 {
 172         status = "okay";
 173 };
 174
 175 /* ULPI SMSC USB3320 */
 176 &usb0 {
 177         status = "okay";
 178 };
 179
 180 &dwc3_0 {
 181         status = "okay";
 182         dr_mode = "host";
 183 };
 184
 185 &xilinx_drm {
 186         status = "okay";
 187 };
 188
 189 &xlnx_dp {
 190         status = "okay";
 191 };
 192
 193 &xlnx_dp_sub {
 194         status = "okay";
 195         xlnx,vid-clk-pl;
 196 };
 197
 198 &xlnx_dp_snd_pcm0 {
 199         status = "okay";
 200 };
 201
 202 &xlnx_dp_snd_pcm1 {
 203         status = "okay";
 204 };
 205
 206 &xlnx_dp_snd_card {
 207         status = "okay";
 208 };
 209
 210 &xlnx_dp_snd_codec0 {
 211         status = "okay";
 212 };
 213
 214 &xlnx_dpdma {
 215         status = "okay";
 216 };