1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP ZC1232
5 * (C) Copyright 2017 - 2020, Xilinx, Inc.
7 * Michal Simek <michal.simek@xilinx.com>
12 #include "zynqmp.dtsi"
13 #include "zynqmp-clk-ccf.dtsi"
14 #include <dt-bindings/phy/phy.h>
17 model = "ZynqMP ZC1232 RevA";
18 compatible = "xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232", "xlnx,zynqmp";
27 bootargs = "earlycon";
28 stdout-path = "serial0:115200n8";
32 device_type = "memory";
33 reg = <0x0 0x0 0x0 0x80000000>;
44 compatible = "m25p80", "jedec,spi-nor"; /* 32MB FIXME */
48 spi-tx-bus-width = <1>;
49 spi-rx-bus-width = <4>;
50 spi-max-frequency = <108000000>; /* Based on DC1 spec */
51 partition@0 { /* for testing purpose */
52 label = "qspi-fsbl-uboot";
55 partition@100000 { /* for testing purpose */
57 reg = <0x100000 0x500000>;
59 partition@600000 { /* for testing purpose */
60 label = "qspi-device-tree";
61 reg = <0x600000 0x20000>;
63 partition@620000 { /* for testing purpose */
64 label = "qspi-rootfs";
65 reg = <0x620000 0x5E0000>;
72 /* SATA OOB timing settings */
73 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
74 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
75 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
76 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
77 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
78 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
79 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
80 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
81 phy-names = "sata-phy";
82 phys = <&lane0 PHY_TYPE_SATA 0 0 125000000>, <&lane1 PHY_TYPE_SATA 1 1 125000000>;