arch/arm/dts/zynqmp-sm-k26-revA.dts

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * dts file for Xilinx ZynqMP SM-K26 rev1/B/A
   4  *
   5  * (C) Copyright 2020 - 2021, Xilinx, Inc.
   6  *
   7  * Michal Simek <michal.simek@xilinx.com>
   8  */
   9
  10 /dts-v1/;
  11
  12 #include "zynqmp.dtsi"
  13 #include "zynqmp-clk-ccf.dtsi"
  14 #include <dt-bindings/input/input.h>
  15 #include <dt-bindings/gpio/gpio.h>
  16 #include <dt-bindings/phy/phy.h>
  17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
  18
  19 / {
  20         model = "ZynqMP SM-K26 Rev1/B/A";
  21         compatible = "xlnx,zynqmp-sm-k26-rev1", "xlnx,zynqmp-sm-k26-revB",
  22                      "xlnx,zynqmp-sm-k26-revA", "xlnx,zynqmp-sm-k26",
  23                      "xlnx,zynqmp";
  24
  25         aliases {
  26                 i2c0 = &i2c0;
  27                 i2c1 = &i2c1;
  28                 mmc0 = &sdhci0;
  29                 mmc1 = &sdhci1;
  30                 nvmem0 = &eeprom;
  31                 nvmem1 = &eeprom_cc;
  32                 rtc0 = &rtc;
  33                 serial0 = &uart0;
  34                 serial1 = &uart1;
  35                 serial2 = &dcc;
  36                 spi0 = &qspi;
  37                 spi1 = &spi0;
  38                 spi2 = &spi1;
  39                 usb0 = &usb0;
  40                 usb1 = &usb1;
  41         };
  42
  43         chosen {
  44                 bootargs = "earlycon";
  45                 stdout-path = "serial1:115200n8";
  46         };
  47
  48         memory@0 {
  49                 device_type = "memory"; /* 4GB */
  50                 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
  51         };
  52
  53         gpio-keys {
  54                 compatible = "gpio-keys";
  55                 autorepeat;
  56                 fwuen {
  57                         label = "fwuen";
  58                         gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
  59                 };
  60         };
  61
  62         leds {
  63                 compatible = "gpio-leds";
  64                 ds35-led {
  65                         label = "heartbeat";
  66                         gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;
  67                         linux,default-trigger = "heartbeat";
  68                 };
  69
  70                 ds36-led {
  71                         label = "vbus_det";
  72                         gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;
  73                         default-state = "on";
  74                 };
  75         };
  76
  77         ams {
  78                 compatible = "iio-hwmon";
  79                 io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,
  80                         <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,
  81                         <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,
  82                         <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>,
  83                         <&xilinx_ams 12>, <&xilinx_ams 13>, <&xilinx_ams 14>,
  84                         <&xilinx_ams 15>, <&xilinx_ams 16>, <&xilinx_ams 17>,
  85                         <&xilinx_ams 18>, <&xilinx_ams 19>, <&xilinx_ams 20>,
  86                         <&xilinx_ams 21>, <&xilinx_ams 22>, <&xilinx_ams 23>,
  87                         <&xilinx_ams 24>, <&xilinx_ams 25>, <&xilinx_ams 26>,
  88                         <&xilinx_ams 27>, <&xilinx_ams 28>, <&xilinx_ams 29>;
  89         };
  90 };
  91
  92 &uart1 { /* MIO36/MIO37 */
  93         status = "okay";
  94 };
  95
  96 &pinctrl0 {
  97         status = "okay";
  98         pinctrl_sdhci0_default: sdhci0-default {
  99                 conf {
 100                         groups = "sdio0_0_grp";
 101                         slew-rate = <SLEW_RATE_SLOW>;
 102                         power-source = <IO_STANDARD_LVCMOS18>;
 103                         bias-disable;
 104                 };
 105
 106                 mux {
 107                         groups = "sdio0_0_grp";
 108                         function = "sdio0";
 109                 };
 110         };
 111 };
 112
 113 &qspi { /* MIO 0-5 - U143 */
 114         status = "okay";
 115         flash@0 { /* MT25QU512A */
 116                 compatible = "mt25qu512a", "jedec,spi-nor"; /* 64MB */
 117                 #address-cells = <1>;
 118                 #size-cells = <1>;
 119                 reg = <0>;
 120                 spi-tx-bus-width = <1>;
 121                 spi-rx-bus-width = <4>;
 122                 spi-max-frequency = <40000000>; /* 40MHz */
 123                 partition@0 {
 124                         label = "Image Selector";
 125                         reg = <0x0 0x80000>; /* 512KB */
 126                         read-only;
 127                         lock;
 128                 };
 129                 partition@80000 {
 130                         label = "Image Selector Golden";
 131                         reg = <0x80000 0x80000>; /* 512KB */
 132                         read-only;
 133                         lock;
 134                 };
 135                 partition@100000 {
 136                         label = "Persistent Register";
 137                         reg = <0x100000 0x20000>; /* 128KB */
 138                 };
 139                 partition@120000 {
 140                         label = "Persistent Register Backup";
 141                         reg = <0x120000 0x20000>; /* 128KB */
 142                 };
 143                 partition@140000 {
 144                         label = "Open_1";
 145                         reg = <0x140000 0xC0000>; /* 768KB */
 146                 };
 147                 partition@200000 {
 148                         label = "Image A (FSBL, PMU, ATF, U-Boot)";
 149                         reg = <0x200000 0xD00000>; /* 13MB */
 150                 };
 151                 partition@f00000 {
 152                         label = "ImgSel Image A Catch";
 153                         reg = <0xF00000 0x80000>; /* 512KB */
 154                         read-only;
 155                         lock;
 156                 };
 157                 partition@f80000 {
 158                         label = "Image B (FSBL, PMU, ATF, U-Boot)";
 159                         reg = <0xF80000 0xD00000>; /* 13MB */
 160                 };
 161                 partition@1c80000 {
 162                         label = "ImgSel Image B Catch";
 163                         reg = <0x1C80000 0x80000>; /* 512KB */
 164                         read-only;
 165                         lock;
 166                 };
 167                 partition@1d00000 {
 168                         label = "Open_2";
 169                         reg = <0x1D00000 0x100000>; /* 1MB */
 170                 };
 171                 partition@1e00000 {
 172                         label = "Recovery Image";
 173                         reg = <0x1E00000 0x200000>; /* 2MB */
 174                         read-only;
 175                         lock;
 176                 };
 177                 partition@2000000 {
 178                         label = "Recovery Image Backup";
 179                         reg = <0x2000000 0x200000>; /* 2MB */
 180                         read-only;
 181                         lock;
 182                 };
 183                 partition@2200000 {
 184                         label = "U-Boot storage variables";
 185                         reg = <0x2200000 0x20000>; /* 128KB */
 186                 };
 187                 partition@2220000 {
 188                         label = "U-Boot storage variables backup";
 189                         reg = <0x2220000 0x20000>; /* 128KB */
 190                 };
 191                 partition@2240000 {
 192                         label = "SHA256";
 193                         reg = <0x2240000 0x10000>; /* 256B but 64KB sector */
 194                         read-only;
 195                         lock;
 196                 };
 197                 partition@2250000 {
 198                         label = "User";
 199                         reg = <0x2250000 0x1db0000>; /* 29.5 MB */
 200                 };
 201         };
 202 };
 203
 204 &sdhci0 { /* MIO13-23 - 16GB emmc MTFC16GAPALBH-IT - U133A */
 205         status = "okay";
 206         pinctrl-names = "default";
 207         pinctrl-0 = <&pinctrl_sdhci0_default>;
 208         non-removable;
 209         disable-wp;
 210         bus-width = <8>;
 211         xlnx,mio-bank = <0>;
 212         assigned-clock-rates = <187498123>;
 213 };
 214
 215 &spi1 { /* MIO6, 9-11 */
 216         status = "okay";
 217         label = "TPM";
 218         num-cs = <1>;
 219         tpm@0 { /* slm9670 - U144 */
 220                 compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
 221                 reg = <0>;
 222                 spi-max-frequency = <18500000>;
 223         };
 224 };
 225
 226 &i2c1 {
 227         status = "okay";
 228         u-boot,dm-pre-reloc;
 229         clock-frequency = <400000>;
 230         scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
 231         sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
 232
 233         eeprom: eeprom@50 { /* u46 - also at address 0x58 */
 234                 u-boot,dm-pre-reloc;
 235                 compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */
 236                 reg = <0x50>;
 237                 /* WP pin EE_WP_EN connected to slg7x644092@68 */
 238         };
 239
 240         eeprom_cc: eeprom@51 { /* required by spec - also at address 0x59 */
 241                 u-boot,dm-pre-reloc;
 242                 compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */
 243                 reg = <0x51>;
 244         };
 245
 246         /* da9062@30 - u170 - also at address 0x31 */
 247         /* da9131@33 - u167 */
 248         da9131: pmic@33 {
 249                 compatible = "dlg,da9131";
 250                 reg = <0x33>;
 251                 regulators {
 252                         da9131_buck1: buck1 {
 253                                 regulator-name = "da9131_buck1";
 254                                 regulator-boot-on;
 255                                 regulator-always-on;
 256                         };
 257                         da9131_buck2: buck2 {
 258                                 regulator-name = "da9131_buck2";
 259                                 regulator-boot-on;
 260                                 regulator-always-on;
 261                         };
 262                 };
 263         };
 264
 265         /* da9130@32 - u166 */
 266         da9130: pmic@32 {
 267                 compatible = "dlg,da9130";
 268                 reg = <0x32>;
 269                 regulators {
 270                         da9130_buck1: buck1 {
 271                                 regulator-name = "da9130_buck1";
 272                                 regulator-boot-on;
 273                                 regulator-always-on;
 274                         };
 275                 };
 276         };
 277
 278         /* slg7x644091@70 - u168 NOT accessible due to address conflict with stdp4320 */
 279         /*
 280          * stdp4320 - u27 FW has below two issues to be fixed in next board revision.
 281          * Device acknowledging to addresses 0x5C, 0x5D, 0x70, 0x72, 0x76.
 282          * Address conflict with slg7x644091@70 making both the devices NOT accessible.
 283          * With the FW fix, stdp4320 should respond to address 0x73 only.
 284          */
 285         /* slg7x644092@68 - u169 */
 286         /* Also connected via JA1C as C23/C24 */
 287 };
 288
 289 &gpio {
 290         status = "okay";
 291         gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */
 292                           "QSPI_CS_B", "SPI_CLK", "LED1", "LED2", "SPI_CS_B", /* 5 - 9 */
 293                           "SPI_MISO", "SPI_MOSI", "FWUEN", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */
 294                           "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */
 295                           "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST", "I2C1_SCL", /* 20 - 24 */
 296                           "I2C1_SDA", "", "", "", "", /* 25 - 29 */
 297                           "", "", "", "", "", /* 30 - 34 */
 298                           "", "", "", "", "", /* 35 - 39 */
 299                           "", "", "", "", "", /* 40 - 44 */
 300                           "", "", "", "", "", /* 45 - 49 */
 301                           "", "", "", "", "", /* 50 - 54 */
 302                           "", "", "", "", "", /* 55 - 59 */
 303                           "", "", "", "", "", /* 60 - 64 */
 304                           "", "", "", "", "", /* 65 - 69 */
 305                           "", "", "", "", "", /* 70 - 74 */
 306                           "", "", "", /* 75 - 77, MIO end and EMIO start */
 307                           "", "", /* 78 - 79 */
 308                           "", "", "", "", "", /* 80 - 84 */
 309                           "", "", "", "", "", /* 85 - 89 */
 310                           "", "", "", "", "", /* 90 - 94 */
 311                           "", "", "", "", "", /* 95 - 99 */
 312                           "", "", "", "", "", /* 100 - 104 */
 313                           "", "", "", "", "", /* 105 - 109 */
 314                           "", "", "", "", "", /* 110 - 114 */
 315                           "", "", "", "", "", /* 115 - 119 */
 316                           "", "", "", "", "", /* 120 - 124 */
 317                           "", "", "", "", "", /* 125 - 129 */
 318                           "", "", "", "", "", /* 130 - 134 */
 319                           "", "", "", "", "", /* 135 - 139 */
 320                           "", "", "", "", "", /* 140 - 144 */
 321                           "", "", "", "", "", /* 145 - 149 */
 322                           "", "", "", "", "", /* 150 - 154 */
 323                           "", "", "", "", "", /* 155 - 159 */
 324                           "", "", "", "", "", /* 160 - 164 */
 325                           "", "", "", "", "", /* 165 - 169 */
 326                           "", "", "", ""; /* 170 - 174 */
 327 };
 328
 329 &xilinx_ams {
 330         status = "okay";
 331 };
 332
 333 &ams_ps {
 334         status = "okay";
 335 };
 336
 337 &ams_pl {
 338         status = "okay";
 339 };
 340
 341 &zynqmp_dpsub {
 342         status = "okay";
 343 };