arch/arm/dts/zynqmp-sck-kv-g-revB.dts

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * dts file for KV260 revA Carrier Card
   4  *
   5  * (C) Copyright 2020 - 2021, Xilinx, Inc.
   6  *
   7  * Michal Simek <michal.simek@amd.com>
   8  */
   9
  10 #include <dt-bindings/gpio/gpio.h>
  11 #include <dt-bindings/net/ti-dp83867.h>
  12 #include <dt-bindings/phy/phy.h>
  13 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
  14
  15 /dts-v1/;
  16 /plugin/;
  17
  18 &{/} {
  19         compatible = "xlnx,zynqmp-sk-kv260-rev2",
  20                      "xlnx,zynqmp-sk-kv260-rev1",
  21                      "xlnx,zynqmp-sk-kv260-revB",
  22                      "xlnx,zynqmp-sk-kv260", "xlnx,zynqmp";
  23         model = "ZynqMP KV260 revB";
  24 };
  25
  26 &i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */
  27         #address-cells = <1>;
  28         #size-cells = <0>;
  29         pinctrl-names = "default", "gpio";
  30         pinctrl-0 = <&pinctrl_i2c1_default>;
  31         pinctrl-1 = <&pinctrl_i2c1_gpio>;
  32         scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
  33         sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
  34
  35         u14: ina260@40 { /* u14 */
  36                 compatible = "ti,ina260";
  37                 #io-channel-cells = <1>;
  38                 label = "ina260-u14";
  39                 reg = <0x40>;
  40         };
  41         /* u43 - 0x2d - USB hub */
  42         /* u27 - 0xe0 - STDP4320 DP/HDMI splitter */
  43 };
  44
  45 &amba {
  46         ina260-u14 {
  47                 compatible = "iio-hwmon";
  48                 io-channels = <&u14 0>, <&u14 1>, <&u14 2>;
  49         };
  50
  51         si5332_0: si5332_0 { /* u17 */
  52                 compatible = "fixed-clock";
  53                 #clock-cells = <0>;
  54                 clock-frequency = <125000000>;
  55         };
  56
  57         si5332_1: si5332_1 { /* u17 */
  58                 compatible = "fixed-clock";
  59                 #clock-cells = <0>;
  60                 clock-frequency = <25000000>;
  61         };
  62
  63         si5332_2: si5332_2 { /* u17 */
  64                 compatible = "fixed-clock";
  65                 #clock-cells = <0>;
  66                 clock-frequency = <48000000>;
  67         };
  68
  69         si5332_3: si5332_3 { /* u17 */
  70                 compatible = "fixed-clock";
  71                 #clock-cells = <0>;
  72                 clock-frequency = <24000000>;
  73         };
  74
  75         si5332_4: si5332_4 { /* u17 */
  76                 compatible = "fixed-clock";
  77                 #clock-cells = <0>;
  78                 clock-frequency = <26000000>;
  79         };
  80
  81         si5332_5: si5332_5 { /* u17 */
  82                 compatible = "fixed-clock";
  83                 #clock-cells = <0>;
  84                 clock-frequency = <27000000>;
  85         };
  86 };
  87
  88 /* DP/USB 3.0 */
  89 &psgtr {
  90         status = "okay";
  91         /* pcie, usb3, sata */
  92         clocks = <&si5332_5>, <&si5332_4>, <&si5332_0>;
  93         clock-names = "ref0", "ref1", "ref2";
  94 };
  95
  96 &zynqmp_dpsub {
  97         status = "okay";
  98         phy-names = "dp-phy0", "dp-phy1";
  99         phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;
 100         assigned-clock-rates = <27000000>, <25000000>, <300000000>;
 101 };
 102
 103 &zynqmp_dpdma {
 104         status = "okay";
 105         assigned-clock-rates = <600000000>;
 106 };
 107
 108 &usb0 {
 109         status = "okay";
 110         pinctrl-names = "default";
 111         pinctrl-0 = <&pinctrl_usb0_default>;
 112         phy-names = "usb3-phy";
 113         phys = <&psgtr 2 PHY_TYPE_USB3 0 1>;
 114         assigned-clock-rates = <250000000>, <20000000>;
 115
 116         usb5744: usb-hub { /* u43 */
 117                 status = "okay";
 118                 compatible = "microchip,usb5744";
 119                 i2c-bus = <&i2c1>;
 120                 reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
 121         };
 122 };
 123
 124 &dwc3_0 {
 125         status = "okay";
 126         dr_mode = "host";
 127         snps,usb3_lpm_capable;
 128         maximum-speed = "super-speed";
 129 };
 130
 131 &sdhci1 { /* on CC with tuned parameters */
 132         status = "okay";
 133         pinctrl-names = "default";
 134         pinctrl-0 = <&pinctrl_sdhci1_default>;
 135         /*
 136          * SD 3.0 requires level shifter and this property
 137          * should be removed if the board has level shifter and
 138          * need to work in UHS mode
 139          */
 140         no-1-8-v;
 141         disable-wp;
 142         xlnx,mio-bank = <1>;
 143         clk-phase-sd-hs = <126>, <60>;
 144         clk-phase-uhs-sdr25 = <120>, <60>;
 145         clk-phase-uhs-ddr50 = <126>, <48>;
 146         assigned-clock-rates = <187498123>;
 147         bus-width = <8>;
 148 };
 149
 150 &gem3 {
 151         status = "okay";
 152         pinctrl-names = "default";
 153         pinctrl-0 = <&pinctrl_gem3_default>;
 154         phy-handle = <&phy0>;
 155         phy-mode = "rgmii-id";
 156         assigned-clock-rates = <250000000>;
 157
 158         mdio: mdio {
 159                 #address-cells = <1>;
 160                 #size-cells = <0>;
 161
 162                 phy0: ethernet-phy@1 {
 163                         #phy-cells = <1>;
 164                         reg = <1>;
 165                         compatible = "ethernet-phy-id2000.a231";
 166                         ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
 167                         ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
 168                         ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
 169                         ti,dp83867-rxctrl-strap-quirk;
 170                         reset-assert-us = <100>;
 171                         reset-deassert-us = <280>;
 172                         reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
 173                 };
 174         };
 175 };
 176
 177 &pinctrl0 {
 178         status = "okay";
 179
 180         pinctrl_uart1_default: uart1-default {
 181                 conf {
 182                         groups = "uart1_9_grp";
 183                         slew-rate = <SLEW_RATE_SLOW>;
 184                         power-source = <IO_STANDARD_LVCMOS18>;
 185                         drive-strength = <12>;
 186                 };
 187
 188                 conf-rx {
 189                         pins = "MIO37";
 190                         bias-high-impedance;
 191                 };
 192
 193                 conf-tx {
 194                         pins = "MIO36";
 195                         bias-disable;
 196                 };
 197
 198                 mux {
 199                         groups = "uart1_9_grp";
 200                         function = "uart1";
 201                 };
 202         };
 203
 204         pinctrl_i2c1_default: i2c1-default {
 205                 conf {
 206                         groups = "i2c1_6_grp";
 207                         bias-pull-up;
 208                         slew-rate = <SLEW_RATE_SLOW>;
 209                         power-source = <IO_STANDARD_LVCMOS18>;
 210                 };
 211
 212                 mux {
 213                         groups = "i2c1_6_grp";
 214                         function = "i2c1";
 215                 };
 216         };
 217
 218         pinctrl_i2c1_gpio: i2c1-gpio {
 219                 conf {
 220                         groups = "gpio0_24_grp", "gpio0_25_grp";
 221                         slew-rate = <SLEW_RATE_SLOW>;
 222                         power-source = <IO_STANDARD_LVCMOS18>;
 223                 };
 224
 225                 mux {
 226                         groups = "gpio0_24_grp", "gpio0_25_grp";
 227                         function = "gpio0";
 228                 };
 229         };
 230
 231         pinctrl_gem3_default: gem3-default {
 232                 conf {
 233                         groups = "ethernet3_0_grp";
 234                         slew-rate = <SLEW_RATE_SLOW>;
 235                         power-source = <IO_STANDARD_LVCMOS18>;
 236                 };
 237
 238                 conf-rx {
 239                         pins = "MIO70", "MIO72", "MIO74";
 240                         bias-high-impedance;
 241                         low-power-disable;
 242                 };
 243
 244                 conf-bootstrap {
 245                         pins = "MIO71", "MIO73", "MIO75";
 246                         bias-disable;
 247                         low-power-disable;
 248                 };
 249
 250                 conf-tx {
 251                         pins = "MIO64", "MIO65", "MIO66",
 252                                 "MIO67", "MIO68", "MIO69";
 253                         bias-disable;
 254                         low-power-enable;
 255                 };
 256
 257                 conf-mdio {
 258                         groups = "mdio3_0_grp";
 259                         slew-rate = <SLEW_RATE_SLOW>;
 260                         power-source = <IO_STANDARD_LVCMOS18>;
 261                         bias-disable;
 262                 };
 263
 264                 mux-mdio {
 265                         function = "mdio3";
 266                         groups = "mdio3_0_grp";
 267                 };
 268
 269                 mux {
 270                         function = "ethernet3";
 271                         groups = "ethernet3_0_grp";
 272                 };
 273         };
 274
 275         pinctrl_usb0_default: usb0-default {
 276                 conf {
 277                         groups = "usb0_0_grp";
 278                         power-source = <IO_STANDARD_LVCMOS18>;
 279                 };
 280
 281                 conf-rx {
 282                         pins = "MIO52", "MIO53", "MIO55";
 283                         bias-high-impedance;
 284                         drive-strength = <12>;
 285                         slew-rate = <SLEW_RATE_FAST>;
 286                 };
 287
 288                 conf-tx {
 289                         pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
 290                         "MIO60", "MIO61", "MIO62", "MIO63";
 291                         bias-disable;
 292                         drive-strength = <4>;
 293                         slew-rate = <SLEW_RATE_SLOW>;
 294                 };
 295
 296                 mux {
 297                         groups = "usb0_0_grp";
 298                         function = "usb0";
 299                 };
 300         };
 301
 302         pinctrl_sdhci1_default: sdhci1-default {
 303                 conf {
 304                         groups = "sdio1_0_grp";
 305                         slew-rate = <SLEW_RATE_SLOW>;
 306                         power-source = <IO_STANDARD_LVCMOS18>;
 307                         bias-disable;
 308                 };
 309
 310                 conf-cd {
 311                         groups = "sdio1_cd_0_grp";
 312                         bias-high-impedance;
 313                         bias-pull-up;
 314                         slew-rate = <SLEW_RATE_SLOW>;
 315                         power-source = <IO_STANDARD_LVCMOS18>;
 316                 };
 317
 318                 mux-cd {
 319                         groups = "sdio1_cd_0_grp";
 320                         function = "sdio1_cd";
 321                 };
 322
 323                 mux {
 324                         groups = "sdio1_0_grp";
 325                         function = "sdio1";
 326                 };
 327         };
 328 };
 329
 330 &uart1 {
 331         status = "okay";
 332         pinctrl-names = "default";
 333         pinctrl-0 = <&pinctrl_uart1_default>;
 334 };