arch/arm/dts/zynqmp-sck-kv-g-revB.dts

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * dts file for KV260 revA Carrier Card
   4  *
   5  * (C) Copyright 2020 - 2021, Xilinx, Inc.
   6  *
   7  * Michal Simek <michal.simek@amd.com>
   8  */
   9
  10 #include <dt-bindings/gpio/gpio.h>
  11 #include <dt-bindings/net/ti-dp83867.h>
  12 #include <dt-bindings/phy/phy.h>
  13 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
  14
  15 /dts-v1/;
  16 /plugin/;
  17
  18 &{/} {
  19         compatible = "xlnx,zynqmp-sk-kv260-rev1",
  20                      "xlnx,zynqmp-sk-kv260-revB",
  21                      "xlnx,zynqmp-sk-kv260", "xlnx,zynqmp";
  22         model = "ZynqMP KV260 revB";
  23 };
  24
  25 &i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */
  26         #address-cells = <1>;
  27         #size-cells = <0>;
  28         pinctrl-names = "default", "gpio";
  29         pinctrl-0 = <&pinctrl_i2c1_default>;
  30         pinctrl-1 = <&pinctrl_i2c1_gpio>;
  31         scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
  32         sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
  33
  34         u14: ina260@40 { /* u14 */
  35                 compatible = "ti,ina260";
  36                 #io-channel-cells = <1>;
  37                 label = "ina260-u14";
  38                 reg = <0x40>;
  39         };
  40         /* u43 - 0x2d - USB hub */
  41         /* u27 - 0xe0 - STDP4320 DP/HDMI splitter */
  42 };
  43
  44 &amba {
  45         ina260-u14 {
  46                 compatible = "iio-hwmon";
  47                 io-channels = <&u14 0>, <&u14 1>, <&u14 2>;
  48         };
  49
  50         si5332_0: si5332_0 { /* u17 */
  51                 compatible = "fixed-clock";
  52                 #clock-cells = <0>;
  53                 clock-frequency = <125000000>;
  54         };
  55
  56         si5332_1: si5332_1 { /* u17 */
  57                 compatible = "fixed-clock";
  58                 #clock-cells = <0>;
  59                 clock-frequency = <25000000>;
  60         };
  61
  62         si5332_2: si5332_2 { /* u17 */
  63                 compatible = "fixed-clock";
  64                 #clock-cells = <0>;
  65                 clock-frequency = <48000000>;
  66         };
  67
  68         si5332_3: si5332_3 { /* u17 */
  69                 compatible = "fixed-clock";
  70                 #clock-cells = <0>;
  71                 clock-frequency = <24000000>;
  72         };
  73
  74         si5332_4: si5332_4 { /* u17 */
  75                 compatible = "fixed-clock";
  76                 #clock-cells = <0>;
  77                 clock-frequency = <26000000>;
  78         };
  79
  80         si5332_5: si5332_5 { /* u17 */
  81                 compatible = "fixed-clock";
  82                 #clock-cells = <0>;
  83                 clock-frequency = <27000000>;
  84         };
  85 };
  86
  87 /* DP/USB 3.0 */
  88 &psgtr {
  89         status = "okay";
  90         /* pcie, usb3, sata */
  91         clocks = <&si5332_5>, <&si5332_4>, <&si5332_0>;
  92         clock-names = "ref0", "ref1", "ref2";
  93 };
  94
  95 &zynqmp_dpsub {
  96         status = "okay";
  97         phy-names = "dp-phy0", "dp-phy1";
  98         phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;
  99         assigned-clock-rates = <27000000>, <25000000>, <300000000>;
 100 };
 101
 102 &zynqmp_dpdma {
 103         status = "okay";
 104         assigned-clock-rates = <600000000>;
 105 };
 106
 107 &usb0 {
 108         status = "okay";
 109         pinctrl-names = "default";
 110         pinctrl-0 = <&pinctrl_usb0_default>;
 111         phy-names = "usb3-phy";
 112         phys = <&psgtr 2 PHY_TYPE_USB3 0 1>;
 113         assigned-clock-rates = <250000000>, <20000000>;
 114
 115         usb5744: usb-hub { /* u43 */
 116                 status = "okay";
 117                 compatible = "microchip,usb5744";
 118                 i2c-bus = <&i2c1>;
 119                 reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
 120         };
 121 };
 122
 123 &dwc3_0 {
 124         status = "okay";
 125         dr_mode = "host";
 126         snps,usb3_lpm_capable;
 127         maximum-speed = "super-speed";
 128 };
 129
 130 &sdhci1 { /* on CC with tuned parameters */
 131         status = "okay";
 132         pinctrl-names = "default";
 133         pinctrl-0 = <&pinctrl_sdhci1_default>;
 134         /*
 135          * SD 3.0 requires level shifter and this property
 136          * should be removed if the board has level shifter and
 137          * need to work in UHS mode
 138          */
 139         no-1-8-v;
 140         disable-wp;
 141         xlnx,mio-bank = <1>;
 142         clk-phase-sd-hs = <126>, <60>;
 143         clk-phase-uhs-sdr25 = <120>, <60>;
 144         clk-phase-uhs-ddr50 = <126>, <48>;
 145         assigned-clock-rates = <187498123>;
 146         bus-width = <8>;
 147 };
 148
 149 &gem3 {
 150         status = "okay";
 151         pinctrl-names = "default";
 152         pinctrl-0 = <&pinctrl_gem3_default>;
 153         phy-handle = <&phy0>;
 154         phy-mode = "rgmii-id";
 155         assigned-clock-rates = <250000000>;
 156
 157         mdio: mdio {
 158                 #address-cells = <1>;
 159                 #size-cells = <0>;
 160
 161                 phy0: ethernet-phy@1 {
 162                         #phy-cells = <1>;
 163                         reg = <1>;
 164                         compatible = "ethernet-phy-id2000.a231";
 165                         ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
 166                         ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
 167                         ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
 168                         ti,dp83867-rxctrl-strap-quirk;
 169                         reset-assert-us = <100>;
 170                         reset-deassert-us = <280>;
 171                         reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
 172                 };
 173         };
 174 };
 175
 176 &pinctrl0 {
 177         status = "okay";
 178
 179         pinctrl_uart1_default: uart1-default {
 180                 conf {
 181                         groups = "uart1_9_grp";
 182                         slew-rate = <SLEW_RATE_SLOW>;
 183                         power-source = <IO_STANDARD_LVCMOS18>;
 184                         drive-strength = <12>;
 185                 };
 186
 187                 conf-rx {
 188                         pins = "MIO37";
 189                         bias-high-impedance;
 190                 };
 191
 192                 conf-tx {
 193                         pins = "MIO36";
 194                         bias-disable;
 195                 };
 196
 197                 mux {
 198                         groups = "uart1_9_grp";
 199                         function = "uart1";
 200                 };
 201         };
 202
 203         pinctrl_i2c1_default: i2c1-default {
 204                 conf {
 205                         groups = "i2c1_6_grp";
 206                         bias-pull-up;
 207                         slew-rate = <SLEW_RATE_SLOW>;
 208                         power-source = <IO_STANDARD_LVCMOS18>;
 209                 };
 210
 211                 mux {
 212                         groups = "i2c1_6_grp";
 213                         function = "i2c1";
 214                 };
 215         };
 216
 217         pinctrl_i2c1_gpio: i2c1-gpio {
 218                 conf {
 219                         groups = "gpio0_24_grp", "gpio0_25_grp";
 220                         slew-rate = <SLEW_RATE_SLOW>;
 221                         power-source = <IO_STANDARD_LVCMOS18>;
 222                 };
 223
 224                 mux {
 225                         groups = "gpio0_24_grp", "gpio0_25_grp";
 226                         function = "gpio0";
 227                 };
 228         };
 229
 230         pinctrl_gem3_default: gem3-default {
 231                 conf {
 232                         groups = "ethernet3_0_grp";
 233                         slew-rate = <SLEW_RATE_SLOW>;
 234                         power-source = <IO_STANDARD_LVCMOS18>;
 235                 };
 236
 237                 conf-rx {
 238                         pins = "MIO70", "MIO72", "MIO74";
 239                         bias-high-impedance;
 240                         low-power-disable;
 241                 };
 242
 243                 conf-bootstrap {
 244                         pins = "MIO71", "MIO73", "MIO75";
 245                         bias-disable;
 246                         low-power-disable;
 247                 };
 248
 249                 conf-tx {
 250                         pins = "MIO64", "MIO65", "MIO66",
 251                                 "MIO67", "MIO68", "MIO69";
 252                         bias-disable;
 253                         low-power-enable;
 254                 };
 255
 256                 conf-mdio {
 257                         groups = "mdio3_0_grp";
 258                         slew-rate = <SLEW_RATE_SLOW>;
 259                         power-source = <IO_STANDARD_LVCMOS18>;
 260                         bias-disable;
 261                 };
 262
 263                 mux-mdio {
 264                         function = "mdio3";
 265                         groups = "mdio3_0_grp";
 266                 };
 267
 268                 mux {
 269                         function = "ethernet3";
 270                         groups = "ethernet3_0_grp";
 271                 };
 272         };
 273
 274         pinctrl_usb0_default: usb0-default {
 275                 conf {
 276                         groups = "usb0_0_grp";
 277                         power-source = <IO_STANDARD_LVCMOS18>;
 278                 };
 279
 280                 conf-rx {
 281                         pins = "MIO52", "MIO53", "MIO55";
 282                         bias-high-impedance;
 283                         drive-strength = <12>;
 284                         slew-rate = <SLEW_RATE_FAST>;
 285                 };
 286
 287                 conf-tx {
 288                         pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
 289                         "MIO60", "MIO61", "MIO62", "MIO63";
 290                         bias-disable;
 291                         drive-strength = <4>;
 292                         slew-rate = <SLEW_RATE_SLOW>;
 293                 };
 294
 295                 mux {
 296                         groups = "usb0_0_grp";
 297                         function = "usb0";
 298                 };
 299         };
 300
 301         pinctrl_sdhci1_default: sdhci1-default {
 302                 conf {
 303                         groups = "sdio1_0_grp";
 304                         slew-rate = <SLEW_RATE_SLOW>;
 305                         power-source = <IO_STANDARD_LVCMOS18>;
 306                         bias-disable;
 307                 };
 308
 309                 conf-cd {
 310                         groups = "sdio1_cd_0_grp";
 311                         bias-high-impedance;
 312                         bias-pull-up;
 313                         slew-rate = <SLEW_RATE_SLOW>;
 314                         power-source = <IO_STANDARD_LVCMOS18>;
 315                 };
 316
 317                 mux-cd {
 318                         groups = "sdio1_cd_0_grp";
 319                         function = "sdio1_cd";
 320                 };
 321
 322                 mux {
 323                         groups = "sdio1_0_grp";
 324                         function = "sdio1";
 325                 };
 326         };
 327 };
 328
 329 &uart1 {
 330         status = "okay";
 331         pinctrl-names = "default";
 332         pinctrl-0 = <&pinctrl_uart1_default>;
 333 };