arch/arm/dts/zynqmp-sck-kv-g-revA.dts

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * dts file for KV260 revA Carrier Card
   4  *
   5  * (C) Copyright 2020 - 2021, Xilinx, Inc.
   6  *
   7  * SD level shifter:
   8  * "A" – A01 board un-modified (NXP)
   9  * "Y" – A01 board modified with legacy interposer (Nexperia)
  10  * "Z" – A01 board modified with Diode interposer
  11  *
  12  * Michal Simek <michal.simek@xilinx.com>
  13  */
  14
  15  #include <dt-bindings/gpio/gpio.h>
  16  #include <dt-bindings/net/ti-dp83867.h>
  17  #include <dt-bindings/phy/phy.h>
  18  #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
  19
  20 /dts-v1/;
  21 /plugin/;
  22
  23 &{/} {
  24         compatible = "xlnx,zynqmp-sk-kv260-revA",
  25                      "xlnx,zynqmp-sk-kv260-revY",
  26                      "xlnx,zynqmp-sk-kv260-revZ",
  27                      "xlnx,zynqmp-sk-kv260", "xlnx,zynqmp";
  28 };
  29
  30 &i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */
  31         #address-cells = <1>;
  32         #size-cells = <0>;
  33         pinctrl-names = "default", "gpio";
  34         pinctrl-0 = <&pinctrl_i2c1_default>;
  35         pinctrl-1 = <&pinctrl_i2c1_gpio>;
  36         scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
  37         sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
  38
  39         u14: ina260@40 { /* u14 */
  40                 compatible = "ti,ina260";
  41                 #io-channel-cells = <1>;
  42                 label = "ina260-u14";
  43                 reg = <0x40>;
  44         };
  45         /* u27 - 0xe0 - STDP4320 DP/HDMI splitter */
  46 };
  47
  48 &amba {
  49         ina260-u14 {
  50                 compatible = "iio-hwmon";
  51                 io-channels = <&u14 0>, <&u14 1>, <&u14 2>;
  52         };
  53
  54         si5332_0: si5332_0 { /* u17 */
  55                 compatible = "fixed-clock";
  56                 #clock-cells = <0>;
  57                 clock-frequency = <125000000>;
  58         };
  59
  60         si5332_1: si5332_1 { /* u17 */
  61                 compatible = "fixed-clock";
  62                 #clock-cells = <0>;
  63                 clock-frequency = <25000000>;
  64         };
  65
  66         si5332_2: si5332_2 { /* u17 */
  67                 compatible = "fixed-clock";
  68                 #clock-cells = <0>;
  69                 clock-frequency = <48000000>;
  70         };
  71
  72         si5332_3: si5332_3 { /* u17 */
  73                 compatible = "fixed-clock";
  74                 #clock-cells = <0>;
  75                 clock-frequency = <24000000>;
  76         };
  77
  78         si5332_4: si5332_4 { /* u17 */
  79                 compatible = "fixed-clock";
  80                 #clock-cells = <0>;
  81                 clock-frequency = <26000000>;
  82         };
  83
  84         si5332_5: si5332_5 { /* u17 */
  85                 compatible = "fixed-clock";
  86                 #clock-cells = <0>;
  87                 clock-frequency = <27000000>;
  88         };
  89 };
  90
  91 /* DP/USB 3.0 and SATA */
  92 &psgtr {
  93         status = "okay";
  94         /* pcie, usb3, sata */
  95         clocks = <&si5332_5>, <&si5332_4>, <&si5332_0>;
  96         clock-names = "ref0", "ref1", "ref2";
  97 };
  98
  99 &sata {
 100         status = "okay";
 101         /* SATA OOB timing settings */
 102         ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
 103         ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
 104         ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 105         ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 106         ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
 107         ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
 108         ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 109         ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 110         phy-names = "sata-phy";
 111         phys = <&psgtr 3 PHY_TYPE_SATA 1 2>;
 112 };
 113
 114 &zynqmp_dpsub {
 115         status = "disabled";
 116         phy-names = "dp-phy0", "dp-phy1";
 117         phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;
 118 };
 119
 120 &zynqmp_dpdma {
 121         status = "okay";
 122 };
 123
 124 &usb0 {
 125         status = "okay";
 126         pinctrl-names = "default";
 127         pinctrl-0 = <&pinctrl_usb0_default>;
 128         usbhub: usb5744 { /* u43 */
 129                 compatible = "microchip,usb5744";
 130                 reset-gpios = <&gpio 44 GPIO_ACTIVE_HIGH>;
 131         };
 132 };
 133
 134 &dwc3_0 {
 135         status = "okay";
 136         dr_mode = "host";
 137         snps,usb3_lpm_capable;
 138         phy-names = "usb3-phy";
 139         phys = <&psgtr 2 PHY_TYPE_USB3 0 1>;
 140         maximum-speed = "super-speed";
 141 };
 142
 143 &sdhci1 { /* on CC with tuned parameters */
 144         status = "okay";
 145         pinctrl-names = "default";
 146         pinctrl-0 = <&pinctrl_sdhci1_default>;
 147         /*
 148          * SD 3.0 requires level shifter and this property
 149          * should be removed if the board has level shifter and
 150          * need to work in UHS mode
 151          */
 152         no-1-8-v;
 153         disable-wp;
 154         xlnx,mio-bank = <1>;
 155 };
 156
 157 &gem3 { /* required by spec */
 158         status = "okay";
 159         pinctrl-names = "default";
 160         pinctrl-0 = <&pinctrl_gem3_default>;
 161         phy-handle = <&phy0>;
 162         phy-mode = "rgmii-id";
 163
 164         mdio: mdio {
 165                 #address-cells = <1>;
 166                 #size-cells = <0>;
 167                 reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
 168                 reset-delay-us = <2>;
 169
 170                 phy0: ethernet-phy@1 {
 171                         #phy-cells = <1>;
 172                         reg = <1>;
 173                         ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
 174                         ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
 175                         ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
 176                         ti,dp83867-rxctrl-strap-quirk;
 177                 };
 178         };
 179 };
 180
 181 &pinctrl0 { /* required by spec */
 182         status = "okay";
 183
 184         pinctrl_uart1_default: uart1-default {
 185                 conf {
 186                         groups = "uart1_9_grp";
 187                         slew-rate = <SLEW_RATE_SLOW>;
 188                         power-source = <IO_STANDARD_LVCMOS18>;
 189                         drive-strength = <12>;
 190                 };
 191
 192                 conf-rx {
 193                         pins = "MIO37";
 194                         bias-high-impedance;
 195                 };
 196
 197                 conf-tx {
 198                         pins = "MIO36";
 199                         bias-disable;
 200                 };
 201
 202                 mux {
 203                         groups = "uart1_9_grp";
 204                         function = "uart1";
 205                 };
 206         };
 207
 208         pinctrl_i2c1_default: i2c1-default {
 209                 conf {
 210                         groups = "i2c1_6_grp";
 211                         bias-pull-up;
 212                         slew-rate = <SLEW_RATE_SLOW>;
 213                         power-source = <IO_STANDARD_LVCMOS18>;
 214                 };
 215
 216                 mux {
 217                         groups = "i2c1_6_grp";
 218                         function = "i2c1";
 219                 };
 220         };
 221
 222         pinctrl_i2c1_gpio: i2c1-gpio {
 223                 conf {
 224                         groups = "gpio0_24_grp", "gpio0_25_grp";
 225                         slew-rate = <SLEW_RATE_SLOW>;
 226                         power-source = <IO_STANDARD_LVCMOS18>;
 227                 };
 228
 229                 mux {
 230                         groups = "gpio0_24_grp", "gpio0_25_grp";
 231                         function = "gpio0";
 232                 };
 233         };
 234
 235         pinctrl_gem3_default: gem3-default {
 236                 conf {
 237                         groups = "ethernet3_0_grp";
 238                         slew-rate = <SLEW_RATE_SLOW>;
 239                         power-source = <IO_STANDARD_LVCMOS18>;
 240                 };
 241
 242                 conf-rx {
 243                         pins = "MIO70", "MIO72", "MIO74";
 244                         bias-high-impedance;
 245                         low-power-disable;
 246                 };
 247
 248                 conf-bootstrap {
 249                         pins = "MIO71", "MIO73", "MIO75";
 250                         bias-disable;
 251                         low-power-disable;
 252                 };
 253
 254                 conf-tx {
 255                         pins = "MIO64", "MIO65", "MIO66",
 256                                 "MIO67", "MIO68", "MIO69";
 257                         bias-disable;
 258                         low-power-enable;
 259                 };
 260
 261                 conf-mdio {
 262                         groups = "mdio3_0_grp";
 263                         slew-rate = <SLEW_RATE_SLOW>;
 264                         power-source = <IO_STANDARD_LVCMOS18>;
 265                         bias-disable;
 266                 };
 267
 268                 mux-mdio {
 269                         function = "mdio3";
 270                         groups = "mdio3_0_grp";
 271                 };
 272
 273                 mux {
 274                         function = "ethernet3";
 275                         groups = "ethernet3_0_grp";
 276                 };
 277         };
 278
 279         pinctrl_usb0_default: usb0-default {
 280                 conf {
 281                         groups = "usb0_0_grp";
 282                         slew-rate = <SLEW_RATE_SLOW>;
 283                         power-source = <IO_STANDARD_LVCMOS18>;
 284                 };
 285
 286                 conf-rx {
 287                         pins = "MIO52", "MIO53", "MIO55";
 288                         bias-high-impedance;
 289                 };
 290
 291                 conf-tx {
 292                         pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
 293                         "MIO60", "MIO61", "MIO62", "MIO63";
 294                         bias-disable;
 295                 };
 296
 297                 mux {
 298                         groups = "usb0_0_grp";
 299                         function = "usb0";
 300                 };
 301         };
 302
 303         pinctrl_sdhci1_default: sdhci1-default {
 304                 conf {
 305                         groups = "sdio1_0_grp";
 306                         slew-rate = <SLEW_RATE_SLOW>;
 307                         power-source = <IO_STANDARD_LVCMOS18>;
 308                         bias-disable;
 309                 };
 310
 311                 conf-cd {
 312                         groups = "sdio1_cd_0_grp";
 313                         bias-high-impedance;
 314                         bias-pull-up;
 315                         slew-rate = <SLEW_RATE_SLOW>;
 316                         power-source = <IO_STANDARD_LVCMOS18>;
 317                 };
 318
 319                 mux-cd {
 320                         groups = "sdio1_cd_0_grp";
 321                         function = "sdio1_cd";
 322                 };
 323
 324                 mux {
 325                         groups = "sdio1_0_grp";
 326                         function = "sdio1";
 327                 };
 328         };
 329 };
 330
 331 &uart1 {
 332         status = "okay";
 333         pinctrl-names = "default";
 334         pinctrl-0 = <&pinctrl_uart1_default>;
 335 };