arch/arm/dts/zynqmp-r5.dts

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * dts file for Xilinx ZynqMP R5
   4  *
   5  * (C) Copyright 2018, Xilinx, Inc.
   6  *
   7  * Michal Simek <michal.simek@xilinx.com>
   8  */
   9
  10 /dts-v1/;
  11
  12 / {
  13         #address-cells = <1>;
  14         #size-cells = <1>;
  15         compatible = "xlnx,zynqmp-r5";
  16         model = "Xilinx ZynqMP R5";
  17
  18         cpus {
  19                 #address-cells = <0x1>;
  20                 #size-cells = <0x0>;
  21
  22                 cpu@0 {
  23                         compatible = "arm,cortex-r5";
  24                         device_type = "cpu";
  25                         reg = <0>;
  26                 };
  27         };
  28
  29         aliases {
  30                 serial0 = &uart1;
  31         };
  32
  33         memory@0 {
  34                 device_type = "memory";
  35                 reg = <0x00000000 0x20000000>;
  36         };
  37
  38         chosen {
  39                 bootargs = "";
  40                 stdout-path = "serial0:115200n8";
  41         };
  42
  43         clk100: clk100 {
  44                 compatible = "fixed-clock";
  45                 #clock-cells = <0>;
  46                 clock-frequency = <100000000>;
  47                 u-boot,dm-pre-reloc;
  48         };
  49
  50         amba {
  51                 u-boot,dm-pre-reloc;
  52                 compatible = "simple-bus";
  53                 #address-cells = <1>;
  54                 #size-cells = <1>;
  55                 ranges;
  56
  57                 ttc0: timer@ff110000 {
  58                         compatible = "cdns,ttc";
  59                         status = "okay";
  60                         reg = <0xff110000 0x1000>;
  61                         timer-width = <32>;
  62                         clocks = <&clk100>;
  63                 };
  64
  65                 uart1: serial@ff010000 {
  66                         u-boot,dm-pre-reloc;
  67                         compatible = "cdns,uart-r1p12", "xlnx,xuartps";
  68                         reg = <0xff010000 0x1000>;
  69                         clock-names = "uart_clk", "pclk";
  70                         clocks = <&clk100 &clk100>;
  71                 };
  72         };
  73 };