arch/arm/dts/zynqmp-m-a2197-02-revA.dts

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * dts file for Xilinx Versal a2197 RevA System Controller
   4  *
   5  * (C) Copyright 2019, Xilinx, Inc.
   6  *
   7  * Michal Simek <michal.simek@amd.com>
   8  */
   9 /dts-v1/;
  10
  11 #include "zynqmp.dtsi"
  12 #include "zynqmp-clk-ccf.dtsi"
  13 #include <dt-bindings/gpio/gpio.h>
  14
  15 / {
  16         model = "Versal System Controller on a2197 Memory Char board RevA";
  17         compatible = "xlnx,zynqmp-m-a2197-02-revA", "xlnx,zynqmp-a2197-revA",
  18                      "xlnx,zynqmp-a2197", "xlnx,zynqmp";
  19
  20         aliases {
  21                 ethernet0 = &gem0;
  22                 i2c0 = &i2c0;
  23                 i2c1 = &i2c1;
  24                 mmc0 = &sdhci0;
  25                 mmc1 = &sdhci1;
  26                 nvmem0 = &eeprom;
  27                 rtc0 = &rtc;
  28                 serial0 = &uart0;
  29                 serial1 = &uart1;
  30                 serial2 = &dcc;
  31                 usb0 = &usb0;
  32                 usb1 = &usb1;
  33                 spi0 = &qspi;
  34         };
  35
  36         chosen {
  37                 bootargs = "earlycon";
  38                 stdout-path = "serial0:115200n8";
  39         };
  40
  41         memory@0 {
  42                 device_type = "memory";
  43                 reg = <0x0 0x0 0x0 0x80000000>; /* FIXME don't know how big memory is there */
  44         };
  45
  46         ina226-vcc-aux {
  47                 compatible = "iio-hwmon";
  48                 io-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>;
  49         };
  50         ina226-vcc-ram {
  51                 compatible = "iio-hwmon";
  52                 io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;
  53         };
  54         ina226-vcc1v1-lp4 {
  55                 compatible = "iio-hwmon";
  56                 io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;
  57         };
  58         ina226-vcc1v2-lp4 {
  59                 compatible = "iio-hwmon";
  60                 io-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>;
  61         };
  62         ina226-vdd1-1v8-lp4 {
  63                 compatible = "iio-hwmon";
  64                 io-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>;
  65         };
  66 };
  67
  68 &qspi {
  69         status = "okay";
  70         is-dual = <1>;
  71         flash@0 {
  72                 compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
  73                 #address-cells = <1>;
  74                 #size-cells = <1>;
  75                 reg = <0x0>;
  76                 spi-tx-bus-width = <4>;
  77                 spi-rx-bus-width = <4>;
  78                 spi-max-frequency = <108000000>;
  79         };
  80 };
  81
  82 &sdhci0 { /* emmc MIO 13-23 - with some settings  16GB */
  83         status = "okay";
  84         non-removable;
  85         disable-wp;
  86         bus-width = <8>;
  87         xlnx,mio-bank = <0>; /* FIXME tap delay */
  88 };
  89
  90 &uart0 { /* uart0 MIO38-39 */
  91         status = "okay";
  92 };
  93
  94 &uart1 { /* uart1 MIO40-41 */
  95         status = "okay";
  96 };
  97
  98 &sdhci1 { /* sd1 MIO45-51 cd in place */
  99         status = "disable";
 100         no-1-8-v;
 101         disable-wp;
 102         xlnx,mio-bank = <1>;
 103 };
 104
 105 &gem0 {
 106         status = "okay";
 107         phy-handle = <&phy0>;
 108         phy-mode = "sgmii";
 109         phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>;
 110         phy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */
 111                 reg = <0>;
 112         };
 113 };
 114
 115 &gpio {
 116         status = "okay";
 117         gpio-line-names = "SCLK_OUT", "MISO_MO1", "MO2", "MO3", "MOSI_MIO0", /* 0 - 4 */
 118                   "N_SS_OUT", "", "SYS_CTRL0", "SYS_CTRL1", "SYS_CTRL2", /* 5 - 9 */
 119                   "SYS_CTRL3", "SYS_CTRL4", "SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */
 120                   "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */
 121                   "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */
 122                   "", "RXD0_IN", "TXD0_OUT", "TXD1_OUT", "RXD1_IN", /* 25 - 29 */
 123                   "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */
 124                   "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */
 125                   "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */
 126                   "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */
 127                   "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */
 128                   "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */
 129                   "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */
 130                   "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */
 131                   "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */
 132                   "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
 133                   "", "", "", "", "", /* 78 - 79 */
 134                   "", "", "", "", "", /* 80 - 84 */
 135                   "", "", "", "", "", /* 85 -89 */
 136                   "", "", "", "", "", /* 90 - 94 */
 137                   "", "", "", "", "", /* 95 - 99 */
 138                   "", "", "", "", "", /* 100 - 104 */
 139                   "", "", "", "", "", /* 105 - 109 */
 140                   "", "", "", "", "", /* 110 - 114 */
 141                   "", "", "", "", "", /* 115 - 119 */
 142                   "", "", "", "", "", /* 120 - 124 */
 143                   "", "", "", "", "", /* 125 - 129 */
 144                   "", "", "", "", "", /* 130 - 134 */
 145                   "", "", "", "", "", /* 135 - 139 */
 146                   "", "", "", "", "", /* 140 - 144 */
 147                   "", "", "", "", "", /* 145 - 149 */
 148                   "", "", "", "", "", /* 150 - 154 */
 149                   "", "", "", "", "", /* 155 - 159 */
 150                   "", "", "", "", "", /* 160 - 164 */
 151                   "", "", "", "", "", /* 165 - 169 */
 152                   "", "", "", ""; /* 170 - 173 */
 153 };
 154
 155 &i2c0 { /* MIO 34-35 - can't stay here */
 156         status = "okay";
 157         clock-frequency = <400000>;
 158         i2c-mux@74 { /* u46 */
 159                 compatible = "nxp,pca9548";
 160                 #address-cells = <1>;
 161                 #size-cells = <0>;
 162                 reg = <0x74>;
 163                 /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */
 164                 i2c@0 { /* PMBUS  must be enabled via SW21 */
 165                         #address-cells = <1>;
 166                         #size-cells = <0>;
 167                         reg = <0>;
 168                         reg_vcc1v2_lp4: tps544@15 { /* u97 */
 169                                 compatible = "ti,tps544b25";
 170                                 reg = <0x15>;
 171                         };
 172                         reg_vcc1v1_lp4: tps544@16 { /* u95 */
 173                                 compatible = "ti,tps544b25";
 174                                 reg = <0x16>;
 175                         };
 176                         reg_vdd1_1v8_lp4: tps544@17 { /* u99 */
 177                                 compatible = "ti,tps544b25";
 178                                 reg = <0x17>;
 179                         };
 180                         /* UTIL_PMBUS connection */
 181                         reg_vcc1v8: tps544@13 { /* u92 */
 182                                 compatible = "ti,tps544b25";
 183                                 reg = <0x13>;
 184                         };
 185                         reg_vcc3v3: tps544@14 { /* u93 */
 186                                 compatible = "ti,tps544b25";
 187                                 reg = <0x14>;
 188                         };
 189                         reg_vcc5v0: tps544@1e { /* u94 */
 190                                 compatible = "ti,tps544b25";
 191                                 reg = <0x1e>;
 192                         };
 193                 };
 194                 i2c@1 { /* PMBUS_INA226 */
 195                         #address-cells = <1>;
 196                         #size-cells = <0>;
 197                         reg = <1>;
 198                         vcc_aux: ina226@42 { /* u86 */
 199                                 compatible = "ti,ina226";
 200                                 #io-channel-cells = <1>;
 201                                 label = "ina226-vcc-aux";
 202                                 reg = <0x42>;
 203                                 shunt-resistor = <5000>;
 204                         };
 205                         vcc_ram: ina226@43 { /* u81 */
 206                                 compatible = "ti,ina226";
 207                                 #io-channel-cells = <1>;
 208                                 label = "ina226-vcc-ram";
 209                                 reg = <0x43>;
 210                                 shunt-resistor = <5000>;
 211                         };
 212                         vcc1v1_lp4: ina226@46 { /* u96 */
 213                                 compatible = "ti,ina226";
 214                                 #io-channel-cells = <1>;
 215                                 label = "ina226-vcc1v1-lp4";
 216                                 reg = <0x46>;
 217                                 shunt-resistor = <5000>;
 218                         };
 219                         vcc1v2_lp4: ina226@47 { /* u98 */
 220                                 compatible = "ti,ina226";
 221                                 #io-channel-cells = <1>;
 222                                 label = "ina226-vcc1v2-lp4";
 223                                 reg = <0x47>;
 224                                 shunt-resistor = <5000>;
 225                         };
 226                         vdd1_1v8_lp4: ina226@48 { /* u100 */
 227                                 compatible = "ti,ina226";
 228                                 #io-channel-cells = <1>;
 229                                 label = "ina226-vdd1-1v8-lp4";
 230                                 reg = <0x48>;
 231                                 shunt-resistor = <5000>;
 232                         };
 233                 };
 234                 i2c@2 { /* PMBUS1 */
 235                         #address-cells = <1>;
 236                         #size-cells = <0>;
 237                         reg = <2>;
 238                         reg_vccint: tps53681@60 { /* u69 - 0xc0 */
 239                                 compatible = "ti,tps53681", "ti,tps53679";
 240                                 reg = <0x60>;
 241                         };
 242                         reg_vcc_pmc: tps544@7 { /* u80 */
 243                                 compatible = "ti,tps544b25";
 244                                 reg = <0x7>;
 245                         };
 246                         reg_vcc_ram: tps544@8 { /* u82 */
 247                                 compatible = "ti,tps544b25";
 248                                 reg = <0x8>;
 249                         };
 250                         reg_vcc_pslp: tps544@9 { /* u83 */
 251                                 compatible = "ti,tps544b25";
 252                                 reg = <0x9>;
 253                         };
 254                         reg_vcc_psfp: tps544@a { /* u84 */
 255                                 compatible = "ti,tps544b25";
 256                                 reg = <0xa>;
 257                         };
 258                         reg_vccaux: tps544@d { /* u85 */
 259                                 compatible = "ti,tps544b25";
 260                                 reg = <0xd>;
 261                         };
 262                         reg_vccaux_pmc: tps544@e { /* u87 */
 263                                 compatible = "ti,tps544b25";
 264                                 reg = <0xe>;
 265                         };
 266                         reg_vcco_500: tps544@f { /* u88 */
 267                                 compatible = "ti,tps544b25";
 268                                 reg = <0xf>;
 269                         };
 270                         reg_vcco_501: tps544@10 { /* u89 */
 271                                 compatible = "ti,tps544b25";
 272                                 reg = <0x10>;
 273                         };
 274                         reg_vcco_502: tps544@11 { /* u90 */
 275                                 compatible = "ti,tps544b25";
 276                                 reg = <0x11>;
 277                         };
 278                         reg_vcco_503: tps544@12 { /* u91 */
 279                                 compatible = "ti,tps544b25";
 280                                 reg = <0x12>;
 281                         };
 282                 };
 283                 i2c@3 { /* MEM PMBUS - FIXME bug in schematics */
 284                         #address-cells = <1>;
 285                         #size-cells = <0>;
 286                         /* reg = <3>; */
 287                 };
 288                 i2c@4 { /* LP_I2C_SM */
 289                         #address-cells = <1>;
 290                         #size-cells = <0>;
 291                         reg = <4>;
 292                         /* connected to U20G */
 293                 };
 294                 i2c@5 { /* C0_DDR4_RDIMM */
 295                         #address-cells = <1>;
 296                         #size-cells = <0>;
 297                         reg = <5>;
 298                 };
 299                 i2c@6 { /* C2_DDR5_RDIMM */
 300                         #address-cells = <1>;
 301                         #size-cells = <0>;
 302                         reg = <6>;
 303                 };
 304                 i2c@7 { /* C3_DDR4_UDIMM */
 305                         #address-cells = <1>;
 306                         #size-cells = <0>;
 307                         reg = <7>;
 308                 };
 309         };
 310 };
 311
 312 /* TODO sysctrl via J239 */
 313 /* TODO samtec J212G/H via J242 */
 314 /* TODO teensy via U30 PCA9543A bus 1 */
 315 &i2c1 { /* i2c1 MIO 36-37 */
 316         status = "okay";
 317         clock-frequency = <400000>;
 318
 319         /* Must be enabled via J242 */
 320         eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */
 321                 compatible = "atmel,24c02";
 322                 reg = <0x51>;
 323         };
 324
 325         i2c-mux@74 { /* u47 */
 326                 compatible = "nxp,pca9548";
 327                 #address-cells = <1>;
 328                 #size-cells = <0>;
 329                 reg = <0x74>;
 330                 /* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */
 331                 dc_i2c: i2c@0 { /* DC_I2C */
 332                         #address-cells = <1>;
 333                         #size-cells = <0>;
 334                         reg = <0>;
 335                         /* Use for storing information about SC board */
 336                         eeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */
 337                                 compatible = "atmel,24c08";
 338                                 reg = <0x54>;
 339                         };
 340                         si570_ref_clk: clock-generator@5d { /* u26 */
 341                                 #clock-cells = <0>;
 342                                 compatible = "silabs,si570";
 343                                 reg = <0x5d>; /* FIXME addr */
 344                                 temperature-stability = <50>;
 345                                 factory-fout = <33333333>;
 346                                 clock-frequency = <33333333>;
 347                                 clock-output-names = "REF_CLK"; /* FIXME */
 348                                 silabs,skip-recall;
 349                         };
 350                         /* Connection via Samtec U20D */
 351                         /* Use for storing information about X-PRC card */
 352                         x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */
 353                                 compatible = "atmel,24c02";
 354                                 reg = <0x52>;
 355                         };
 356
 357                         /* Use for setting up certain features on X-PRC card */
 358                         x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */
 359                                 compatible = "nxp,pca9534";
 360                                 reg = <0x22>;
 361                                 gpio-controller; /* IRQ not connected */
 362                                 #gpio-cells = <2>;
 363                                 gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4",
 364                                                   "", "", "", "";
 365                                 gtr_sel0 {
 366                                         gpio-hog;
 367                                         gpios = <0 0>;
 368                                         input; /* FIXME add meaning */
 369                                         line-name = "sw4_1";
 370                                 };
 371                                 gtr_sel1 {
 372                                         gpio-hog;
 373                                         gpios = <1 0>;
 374                                         input; /* FIXME add meaning */
 375                                         line-name = "sw4_2";
 376                                 };
 377                                 gtr_sel2 {
 378                                         gpio-hog;
 379                                         gpios = <2 0>;
 380                                         input; /* FIXME add meaning */
 381                                         line-name = "sw4_3";
 382                                 };
 383                                 gtr_sel3 {
 384                                         gpio-hog;
 385                                         gpios = <3 0>;
 386                                         input; /* FIXME add meaning */
 387                                         line-name = "sw4_4";
 388                                 };
 389                         };
 390                 };
 391                 i2c@2 { /* C0_DDR4 */
 392                         #address-cells = <1>;
 393                         #size-cells = <0>;
 394                         reg = <2>;
 395                         si570_c0_ddr4: clock-generator@55 { /* u4 */
 396                                 #clock-cells = <0>;
 397                                 compatible = "silabs,si570";
 398                                 reg = <0x55>;
 399                                 temperature-stability = <50>;
 400                                 factory-fout = <30000000>;
 401                                 clock-frequency = <30000000>;
 402                                 clock-output-names = "C0_DD4_SI570_CLK";
 403                         };
 404                 };
 405                 i2c@3 { /* C1_RLD3 */
 406                         #address-cells = <1>;
 407                         #size-cells = <0>;
 408                         reg = <3>;
 409                         si570_c1_lp4: clock-generator@55 { /* u7 */
 410                                 #clock-cells = <0>;
 411                                 compatible = "silabs,si570";
 412                                 reg = <0x55>;
 413                                 temperature-stability = <50>;
 414                                 factory-fout = <30000000>;
 415                                 clock-frequency = <30000000>;
 416                                 clock-output-names = "C1_RLD3_SI570_CLK";
 417                         };
 418                 };
 419                 i2c@4 { /* C2_DDR5 */
 420                         #address-cells = <1>;
 421                         #size-cells = <0>;
 422                         reg = <4>;
 423                         si570_c2_lp4: clock-generator@55 { /* u10 */
 424                                 #clock-cells = <0>;
 425                                 compatible = "silabs,si570";
 426                                 reg = <0x55>;
 427                                 temperature-stability = <50>;
 428                                 factory-fout = <30000000>;
 429                                 clock-frequency = <30000000>;
 430                                 clock-output-names = "C2_DDR5_SI570_CLK";
 431                         };
 432                 };
 433                 i2c@5 { /* C3_DDR4 */
 434                         #address-cells = <1>;
 435                         #size-cells = <0>;
 436                         reg = <5>;
 437                         si570_c3_lp4: clock-generator@55 { /* u15 */
 438                                 #clock-cells = <0>;
 439                                 compatible = "silabs,si570";
 440                                 reg = <0x55>;
 441                                 temperature-stability = <50>;
 442                                 factory-fout = <30000000>;
 443                                 clock-frequency = <30000000>;
 444                                 clock-output-names = "C3_LP4_SI570_CLK";
 445                         };
 446                 };
 447                 i2c@6 { /* HSDP_SI570 */
 448                         #address-cells = <1>;
 449                         #size-cells = <0>;
 450                         reg = <6>;
 451                         si570_hsdp: clock-generator@5d { /* u19 */
 452                                 #clock-cells = <0>;
 453                                 compatible = "silabs,si570";
 454                                 reg = <0x5d>;
 455                                 temperature-stability = <50>;
 456                                 factory-fout = <156250000>;
 457                                 clock-frequency = <156250000>;
 458                                 clock-output-names = "HSDP_SI570";
 459                         };
 460                 };
 461         };
 462 };
 463
 464 &usb0 {
 465         status = "okay";
 466 };
 467
 468 &dwc3_0 {
 469         status = "okay";
 470         dr_mode = "host";
 471         /* dr_mode = "peripheral"; */
 472         maximum-speed = "high-speed";
 473 };
 474
 475 &usb1 {
 476         status = "disabled"; /* not at mem board */
 477 };
 478
 479 &dwc3_1 {
 480         /delete-property/ phy-names ;
 481         /delete-property/ phys ;
 482         maximum-speed = "high-speed";
 483         snps,dis_u2_susphy_quirk ;
 484         snps,dis_u3_susphy_quirk ;
 485         status = "disabled";
 486 };