1 // SPDX-License-Identifier: GPL-2.0
3 * dts file for Xilinx Versal a2197 RevA System Controller
5 * (C) Copyright 2019, Xilinx, Inc.
7 * Michal Simek <michal.simek@xilinx.com>
11 #include "zynqmp.dtsi"
12 #include "zynqmp-clk-ccf.dtsi"
13 #include <dt-bindings/gpio/gpio.h>
16 model = "Versal System Controller on a2197 Memory Char board RevA";
17 compatible = "xlnx,zynqmp-m-a2197-01-revA", "xlnx,zynqmp-a2197-revA",
18 "xlnx,zynqmp-a2197", "xlnx,zynqmp";
37 bootargs = "earlycon";
38 stdout-path = "serial0:115200n8";
42 device_type = "memory";
43 reg = <0x0 0x0 0x0 0x80000000>; /* FIXME don't know how big memory is there */
47 compatible = "iio-hwmon";
48 io-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>;
51 compatible = "iio-hwmon";
52 io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;
55 compatible = "iio-hwmon";
56 io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;
59 compatible = "iio-hwmon";
60 io-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>;
63 compatible = "iio-hwmon";
64 io-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>;
67 compatible = "iio-hwmon";
68 io-channels = <&vcc0v6_lp4 0>, <&vcc0v6_lp4 1>, <&vcc0v6_lp4 2>, <&vcc0v6_lp4 3>;
76 compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
80 spi-tx-bus-width = <1>;
81 spi-rx-bus-width = <4>;
82 spi-max-frequency = <108000000>;
86 &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */
91 xlnx,mio-bank = <0>; /* FIXME tap delay */
94 &uart0 { /* uart0 MIO38-39 */
98 &uart1 { /* uart1 MIO40-41 */
102 &sdhci1 { /* sd1 MIO45-51 cd in place */
111 phy-handle = <&phy0>;
112 phy-mode = "sgmii"; /* DTG generates this properly 1512 */
113 phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>;
114 phy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */
116 /* xlnx,phy-type = <PHY_TYPE_SGMII>; */
122 gpio-line-names = "SCLK_OUT", "MISO_MO1", "MO2", "MO3", "MOSI_MIO0", /* 0 - 4 */
123 "N_SS_OUT", "", "SYS_CTRL0", "SYS_CTRL1", "SYS_CTRL2", /* 5 - 9 */
124 "SYS_CTRL3", "SYS_CTRL4", "SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */
125 "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */
126 "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */
127 "", "RXD0_IN", "TXD0_OUT", "TXD1_OUT", "RXD1_IN", /* 25 - 29 */
128 "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */
129 "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */
130 "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */
131 "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */
132 "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */
133 "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */
134 "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */
135 "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */
136 "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */
137 "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
138 "", "", "", "", "", /* 78 - 79 */
139 "", "", "", "", "", /* 80 - 84 */
140 "", "", "", "", "", /* 85 -89 */
141 "", "", "", "", "", /* 90 - 94 */
142 "", "", "", "", "", /* 95 - 99 */
143 "", "", "", "", "", /* 100 - 104 */
144 "", "", "", "", "", /* 105 - 109 */
145 "", "", "", "", "", /* 110 - 114 */
146 "", "", "", "", "", /* 115 - 119 */
147 "", "", "", "", "", /* 120 - 124 */
148 "", "", "", "", "", /* 125 - 129 */
149 "", "", "", "", "", /* 130 - 134 */
150 "", "", "", "", "", /* 135 - 139 */
151 "", "", "", "", "", /* 140 - 144 */
152 "", "", "", "", "", /* 145 - 149 */
153 "", "", "", "", "", /* 150 - 154 */
154 "", "", "", "", "", /* 155 - 159 */
155 "", "", "", "", "", /* 160 - 164 */
156 "", "", "", "", "", /* 165 - 169 */
157 "", "", "", ""; /* 170 - 174 */
160 &i2c0 { /* MIO 34-35 - can't stay here */
162 clock-frequency = <400000>;
163 i2c-mux@74 { /* u46 */
164 compatible = "nxp,pca9548";
165 #address-cells = <1>;
168 /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */
169 i2c@0 { /* PMBUS must be enabled via SW21 */
170 #address-cells = <1>;
173 reg_vcc1v2_lp4: tps544@15 { /* u97 */
174 compatible = "ti,tps544b25";
177 reg_vcc1v1_lp4: tps544@16 { /* u95 */
178 compatible = "ti,tps544b25";
181 reg_vdd1_1v8_lp4: tps544@17 { /* u99 */
182 compatible = "ti,tps544b25";
185 /* UTIL_PMBUS connection */
186 reg_vcc1v8: tps544@13 { /* u92 */
187 compatible = "ti,tps544b25";
190 reg_vcc3v3: tps544@14 { /* u93 */
191 compatible = "ti,tps544b25";
194 reg_vcc5v0: tps544@1e { /* u94 */
195 compatible = "ti,tps544b25";
199 i2c@1 { /* PMBUS_INA226 */
200 #address-cells = <1>;
203 vcc_aux: ina226@42 { /* u86 */
204 compatible = "ti,ina226";
205 #io-channel-cells = <1>;
206 label = "ina226-vcc-aux";
208 shunt-resistor = <5000>;
210 vcc_ram: ina226@43 { /* u81 */
211 compatible = "ti,ina226";
212 #io-channel-cells = <1>;
213 label = "ina226-vcc-ram";
215 shunt-resistor = <5000>;
217 vcc1v1_lp4: ina226@46 { /* u96 */
218 compatible = "ti,ina226";
219 #io-channel-cells = <1>;
220 label = "ina226-vcc1v1-lp4";
222 shunt-resistor = <5000>;
224 vcc1v2_lp4: ina226@47 { /* u98 */
225 compatible = "ti,ina226";
226 #io-channel-cells = <1>;
227 label = "ina226-vcc1v2-lp4";
229 shunt-resistor = <5000>;
231 vdd1_1v8_lp4: ina226@48 { /* u100 */
232 compatible = "ti,ina226";
233 #io-channel-cells = <1>;
234 label = "ina226-vdd1-1v8-lp4";
236 shunt-resistor = <5000>;
238 vcc0v6_lp4: ina226@49 { /* u101 */
239 compatible = "ti,ina226";
240 #io-channel-cells = <1>;
241 label = "ina226-vcc0v6-lp4";
243 shunt-resistor = <5000>;
247 #address-cells = <1>;
250 reg_vccint: tps53681@c0 { /* u69 */
251 compatible = "ti,tps53681", "ti,tps53679";
254 reg_vcc_pmc: tps544@7 { /* u80 */
255 compatible = "ti,tps544b25";
258 reg_vcc_ram: tps544@8 { /* u82 */
259 compatible = "ti,tps544b25";
262 reg_vcc_pslp: tps544@9 { /* u83 */
263 compatible = "ti,tps544b25";
266 reg_vcc_psfp: tps544@a { /* u84 */
267 compatible = "ti,tps544b25";
270 reg_vccaux: tps544@d { /* u85 */
271 compatible = "ti,tps544b25";
274 reg_vccaux_pmc: tps544@e { /* u87 */
275 compatible = "ti,tps544b25";
278 reg_vcco_500: tps544@f { /* u88 */
279 compatible = "ti,tps544b25";
282 reg_vcco_501: tps544@10 { /* u89 */
283 compatible = "ti,tps544b25";
286 reg_vcco_502: tps544@11 { /* u90 */
287 compatible = "ti,tps544b25";
290 reg_vcco_503: tps544@12 { /* u91 */
291 compatible = "ti,tps544b25";
295 i2c@3 { /* MEM PMBUS - FIXME bug in schematics */
296 #address-cells = <1>;
300 i2c@4 { /* LP_I2C_SM */
301 #address-cells = <1>;
304 /* connected to U20G */
310 /* TODO sysctrl via J239 */
311 /* TODO samtec J212G/H via J242 */
312 /* TODO teensy via U30 PCA9543A bus 1 */
313 &i2c1 { /* i2c1 MIO 36-37 */
315 clock-frequency = <400000>;
317 /* Must be enabled via J242 */
318 eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */
319 compatible = "atmel,24c02";
323 i2c-mux@74 { /* u47 */
324 compatible = "nxp,pca9548";
325 #address-cells = <1>;
328 /* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */
329 dc_i2c: i2c@0 { /* DC_I2C */
330 #address-cells = <1>;
333 /* Use for storing information about SC board */
334 eeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */
335 compatible = "atmel,24c08";
338 si570_ref_clk: clock-generator@5d { /* u26 */
340 compatible = "silabs,si570";
341 reg = <0x5d>; /* FIXME addr */
342 temperature-stability = <50>;
343 factory-fout = <33333333>;
344 clock-frequency = <33333333>;
345 clock-output-names = "REF_CLK"; /* FIXME */
348 /* Connection via Samtec U20D */
349 /* Use for storing information about X-PRC card */
350 x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */
351 compatible = "atmel,24c02";
355 /* Use for setting up certain features on X-PRC card */
356 x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */
357 compatible = "nxp,pca9534";
359 gpio-controller; /* IRQ not connected */
361 gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4",
366 input; /* FIXME add meaning */
372 input; /* FIXME add meaning */
378 input; /* FIXME add meaning */
384 input; /* FIXME add meaning */
390 #address-cells = <1>;
393 si570_c0_lp4: clock-generator@55 { /* u10 */
395 compatible = "silabs,si570";
397 temperature-stability = <50>;
398 factory-fout = <30000000>;
399 clock-frequency = <30000000>;
400 clock-output-names = "C0_LP4_SI570_CLK";
404 #address-cells = <1>;
407 si570_c1_lp4: clock-generator@5d { /* u10 */
409 compatible = "silabs,si570";
410 reg = <0x5d>; /* FIXME addr */
411 temperature-stability = <50>;
412 factory-fout = <30000000>;
413 clock-frequency = <30000000>;
414 clock-output-names = "C1_LP4_SI570_CLK";
418 #address-cells = <1>;
421 si570_c2_lp4: clock-generator@55 { /* u10 */
423 compatible = "silabs,si570";
425 temperature-stability = <50>;
426 factory-fout = <30000000>;
427 clock-frequency = <30000000>;
428 clock-output-names = "C2_LP4_SI570_CLK";
432 #address-cells = <1>;
435 si570_c3_lp4: clock-generator@55 { /* u15 */
437 compatible = "silabs,si570";
439 temperature-stability = <50>;
440 factory-fout = <30000000>;
441 clock-frequency = <30000000>;
442 clock-output-names = "C3_LP4_SI570_CLK";
445 i2c@6 { /* HSDP_SI570 */
446 #address-cells = <1>;
449 si570_hsdp: clock-generator@5d { /* u19 */
451 compatible = "silabs,si570";
452 reg = <0x5d>; /* FIXME addr */
453 temperature-stability = <50>;
454 factory-fout = <156250000>;
455 clock-frequency = <156250000>;
456 clock-output-names = "HSDP_SI570";
464 xlnx,usb-polarity = <0>;
465 xlnx,usb-reset-mode = <0>;
471 /* dr_mode = "peripheral"; */
472 maximum-speed = "high-speed";
476 status = "disabled"; /* not at mem board */
477 xlnx,usb-polarity = <0>;
478 xlnx,usb-reset-mode = <0>;
482 /delete-property/ phy-names ;
483 /delete-property/ phys ;
484 maximum-speed = "high-speed";
485 snps,dis_u2_susphy_quirk ;
486 snps,dis_u3_susphy_quirk ;