arch/arm/dts/zynqmp-dlc21-revA.dts

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * dts file for Xilinx ZynqMP DLC21 revA
   4  *
   5  * (C) Copyright 2019 - 2021, Xilinx, Inc.
   6  *
   7  * Michal Simek <michal.simek@xilinx.com>
   8  */
   9 /dts-v1/;
  10
  11 #include "zynqmp.dtsi"
  12 #include "zynqmp-clk-ccf.dtsi"
  13 #include <dt-bindings/gpio/gpio.h>
  14 #include <dt-bindings/phy/phy.h>
  15 #include <include/dt-bindings/gpio/gpio.h>
  16
  17 / {
  18         model = "Smartlynq+ DLC21 RevA";
  19         compatible = "xlnx,zynqmp-dlc21-revA", "xlnx,zynqmp-dlc21",
  20                      "xlnx,zynqmp";
  21
  22         aliases {
  23                 ethernet0 = &gem0;
  24                 gpio0 = &gpio;
  25                 i2c0 = &i2c0;
  26                 mmc0 = &sdhci0;
  27                 mmc1 = &sdhci1;
  28                 rtc0 = &rtc;
  29                 serial0 = &uart0;
  30                 serial2 = &dcc;
  31                 usb0 = &usb0;
  32                 usb1 = &usb1;
  33                 spi0 = &spi0;
  34                 nvmem0 = &eeprom;
  35         };
  36
  37         chosen {
  38                 bootargs = "earlycon";
  39                 stdout-path = "serial0:115200n8";
  40         };
  41
  42         memory@0 {
  43                 device_type = "memory";
  44                 reg = <0 0 0 0x80000000>, <0x8 0 0x3 0x80000000>;
  45         };
  46
  47         si5332_1: si5332_1 { /* clk0_sgmii - u142 */
  48                 compatible = "fixed-clock";
  49                 #clock-cells = <0>;
  50                 clock-frequency = <125000000>;
  51         };
  52
  53         si5332_2: si5332_2 { /* clk1_usb - u142 */
  54                 compatible = "fixed-clock";
  55                 #clock-cells = <0>;
  56                 clock-frequency = <26000000>;
  57         };
  58 };
  59
  60 &sdhci0 { /* emmc MIO 13-23 - with some settings  16GB */
  61         status = "okay";
  62         non-removable;
  63         disable-wp;
  64         bus-width = <8>;
  65         xlnx,mio_bank = <0>;
  66 };
  67
  68 &sdhci1 { /* sd1 MIO45-51 cd in place */
  69         status = "okay";
  70         no-1-8-v;
  71         disable-wp;
  72         xlnx,mio_bank = <1>;
  73 };
  74
  75 &psgtr {
  76         status = "okay";
  77         /* sgmii, usb3 */
  78         clocks = <&si5332_1>, <&si5332_2>;
  79         clock-names = "ref0", "ref1";
  80 };
  81
  82 &uart0 { /* uart0 MIO38-39 */
  83         status = "okay";
  84         u-boot,dm-pre-reloc;
  85 };
  86
  87 &gem0 {
  88         status = "okay";
  89         phy-handle = <&phy0>;
  90         phy-mode = "sgmii"; /* DTG generates this properly  1512 */
  91         is-internal-pcspma;
  92         /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */
  93         phy0: ethernet-phy@0 {
  94                 reg = <0>;
  95         };
  96 };
  97
  98 &gpio {
  99         status = "okay";
 100         gpio-line-names = "", "", "", "", "", /* 0 - 4 */
 101                   "", "", "", "", "", /* 5 - 9 */
 102                   "", "", "", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */
 103                   "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */
 104                   "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */
 105                   "", "DISP_SCL", "DISP_DC_B", "DISP_RES_B", "DISP_CS_B", /* 25 - 29 */
 106                   "", "DISP_SDI", "SYSTEM_RST_R_B", "", "I2C0_SCL", /* 30 - 34 */
 107                   "I2C0_SDA", "", "", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */
 108                   "", "", "ETH_RESET_B", "", "", /* 40 - 44 */
 109                   "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */
 110                   "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */
 111                   "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */
 112                   "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */
 113                   "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */
 114                   "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */
 115                   "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
 116                   "", "", /* 78 - 79 */
 117                   "", "", "", "", "", /* 80 - 84 */
 118                   "", "", "", "", "", /* 85 -89 */
 119                   "", "", "", "", "", /* 90 - 94 */
 120                   "", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */
 121                   "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */
 122                   "", "", "", "", "", /* 105 - 109 */
 123                   "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */
 124                   "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */
 125                   "", "", "", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */
 126                   "SYSCTLR_UTIL_2V5_EN", "", "", "", "", /* 125 - 129 */
 127                   "", "", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "", /* 130 - 134 */
 128                   "", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */
 129                   "", "", "SYSCTLR_ETH_RESET_B", "", "", /* 140 - 144 */
 130                   "", "", "", "", "", /* 145 - 149 */
 131                   "", "", "", "", "", /* 150 - 154 */
 132                   "", "", "", "", "", /* 155 - 159 */
 133                   "", "", "", "", "", /* 160 - 164 */
 134                   "", "", "", "", "", /* 165 - 169 */
 135                   "", "", "", ""; /* 170 - 174 */
 136 };
 137
 138 &i2c0 { /* MIO34/35 */
 139         status = "okay";
 140         clock-frequency = <400000>;
 141
 142         jtag_vref: mcp4725@62 {
 143                 compatible = "microchip,mcp4725";
 144                 reg = <0x62>;
 145                 vref-millivolt = <3300>;
 146         };
 147
 148         eeprom: eeprom@50 { /* u46 */
 149                 compatible = "atmel,24c32";
 150                 reg = <0x50>;
 151         };
 152         /* u138 - TUSB320IRWBR - for USB-C */
 153 };
 154
 155
 156 &usb0 {
 157         status = "okay";
 158         xlnx,usb-polarity = <0>;
 159         xlnx,usb-reset-mode = <0>;
 160 };
 161
 162 &dwc3_0 {
 163         status = "okay";
 164         dr_mode = "peripheral";
 165         snps,dis_u2_susphy_quirk;
 166         snps,dis_u3_susphy_quirk;
 167         maximum-speed = "super-speed";
 168         phy-names = "usb3-phy";
 169         phys = <&psgtr 1 PHY_TYPE_USB3 0 1>;
 170 };
 171
 172 &usb1 {
 173         status = "disabled"; /* Any unknown issue with USB-C */
 174         xlnx,usb-polarity = <0>;
 175         xlnx,usb-reset-mode = <0>;
 176 };
 177
 178 &dwc3_1 {
 179         /delete-property/ phy-names ;
 180         /delete-property/ phys ;
 181         dr_mode = "host";
 182         maximum-speed = "high-speed";
 183         snps,dis_u2_susphy_quirk ;
 184         snps,dis_u3_susphy_quirk ;
 185         status = "okay";
 186 };
 187
 188 &xilinx_ams {
 189         status = "okay";
 190 };
 191
 192 &ams_ps {
 193         status = "okay";
 194 };
 195
 196 &ams_pl {
 197         status = "okay";
 198 };
 199
 200 &spi0 {
 201         status = "okay";
 202         is-decoded-cs = <0>;
 203         num-cs = <1>;
 204         u-boot,dm-pre-reloc;
 205         displayspi@0 {
 206                 compatible = "syncoam,seps525";
 207                 u-boot,dm-pre-reloc;
 208                 reg = <0>;
 209                 status = "okay";
 210                 spi-max-frequency = <10000000>;
 211                 spi-cpol;
 212                 spi-cpha;
 213                 rotate = <0>;
 214                 fps = <50>;
 215                 buswidth = <8>;
 216                 txbuflen = <64000>;
 217                 reset-gpios = <&gpio 0x1c GPIO_ACTIVE_LOW>;
 218                 dc-gpios = <&gpio 0x1b GPIO_ACTIVE_HIGH>;
 219                 debug = <0>;
 220         };
 221 };