1 // SPDX-License-Identifier: GPL-2.0+
3 * Clock specification for Xilinx ZynqMP
5 * (C) Copyright 2015 - 2018, Xilinx, Inc.
7 * Michal Simek <michal.simek@xilinx.com>
12 compatible = "fixed-clock";
14 clock-frequency = <100000000>;
19 compatible = "fixed-clock";
21 clock-frequency = <125000000>;
25 compatible = "fixed-clock";
27 clock-frequency = <200000000>;
32 compatible = "fixed-clock";
34 clock-frequency = <250000000>;
38 compatible = "fixed-clock";
40 clock-frequency = <300000000>;
45 compatible = "fixed-clock";
47 clock-frequency = <600000000>;
51 compatible = "fixed-clock";
53 clock-frequency = <100000000>;
54 clock-accuracy = <100>;
58 compatible = "fixed-clock";
60 clock-frequency = <24576000>;
61 clock-accuracy = <100>;
64 dpdma_clk: dpdma_clk {
65 compatible = "fixed-clock";
67 clock-frequency = <533000000>;
70 drm_clock: drm_clock {
71 compatible = "fixed-clock";
73 clock-frequency = <262750000>;
74 clock-accuracy = <0x64>;
79 clocks = <&clk100 &clk100>;
83 clocks = <&clk100 &clk100>;
87 clocks = <&clk600>, <&clk100>;
91 clocks = <&clk600>, <&clk100>;
95 clocks = <&clk600>, <&clk100>;
99 clocks = <&clk600>, <&clk100>;
103 clocks = <&clk600>, <&clk100>;
107 clocks = <&clk600>, <&clk100>;
111 clocks = <&clk600>, <&clk100>;
115 clocks = <&clk600>, <&clk100>;
119 clocks = <&clk600>, <&clk100>;
123 clocks = <&clk600>, <&clk100>;
127 clocks = <&clk600>, <&clk100>;
131 clocks = <&clk600>, <&clk100>;
135 clocks = <&clk600>, <&clk100>;
139 clocks = <&clk600>, <&clk100>;
143 clocks = <&clk600>, <&clk100>;
147 clocks = <&clk600>, <&clk100>;
151 clocks = <&clk100 &clk100>;
155 clocks = <&clk125>, <&clk125>, <&clk125>;
159 clocks = <&clk125>, <&clk125>, <&clk125>;
163 clocks = <&clk125>, <&clk125>, <&clk125>;
167 clocks = <&clk125>, <&clk125>, <&clk125>;
183 clocks = <&clk300 &clk300>;
191 clocks = <&clk200 &clk200>;
195 clocks = <&clk200 &clk200>;
199 clocks = <&clk200 &clk200>;
203 clocks = <&clk200 &clk200>;
207 clocks = <&clk100 &clk100>;
211 clocks = <&clk100 &clk100>;
215 clocks = <&clk250>, <&clk250>;
219 clocks = <&clk250>, <&clk250>;
227 clocks = <&drm_clock>;
231 clocks = <&dp_aclk>, <&dp_aud_clk>;
235 clocks = <&dpdma_clk>;
238 &xlnx_dp_snd_codec0 {
239 clocks = <&dp_aud_clk>;