arch/arm/dts/zynqmp-clk.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Clock specification for Xilinx ZynqMP
   4  *
   5  * (C) Copyright 2015 - 2018, Xilinx, Inc.
   6  *
   7  * Michal Simek <michal.simek@xilinx.com>
   8  */
   9
  10 / {
  11         clk100: clk100 {
  12                 compatible = "fixed-clock";
  13                 #clock-cells = <0>;
  14                 clock-frequency = <100000000>;
  15                 u-boot,dm-pre-reloc;
  16         };
  17
  18         clk125: clk125 {
  19                 compatible = "fixed-clock";
  20                 #clock-cells = <0>;
  21                 clock-frequency = <125000000>;
  22         };
  23
  24         clk200: clk200 {
  25                 compatible = "fixed-clock";
  26                 #clock-cells = <0>;
  27                 clock-frequency = <200000000>;
  28                 u-boot,dm-pre-reloc;
  29         };
  30
  31         clk250: clk250 {
  32                 compatible = "fixed-clock";
  33                 #clock-cells = <0>;
  34                 clock-frequency = <250000000>;
  35         };
  36
  37         clk300: clk300 {
  38                 compatible = "fixed-clock";
  39                 #clock-cells = <0>;
  40                 clock-frequency = <300000000>;
  41                 u-boot,dm-pre-reloc;
  42         };
  43
  44         clk600: clk600 {
  45                 compatible = "fixed-clock";
  46                 #clock-cells = <0>;
  47                 clock-frequency = <600000000>;
  48         };
  49
  50         dp_aclk: clock0 {
  51                 compatible = "fixed-clock";
  52                 #clock-cells = <0>;
  53                 clock-frequency = <100000000>;
  54                 clock-accuracy = <100>;
  55         };
  56
  57         dp_aud_clk: clock1 {
  58                 compatible = "fixed-clock";
  59                 #clock-cells = <0>;
  60                 clock-frequency = <24576000>;
  61                 clock-accuracy = <100>;
  62         };
  63
  64         dpdma_clk: dpdma_clk {
  65                 compatible = "fixed-clock";
  66                 #clock-cells = <0x0>;
  67                 clock-frequency = <533000000>;
  68         };
  69
  70         drm_clock: drm_clock {
  71                 compatible = "fixed-clock";
  72                 #clock-cells = <0x0>;
  73                 clock-frequency = <262750000>;
  74                 clock-accuracy = <0x64>;
  75         };
  76 };
  77
  78 &can0 {
  79         clocks = <&clk100 &clk100>;
  80 };
  81
  82 &can1 {
  83         clocks = <&clk100 &clk100>;
  84 };
  85
  86 &fpd_dma_chan1 {
  87         clocks = <&clk600>, <&clk100>;
  88 };
  89
  90 &fpd_dma_chan2 {
  91         clocks = <&clk600>, <&clk100>;
  92 };
  93
  94 &fpd_dma_chan3 {
  95         clocks = <&clk600>, <&clk100>;
  96 };
  97
  98 &fpd_dma_chan4 {
  99         clocks = <&clk600>, <&clk100>;
 100 };
 101
 102 &fpd_dma_chan5 {
 103         clocks = <&clk600>, <&clk100>;
 104 };
 105
 106 &fpd_dma_chan6 {
 107         clocks = <&clk600>, <&clk100>;
 108 };
 109
 110 &fpd_dma_chan7 {
 111         clocks = <&clk600>, <&clk100>;
 112 };
 113
 114 &fpd_dma_chan8 {
 115         clocks = <&clk600>, <&clk100>;
 116 };
 117
 118 &lpd_dma_chan1 {
 119         clocks = <&clk600>, <&clk100>;
 120 };
 121
 122 &lpd_dma_chan2 {
 123         clocks = <&clk600>, <&clk100>;
 124 };
 125
 126 &lpd_dma_chan3 {
 127         clocks = <&clk600>, <&clk100>;
 128 };
 129
 130 &lpd_dma_chan4 {
 131         clocks = <&clk600>, <&clk100>;
 132 };
 133
 134 &lpd_dma_chan5 {
 135         clocks = <&clk600>, <&clk100>;
 136 };
 137
 138 &lpd_dma_chan6 {
 139         clocks = <&clk600>, <&clk100>;
 140 };
 141
 142 &lpd_dma_chan7 {
 143         clocks = <&clk600>, <&clk100>;
 144 };
 145
 146 &lpd_dma_chan8 {
 147         clocks = <&clk600>, <&clk100>;
 148 };
 149
 150 &nand0 {
 151         clocks = <&clk100 &clk100>;
 152 };
 153
 154 &gem0 {
 155         clocks = <&clk125>, <&clk125>, <&clk125>;
 156 };
 157
 158 &gem1 {
 159         clocks = <&clk125>, <&clk125>, <&clk125>;
 160 };
 161
 162 &gem2 {
 163         clocks = <&clk125>, <&clk125>, <&clk125>;
 164 };
 165
 166 &gem3 {
 167         clocks = <&clk125>, <&clk125>, <&clk125>;
 168 };
 169
 170 &gpio {
 171         clocks = <&clk100>;
 172 };
 173
 174 &i2c0 {
 175         clocks = <&clk100>;
 176 };
 177
 178 &i2c1 {
 179         clocks = <&clk100>;
 180 };
 181
 182 &qspi {
 183         clocks = <&clk300 &clk300>;
 184 };
 185
 186 &sata {
 187         clocks = <&clk250>;
 188 };
 189
 190 &sdhci0 {
 191         clocks = <&clk200 &clk200>;
 192 };
 193
 194 &sdhci1 {
 195         clocks = <&clk200 &clk200>;
 196 };
 197
 198 &spi0 {
 199         clocks = <&clk200 &clk200>;
 200 };
 201
 202 &spi1 {
 203         clocks = <&clk200 &clk200>;
 204 };
 205
 206 &uart0 {
 207         clocks = <&clk100 &clk100>;
 208 };
 209
 210 &uart1 {
 211         clocks = <&clk100 &clk100>;
 212 };
 213
 214 &usb0 {
 215         clocks = <&clk250>, <&clk250>;
 216 };
 217
 218 &usb1 {
 219         clocks = <&clk250>, <&clk250>;
 220 };
 221
 222 &watchdog0 {
 223         clocks = <&clk100>;
 224 };
 225
 226 &xilinx_drm {
 227         clocks = <&drm_clock>;
 228 };
 229
 230 &xlnx_dp {
 231         clocks = <&dp_aclk>, <&dp_aud_clk>;
 232 };
 233
 234 &xlnx_dpdma {
 235         clocks = <&dpdma_clk>;
 236 };
 237
 238 &xlnx_dp_snd_codec0 {
 239         clocks = <&dp_aud_clk>;
 240 };