1 // SPDX-License-Identifier: GPL-2.0+
3 * Clock specification for Xilinx ZynqMP
5 * (C) Copyright 2017 - 2020, Xilinx, Inc.
7 * Michal Simek <michal.simek@xilinx.com>
10 #include <dt-bindings/clock/xlnx-zynqmp-clk.h>
14 compatible = "xlnx,fclk";
15 clocks = <&zynqmp_clk PL0_REF>;
20 compatible = "xlnx,fclk";
21 clocks = <&zynqmp_clk PL1_REF>;
26 compatible = "xlnx,fclk";
27 clocks = <&zynqmp_clk PL2_REF>;
32 compatible = "xlnx,fclk";
33 clocks = <&zynqmp_clk PL3_REF>;
36 pss_ref_clk: pss_ref_clk {
38 compatible = "fixed-clock";
40 clock-frequency = <33333333>;
43 video_clk: video_clk {
45 compatible = "fixed-clock";
47 clock-frequency = <27000000>;
50 pss_alt_ref_clk: pss_alt_ref_clk {
52 compatible = "fixed-clock";
54 clock-frequency = <0>;
57 gt_crx_ref_clk: gt_crx_ref_clk {
59 compatible = "fixed-clock";
61 clock-frequency = <108000000>;
64 aux_ref_clk: aux_ref_clk {
66 compatible = "fixed-clock";
68 clock-frequency = <27000000>;
72 compatible = "fixed-clock";
74 clock-frequency = <100000000>;
75 clock-accuracy = <100>;
80 zynqmp_clk: clock-controller {
83 compatible = "xlnx,zynqmp-clk";
84 clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>,
85 <&aux_ref_clk>, <>_crx_ref_clk>;
86 clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk",
87 "aux_ref_clk", "gt_crx_ref_clk";
92 clocks = <&zynqmp_clk CAN0_REF>, <&zynqmp_clk LPD_LSBUS>;
96 clocks = <&zynqmp_clk CAN1_REF>, <&zynqmp_clk LPD_LSBUS>;
100 clocks = <&zynqmp_clk ACPU>;
104 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
108 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
112 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
116 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
120 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
124 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
128 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
132 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
136 clocks = <&zynqmp_clk GPU_REF>, <&zynqmp_clk GPU_PP0_REF>, <&zynqmp_clk GPU_PP1_REF>;
140 clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
144 clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
148 clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
152 clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
156 clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
160 clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
164 clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
168 clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
172 clocks = <&zynqmp_clk NAND_REF>, <&zynqmp_clk LPD_LSBUS>;
176 clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>,
177 <&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>,
178 <&zynqmp_clk GEM_TSU>;
179 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
183 clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>,
184 <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>,
185 <&zynqmp_clk GEM_TSU>;
186 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
190 clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>,
191 <&zynqmp_clk GEM2_TX>, <&zynqmp_clk GEM2_RX>,
192 <&zynqmp_clk GEM_TSU>;
193 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
197 clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>,
198 <&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>,
199 <&zynqmp_clk GEM_TSU>;
200 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
204 clocks = <&zynqmp_clk LPD_LSBUS>;
208 clocks = <&zynqmp_clk I2C0_REF>;
212 clocks = <&zynqmp_clk I2C1_REF>;
216 clocks = <&zynqmp_clk PCIE_REF>;
220 clocks = <&zynqmp_clk QSPI_REF>, <&zynqmp_clk LPD_LSBUS>;
224 clocks = <&zynqmp_clk SATA_REF>;
228 clocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>;
232 clocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>;
236 clocks = <&zynqmp_clk SPI0_REF>, <&zynqmp_clk LPD_LSBUS>;
240 clocks = <&zynqmp_clk SPI1_REF>, <&zynqmp_clk LPD_LSBUS>;
244 clocks = <&zynqmp_clk LPD_LSBUS>;
248 clocks = <&zynqmp_clk LPD_LSBUS>;
252 clocks = <&zynqmp_clk LPD_LSBUS>;
256 clocks = <&zynqmp_clk LPD_LSBUS>;
260 clocks = <&zynqmp_clk UART0_REF>, <&zynqmp_clk LPD_LSBUS>;
264 clocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>;
268 clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
272 clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
276 clocks = <&zynqmp_clk WDT>;
280 clocks = <&zynqmp_clk LPD_WDT>;
284 clocks = <&zynqmp_clk AMS_REF>;
288 clocks = <&dp_aclk>, <&zynqmp_clk DP_AUDIO_REF>, <&zynqmp_clk DP_VIDEO_REF>;
292 clocks = <&zynqmp_clk DPDMA_REF>;
295 &zynqmp_dp_snd_codec0 {
296 clocks = <&zynqmp_clk DP_AUDIO_REF>;
300 clocks = <&zynqmp_clk PCAP>;