arch/arm/dts/zynq-microzed.dts

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Xilinx MicroZED board DTS
   4  *
   5  * Copyright (C) 2013 - 2016 Xilinx, Inc.
   6  */
   7 /dts-v1/;
   8 #include "zynq-7000.dtsi"
   9
  10 / {
  11         model = "Avnet MicroZed board";
  12         compatible = "avnet,zynq-microzed", "xlnx,zynq-microzed", "xlnx,zynq-7000";
  13
  14         aliases {
  15                 serial0 = &uart1;
  16                 spi0 = &qspi;
  17                 mmc0 = &sdhci0;
  18         };
  19
  20         memory@0 {
  21                 device_type = "memory";
  22                 reg = <0x0 0x40000000>;
  23         };
  24
  25         chosen {
  26                 bootargs = "earlycon";
  27                 stdout-path = "serial0:115200n8";
  28         };
  29
  30         usb_phy0: phy0 {
  31                 compatible = "usb-nop-xceiv";
  32                 #phy-cells = <0>;
  33         };
  34 };
  35
  36 &clkc {
  37         ps-clk-frequency = <33333333>;
  38 };
  39
  40 &qspi {
  41         bootph-all;
  42         status = "okay";
  43 };
  44
  45 &gem0 {
  46         status = "okay";
  47         phy-mode = "rgmii-id";
  48         phy-handle = <&ethernet_phy>;
  49
  50         ethernet_phy: ethernet-phy@0 {
  51                 reg = <0>;
  52         };
  53 };
  54
  55 &sdhci0 {
  56         bootph-all;
  57         status = "okay";
  58 };
  59
  60 &uart1 {
  61         bootph-all;
  62         status = "okay";
  63 };
  64
  65 &usb0 {
  66         status = "okay";
  67         dr_mode = "host";
  68         usb-phy = <&usb_phy0>;
  69         pinctrl-names = "default";
  70         pinctrl-0 = <&pinctrl_usb0_default>;
  71 };
  72
  73 &pinctrl0 {
  74         pinctrl_usb0_default: usb0-default {
  75                 mux {
  76                         groups = "usb0_0_grp";
  77                         function = "usb0";
  78                 };
  79
  80                 conf {
  81                         groups = "usb0_0_grp";
  82                         slew-rate = <0>;
  83                         io-standard = <1>;
  84                 };
  85
  86                 conf-rx {
  87                         pins = "MIO29", "MIO31", "MIO36";
  88                         bias-high-impedance;
  89                 };
  90
  91                 conf-tx {
  92                         pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34",
  93                                "MIO35", "MIO37", "MIO38", "MIO39";
  94                         bias-disable;
  95                 };
  96         };
  97 };