1 // SPDX-License-Identifier: GPL-2.0+
3 * Xilinx CSE NOR board DTS
5 * Copyright (C) 2018 Xilinx, Inc.
12 model = "Zynq CSE NOR Board";
13 compatible = "xlnx,zynq-cse-nor", "xlnx,zynq-7000";
20 device_type = "memory";
21 reg = <0xFFFC0000 0x40000>;
25 stdout-path = "serial0:115200n8";
29 compatible = "arm,dcc";
36 compatible = "simple-bus";
45 compatible = "xlnx,zynq-slcr", "syscon", "simple-bus";
46 reg = <0xF8000000 0x1000>;
51 compatible = "xlnx,ps7-clkc";
52 clock-output-names = "armpll", "ddrpll",
54 "cpu_3or2x", "cpu_2x", "cpu_1x",
55 "ddr2x", "ddr3x", "dci",
56 "lqspi", "smc", "pcap", "gem0",
57 "gem1", "fclk0", "fclk1",
58 "fclk2", "fclk3", "can0",
59 "can1", "sdio0", "sdio1",
60 "uart0", "uart1", "spi0",
61 "spi1", "dma", "usb0_aper",
62 "usb1_aper", "gem0_aper",
63 "gem1_aper", "sdio0_aper",
64 "sdio1_aper", "spi0_aper",
65 "spi1_aper", "can0_aper",
66 "can1_aper", "i2c0_aper",
67 "i2c1_aper", "uart0_aper",
68 "uart1_aper", "gpio_aper",
69 "lqspi_aper", "smc_aper",
70 "swdt", "dbg_trc", "dbg_apb";
76 * This is partially hack because it is normally subnode of smcc
77 * but for mini U-Boot there is no reason to enable SMCC driver
78 * which does almost nothing in NOR flash configuration that's
79 * why place cfi-flash directly here.
83 compatible = "cfi-flash";
84 reg = <0xe2000000 0x2000000>;