1 // SPDX-License-Identifier: GPL-2.0+
3 * Xilinx Zynq 7000 DTSI
4 * Describes the hardware common to all Zynq 7000-based boards.
6 * Copyright (C) 2011 - 2015 Xilinx
12 compatible = "xlnx,zynq-7000";
19 compatible = "arm,cortex-a9";
23 clock-latency = <1000>;
24 cpu0-supply = <®ulator_vccpint>;
33 compatible = "arm,cortex-a9";
40 fpga_full: fpga-full {
41 compatible = "fpga-region";
49 compatible = "arm,cortex-a9-pmu";
50 interrupts = <0 5 4>, <0 6 4>;
51 interrupt-parent = <&intc>;
52 reg = <0xf8891000 0x1000>,
56 regulator_vccpint: fixedregulator {
57 compatible = "regulator-fixed";
58 regulator-name = "VCCPINT";
59 regulator-min-microvolt = <1000000>;
60 regulator-max-microvolt = <1000000>;
66 compatible = "arm,coresight-static-replicator";
67 clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
68 clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
74 /* replicator output ports */
77 replicator_out_port0: endpoint {
78 remote-endpoint = <&tpiu_in_port>;
83 replicator_out_port1: endpoint {
84 remote-endpoint = <&etb_in_port>;
89 /* replicator input port */
91 replicator_in_port0: endpoint {
92 remote-endpoint = <&funnel_out_port>;
100 compatible = "simple-bus";
101 #address-cells = <1>;
103 interrupt-parent = <&intc>;
107 compatible = "xlnx,zynq-xadc-1.00.a";
108 reg = <0xf8007100 0x20>;
109 interrupts = <0 7 4>;
110 interrupt-parent = <&intc>;
115 compatible = "xlnx,zynq-can-1.0";
117 clocks = <&clkc 19>, <&clkc 36>;
118 clock-names = "can_clk", "pclk";
119 reg = <0xe0008000 0x1000>;
120 interrupts = <0 28 4>;
121 interrupt-parent = <&intc>;
122 tx-fifo-depth = <0x40>;
123 rx-fifo-depth = <0x40>;
127 compatible = "xlnx,zynq-can-1.0";
129 clocks = <&clkc 20>, <&clkc 37>;
130 clock-names = "can_clk", "pclk";
131 reg = <0xe0009000 0x1000>;
132 interrupts = <0 51 4>;
133 interrupt-parent = <&intc>;
134 tx-fifo-depth = <0x40>;
135 rx-fifo-depth = <0x40>;
138 gpio0: gpio@e000a000 {
139 compatible = "xlnx,zynq-gpio-1.0";
143 interrupt-controller;
144 #interrupt-cells = <2>;
145 interrupt-parent = <&intc>;
146 interrupts = <0 20 4>;
147 reg = <0xe000a000 0x1000>;
151 compatible = "cdns,i2c-r1p10";
154 interrupt-parent = <&intc>;
155 interrupts = <0 25 4>;
156 reg = <0xe0004000 0x1000>;
157 #address-cells = <1>;
162 compatible = "cdns,i2c-r1p10";
165 interrupt-parent = <&intc>;
166 interrupts = <0 48 4>;
167 reg = <0xe0005000 0x1000>;
168 #address-cells = <1>;
172 intc: interrupt-controller@f8f01000 {
173 compatible = "arm,cortex-a9-gic";
174 #interrupt-cells = <3>;
175 interrupt-controller;
176 reg = <0xF8F01000 0x1000>,
180 L2: cache-controller@f8f02000 {
181 compatible = "arm,pl310-cache";
182 reg = <0xF8F02000 0x1000>;
183 interrupts = <0 2 4>;
184 arm,data-latency = <3 2 2>;
185 arm,tag-latency = <2 2 2>;
190 mc: memory-controller@f8006000 {
191 compatible = "xlnx,zynq-ddrc-a05";
192 reg = <0xf8006000 0x1000>;
195 uart0: serial@e0000000 {
196 compatible = "xlnx,xuartps", "cdns,uart-r1p8";
198 clocks = <&clkc 23>, <&clkc 40>;
199 clock-names = "uart_clk", "pclk";
200 reg = <0xE0000000 0x1000>;
201 interrupts = <0 27 4>;
204 uart1: serial@e0001000 {
205 compatible = "xlnx,xuartps", "cdns,uart-r1p8";
207 clocks = <&clkc 24>, <&clkc 41>;
208 clock-names = "uart_clk", "pclk";
209 reg = <0xE0001000 0x1000>;
210 interrupts = <0 50 4>;
214 compatible = "xlnx,zynq-spi-r1p6";
215 reg = <0xe0006000 0x1000>;
217 interrupt-parent = <&intc>;
218 interrupts = <0 26 4>;
219 clocks = <&clkc 25>, <&clkc 34>;
220 clock-names = "ref_clk", "pclk";
221 #address-cells = <1>;
226 compatible = "xlnx,zynq-spi-r1p6";
227 reg = <0xe0007000 0x1000>;
229 interrupt-parent = <&intc>;
230 interrupts = <0 49 4>;
231 clocks = <&clkc 26>, <&clkc 35>;
232 clock-names = "ref_clk", "pclk";
233 #address-cells = <1>;
238 clock-names = "ref_clk", "pclk";
239 clocks = <&clkc 10>, <&clkc 43>;
240 compatible = "xlnx,zynq-qspi-1.0";
242 interrupt-parent = <&intc>;
243 interrupts = <0 19 4>;
244 reg = <0xe000d000 0x1000>;
245 #address-cells = <1>;
249 gem0: ethernet@e000b000 {
250 compatible = "cdns,zynq-gem", "cdns,gem";
251 reg = <0xe000b000 0x1000>;
253 interrupts = <0 22 4>;
254 clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
255 clock-names = "pclk", "hclk", "tx_clk";
256 #address-cells = <1>;
260 gem1: ethernet@e000c000 {
261 compatible = "cdns,zynq-gem", "cdns,gem";
262 reg = <0xe000c000 0x1000>;
264 interrupts = <0 45 4>;
265 clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
266 clock-names = "pclk", "hclk", "tx_clk";
267 #address-cells = <1>;
271 smcc: memory-controller@e000e000 {
272 compatible = "arm,pl353-smc-r2p1", "arm,primecell";
273 reg = <0xe000e000 0x0001000>;
275 clock-names = "memclk", "apb_pclk";
276 clocks = <&clkc 11>, <&clkc 44>;
277 ranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */
278 0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */
279 0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */
280 #address-cells = <2>;
282 interrupt-parent = <&intc>;
283 interrupts = <0 18 4>;
285 nfc0: nand-controller@0,0 {
286 compatible = "arm,pl353-nand-r2p1";
287 reg = <0 0 0x1000000>;
289 #address-cells = <1>;
294 compatible = "cfi-flash";
295 reg = <1 0 0x2000000>;
296 #address-cells = <1>;
301 sdhci0: mmc@e0100000 {
302 compatible = "arasan,sdhci-8.9a";
304 clock-names = "clk_xin", "clk_ahb";
305 clocks = <&clkc 21>, <&clkc 32>;
306 interrupt-parent = <&intc>;
307 interrupts = <0 24 4>;
308 reg = <0xe0100000 0x1000>;
311 sdhci1: mmc@e0101000 {
312 compatible = "arasan,sdhci-8.9a";
314 clock-names = "clk_xin", "clk_ahb";
315 clocks = <&clkc 22>, <&clkc 33>;
316 interrupt-parent = <&intc>;
317 interrupts = <0 47 4>;
318 reg = <0xe0101000 0x1000>;
321 slcr: slcr@f8000000 {
323 #address-cells = <1>;
325 compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
326 reg = <0xF8000000 0x1000>;
331 compatible = "xlnx,ps7-clkc";
333 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
334 "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
335 "dci", "lqspi", "smc", "pcap", "gem0", "gem1",
336 "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
337 "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
338 "dma", "usb0_aper", "usb1_aper", "gem0_aper",
339 "gem1_aper", "sdio0_aper", "sdio1_aper",
340 "spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
341 "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
342 "gpio_aper", "lqspi_aper", "smc_aper", "swdt",
343 "dbg_trc", "dbg_apb";
348 compatible = "xlnx,zynq-reset";
354 pinctrl0: pinctrl@700 {
355 compatible = "xlnx,pinctrl-zynq";
361 dmac_s: dmac@f8003000 {
362 compatible = "arm,pl330", "arm,primecell";
363 reg = <0xf8003000 0x1000>;
364 interrupt-parent = <&intc>;
365 interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3",
366 "dma4", "dma5", "dma6", "dma7";
367 interrupts = <0 13 4>,
376 clock-names = "apb_pclk";
379 devcfg: devcfg@f8007000 {
380 compatible = "xlnx,zynq-devcfg-1.0";
381 interrupt-parent = <&intc>;
382 interrupts = <0 8 4>;
383 reg = <0xf8007000 0x100>;
384 clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>;
385 clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3";
389 efuse: efuse@f800d000 {
390 compatible = "xlnx,zynq-efuse";
391 reg = <0xf800d000 0x20>;
394 global_timer: timer@f8f00200 {
395 compatible = "arm,cortex-a9-global-timer";
396 reg = <0xf8f00200 0x20>;
397 interrupts = <1 11 0x301>;
398 interrupt-parent = <&intc>;
402 ttc0: timer@f8001000 {
403 interrupt-parent = <&intc>;
404 interrupts = <0 10 4>, <0 11 4>, <0 12 4>;
405 compatible = "cdns,ttc";
407 reg = <0xF8001000 0x1000>;
410 ttc1: timer@f8002000 {
411 interrupt-parent = <&intc>;
412 interrupts = <0 37 4>, <0 38 4>, <0 39 4>;
413 compatible = "cdns,ttc";
415 reg = <0xF8002000 0x1000>;
418 scutimer: timer@f8f00600 {
419 interrupt-parent = <&intc>;
420 interrupts = <1 13 0x301>;
421 compatible = "arm,cortex-a9-twd-timer";
422 reg = <0xf8f00600 0x20>;
427 compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
430 interrupt-parent = <&intc>;
431 interrupts = <0 21 4>;
432 reg = <0xe0002000 0x1000>;
437 compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
440 interrupt-parent = <&intc>;
441 interrupts = <0 44 4>;
442 reg = <0xe0003000 0x1000>;
446 watchdog0: watchdog@f8005000 {
448 compatible = "cdns,wdt-r1p2";
449 interrupt-parent = <&intc>;
450 interrupts = <0 9 1>;
451 reg = <0xf8005000 0x1000>;
456 compatible = "arm,coresight-etb10", "arm,primecell";
457 reg = <0xf8801000 0x1000>;
458 clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
459 clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
462 etb_in_port: endpoint {
463 remote-endpoint = <&replicator_out_port1>;
470 compatible = "arm,coresight-tpiu", "arm,primecell";
471 reg = <0xf8803000 0x1000>;
472 clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
473 clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
476 tpiu_in_port: endpoint {
477 remote-endpoint = <&replicator_out_port0>;
484 compatible = "arm,coresight-static-funnel", "arm,primecell";
485 reg = <0xf8804000 0x1000>;
486 clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
487 clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
489 /* funnel output ports */
492 funnel_out_port: endpoint {
494 <&replicator_in_port0>;
500 #address-cells = <1>;
503 /* funnel input ports */
506 funnel0_in_port0: endpoint {
507 remote-endpoint = <&ptm0_out_port>;
513 funnel0_in_port1: endpoint {
514 remote-endpoint = <&ptm1_out_port>;
520 funnel0_in_port2: endpoint {
523 /* The other input ports are not connect to anything */
528 compatible = "arm,coresight-etm3x", "arm,primecell";
529 reg = <0xf889c000 0x1000>;
530 clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
531 clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
535 ptm0_out_port: endpoint {
536 remote-endpoint = <&funnel0_in_port0>;
543 compatible = "arm,coresight-etm3x", "arm,primecell";
544 reg = <0xf889d000 0x1000>;
545 clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
546 clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
550 ptm1_out_port: endpoint {
551 remote-endpoint = <&funnel0_in_port1>;